cleanup sources and prepare for 2.6.27

SVN-Revision: 13660

3 files changed, 103 insertions, 12 deletions

diff --git a/target/linux/ifxmips/patches/000-mips-bad-intctl.patch b/target/linux/ifxmips/patches/000-mips-bad-intctl.patch
new file mode 100644
index 0000000..3b1c2dc
--- /dev/null
+++ b/target/linux/ifxmips/patches/000-mips-bad-intctl.patch
@@ -0,0 +1,34 @@
+--- a/arch/mips/kernel/traps.c
++++ b/arch/mips/kernel/traps.c
+@@ -1464,7 +1464,16 @@ void __cpuinit per_cpu_trap_init(void)
+ 	 */
+ 	if (cpu_has_mips_r2) {
+ 		cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
++		if (!cp0_compare_irq)
++			cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
++
+ 		cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
++		if (!cp0_perfcount_irq)
++			cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
++
++		if (arch_fixup_c0_irqs)
++			arch_fixup_c0_irqs();
++
+ 		if (cp0_perfcount_irq == cp0_compare_irq)
+ 			cp0_perfcount_irq = -1;
+ 	} else {
+--- a/include/asm-mips/irq.h
++++ b/include/asm-mips/irq.h
+@@ -156,8 +156,12 @@ extern void free_irqno(unsigned int irq)
+  * IE7.  Since R2 their number has to be read from the c0_intctl register.
+  */
+ #define CP0_LEGACY_COMPARE_IRQ 7
++#define CP0_LEGACY_PERFCNT_IRQ 7
+ 
+ extern int cp0_compare_irq;
+ extern int cp0_perfcount_irq;
+ 
++extern void __weak arch_fixup_c0_irqs(void);
++
++
+ #endif /* _ASM_IRQ_H */
diff --git a/target/linux/ifxmips/patches/010-mips_clocksource_init_war.patch b/target/linux/ifxmips/patches/010-mips_clocksource_init_war.patch
new file mode 100644
index 0000000..61d9610
--- /dev/null
+++ b/target/linux/ifxmips/patches/010-mips_clocksource_init_war.patch
@@ -0,0 +1,65 @@
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -13,6 +13,22 @@
+ #include <asm/smtc_ipi.h>
+ #include <asm/time.h>
+ 
++/*
++ * Compare interrupt can be routed and latched outside the core,
++ * so a single execution hazard barrier may not be enough to give
++ * it time to clear as seen in the Cause register.  4 time the
++ * pipeline depth seems reasonably conservative, and empirically
++ * works better in configurations with high CPU/bus clock ratios.
++ */
++
++#define compare_change_hazard() \
++	do { \
++		irq_disable_hazard(); \
++		irq_disable_hazard(); \
++		irq_disable_hazard(); \
++		irq_disable_hazard(); \
++	} while (0)
++
+ static int mips_next_event(unsigned long delta,
+                            struct clock_event_device *evt)
+ {
+@@ -28,6 +44,7 @@ static int mips_next_event(unsigned long
+ 	cnt = read_c0_count();
+ 	cnt += delta;
+ 	write_c0_compare(cnt);
++	compare_change_hazard();
+ 	res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
+ #ifdef CONFIG_MIPS_MT_SMTC
+ 	evpe(vpflags);
+@@ -187,7 +204,7 @@ static int c0_compare_int_usable(void)
+ 	 */
+ 	if (c0_compare_int_pending()) {
+ 		write_c0_compare(read_c0_count());
+-		irq_disable_hazard();
++		compare_change_hazard();
+ 		if (c0_compare_int_pending())
+ 			return 0;
+ 	}
+@@ -196,7 +213,7 @@ static int c0_compare_int_usable(void)
+ 		cnt = read_c0_count();
+ 		cnt += delta;
+ 		write_c0_compare(cnt);
+-		irq_disable_hazard();
++		compare_change_hazard();
+ 		if ((int)(read_c0_count() - cnt) < 0)
+ 		    break;
+ 		/* increase delta if the timer was already expired */
+@@ -205,11 +222,12 @@ static int c0_compare_int_usable(void)
+ 	while ((int)(read_c0_count() - cnt) <= 0)
+ 		;	/* Wait for expiry  */
+ 
++	compare_change_hazard();
+ 	if (!c0_compare_int_pending())
+ 		return 0;
+ 
+ 	write_c0_compare(read_c0_count());
+-	irq_disable_hazard();
++	compare_change_hazard();
+ 	if (c0_compare_int_pending())
+ 		return 0;
+ 
diff --git a/target/linux/ifxmips/patches/100-board.patch b/target/linux/ifxmips/patches/100-board.patch
index e33a470..052a08a 100644
--- a/target/linux/ifxmips/patches/100-board.patch
+++ b/target/linux/ifxmips/patches/100-board.patch
@@ -1,6 +1,6 @@
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -78,6 +78,21 @@ config MIPS_COBALT
+@@ -78,6 +78,23 @@ config MIPS_COBALT
  	select SYS_SUPPORTS_LITTLE_ENDIAN
  	select GENERIC_HARDIRQS_NO__DO_IRQ
  
@@ -11,9 +11,11 @@
 +	select CEVT_R4K
 +	select CSRC_R4K
 +	select SYS_HAS_CPU_MIPS32_R1
++	select SYS_HAS_CPU_MIPS32_R2
 +	select HAVE_STD_PC_SERIAL_PORT
 +	select SYS_SUPPORTS_BIG_ENDIAN
 +	select SYS_SUPPORTS_32BIT_KERNEL
++	select SYS_SUPPORTS_MULTITHREADING
 +	select SYS_HAS_EARLY_PRINTK
 +	select HW_HAS_PCI
 +	select GENERIC_GPIO
@@ -22,7 +24,7 @@
  config MACH_DECSTATION
  	bool "DECstations"
  	select BOOT_ELF32
-@@ -697,6 +712,7 @@ source "arch/mips/sibyte/Kconfig"
+@@ -697,6 +714,7 @@ source "arch/mips/sibyte/Kconfig"
  source "arch/mips/tx4927/Kconfig"
  source "arch/mips/tx4938/Kconfig"
  source "arch/mips/vr41xx/Kconfig"
@@ -61,16 +63,6 @@
  #define CL_SIZE			COMMAND_LINE_SIZE
  
  extern char *system_type;
---- a/arch/mips/kernel/traps.c
-+++ b/arch/mips/kernel/traps.c
-@@ -1464,6 +1464,7 @@ void __cpuinit per_cpu_trap_init(void)
- 	 */
- 	if (cpu_has_mips_r2) {
- 		cp0_compare_irq = (read_c0_intctl() >> 29) & 7;
-+		cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
- 		cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7;
- 		if (cp0_perfcount_irq == cp0_compare_irq)
- 			cp0_perfcount_irq = -1;
 --- a/arch/mips/pci/Makefile
 +++ b/arch/mips/pci/Makefile
 @@ -48,3 +48,4 @@ obj-$(CONFIG_TOSHIBA_RBTX4938)	+= fixup-