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authorLuka Perkov <luka@openwrt.org>2013-10-16 03:25:57 +0000
committerLuka Perkov <luka@openwrt.org>2013-10-16 03:25:57 +0000
commit0a0ac79cb7f6c3e4968e2b5b8e0a7a251b2e6f2e (patch)
tree3cc5242d8af40bb2e4a754a6ac31e8e48d8b66e4 /target/linux/imx6/patches-3.10
parent365ed4d22f8353db53c18aba7f37fea7871de2b4 (diff)
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imx6: add support for gw52xx
The Gateworks GW51xx family of products is based on the Freescale i.MX6DL SoC and offers a small form-factor with peripherals such as: * i.MX6DL 512MB DDR3 * 256MB NAND FLASH * 2x PCIe * 1x USB EHCI (to PCIe socket2) * 1x USB OTG (to front panel or PCIe socket1) * 1x uSD * LVDS * HDMI AudioVideo out * Analog Video in * Digital IO * Gateworks System Controller Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 38425
Diffstat (limited to 'target/linux/imx6/patches-3.10')
-rw-r--r--target/linux/imx6/patches-3.10/113-gw52xx.patch57
1 files changed, 57 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.10/113-gw52xx.patch b/target/linux/imx6/patches-3.10/113-gw52xx.patch
new file mode 100644
index 0000000..4663a3b
--- /dev/null
+++ b/target/linux/imx6/patches-3.10/113-gw52xx.patch
@@ -0,0 +1,57 @@
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -120,6 +120,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
+ imx6q-gw5400-a.dtb \
+ imx6q-gw54xx.dtb \
+ imx6dl-gw51xx.dtb \
++ imx6dl-gw52xx.dtb \
+ imx6q-sabreauto.dtb \
+ imx6q-sabrelite.dtb \
+ imx6q-sabresd.dtb \
+--- a/arch/arm/boot/dts/imx6dl.dtsi
++++ b/arch/arm/boot/dts/imx6dl.dtsi
+@@ -37,6 +37,18 @@
+ compatible = "fsl,imx6dl-iomuxc";
+ reg = <0x020e0000 0x4000>;
+
++ /* shared pinctrl settings */
++ audmux {
++ pinctrl_audmux_1: audmux-1 {
++ fsl,pins = <
++ MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
++ MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
++ MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
++ MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
++ >;
++ };
++ };
++
+ enet {
+ pinctrl_enet_1: enetgrp-1 {
+ fsl,pins = <
+@@ -197,6 +209,12 @@
+ MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
+ >;
+ };
++ pinctrl_uart2_3: uart2grp-3 {
++ fsl,pins = <
++ MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ >;
++ };
+ };
+
+ uart3 {
+@@ -227,6 +245,12 @@
+ };
+
+ usbotg {
++ pinctrl_usbotg_1: usbotggrp-1 {
++ fsl,pins = <
++ MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
++
+ pinctrl_usbotg_2: usbotggrp-2 {
+ fsl,pins = <
+ MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059