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| author | John Crispin <john@openwrt.org> | 2015-04-03 19:06:30 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-04-03 19:06:30 +0000 |
| commit | 5d52f4b51d223f245e27e6386e099ac8b5385b62 (patch) | |
| tree | e0ec2775726a5912e7e34877cd37e41aa000c18b /target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch | |
| parent | 114338003a6619582a594c4156da989e7afe102a (diff) | |
| download | mtk-20170518-5d52f4b51d223f245e27e6386e099ac8b5385b62.zip mtk-20170518-5d52f4b51d223f245e27e6386e099ac8b5385b62.tar.gz mtk-20170518-5d52f4b51d223f245e27e6386e099ac8b5385b62.tar.bz2 | |
ipq806x: add platform usb support
This change adds DWC3 QCOM USB phys and TCSR drivers. These are
cherry-picked from the following LKML threads:
*dwc3 qcom: https://lkml.org/lkml/2014/9/12/599
*tcsr: https://lkml.org/lkml/2015/2/9/579
We're also adding an additional patch to add the corresponding dev nodes
in the IPQ806x and AP148 dts files.
Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
SVN-Revision: 45261
Diffstat (limited to 'target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch b/target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch new file mode 100644 index 0000000..322e1d9 --- /dev/null +++ b/target/linux/ipq806x/patches-3.18/103-ARM-DT-ipq8064-Add-TCSR-support.patch @@ -0,0 +1,65 @@ +--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi ++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi +@@ -132,6 +132,7 @@ + + gsbi2: gsbi@12480000 { + compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <2>; + reg = <0x12480000 0x100>; + clocks = <&gcc GSBI2_H_CLK>; + clock-names = "iface"; +@@ -140,6 +141,8 @@ + ranges; + status = "disabled"; + ++ syscon-tcsr = <&tcsr>; ++ + uart2: serial@12490000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x12490000 0x1000>, +@@ -167,6 +170,7 @@ + + gsbi4: gsbi@16300000 { + compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <4>; + reg = <0x16300000 0x100>; + clocks = <&gcc GSBI4_H_CLK>; + clock-names = "iface"; +@@ -175,6 +179,8 @@ + ranges; + status = "disabled"; + ++ syscon-tcsr = <&tcsr>; ++ + uart4: serial@16340000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x16340000 0x1000>, +@@ -201,6 +207,7 @@ + + gsbi5: gsbi@1a200000 { + compatible = "qcom,gsbi-v1.0.0"; ++ cell-index = <5>; + reg = <0x1a200000 0x100>; + clocks = <&gcc GSBI5_H_CLK>; + clock-names = "iface"; +@@ -209,6 +216,8 @@ + ranges; + status = "disabled"; + ++ syscon-tcsr = <&tcsr>; ++ + uart5: serial@1a240000 { + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; + reg = <0x1a240000 0x1000>, +@@ -279,6 +288,11 @@ + status = "disabled"; + }; + ++ tcsr: syscon@1a400000 { ++ compatible = "qcom,tcsr-ipq8064", "syscon"; ++ reg = <0x1a400000 0x100>; ++ }; ++ + qcom,ssbi@500000 { + compatible = "qcom,ssbi"; + reg = <0x00500000 0x1000>; |