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authorFelix Fietkau <nbd@openwrt.org>2015-08-04 23:09:55 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-08-04 23:09:55 +0000
commitf7651fdba51fae235bb9e43fcecc0478faf927d0 (patch)
treedf2c2dfd4c247210c9ba11828619b5eaf1584b91 /target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
parentc4c986e419d7098104681c364978d065a3b7f2e1 (diff)
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ipq806x: fix pcie pinmux naming in ipq806x dts
PCIe controller nodes are numbers 0/1/2 in the chipset dtsi file, but the pinmux nodes are numbers 1/2/3. We'll make it consistent by changing the pinmux numbering to match the controller's one. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46556
Diffstat (limited to 'target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch')
-rw-r--r--target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch31
1 files changed, 12 insertions, 19 deletions
diff --git a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index 80ac25f..bdc91fb 100644
--- a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -15,11 +15,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -30,6 +30,22 @@
+@@ -35,6 +35,22 @@
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -27,7 +27,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
-@@ -133,5 +149,19 @@
+@@ -138,5 +154,19 @@
usb30@1 {
status = "ok";
};
@@ -46,14 +46,14 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -64,7 +64,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -80,7 +80,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie3_pins: pcie3_pinmux {
++ pcie2_pins: pcie2_pinmux {
+ mux {
+ pins = "gpio63";
+ drive-strength = <2>;
@@ -99,21 +99,21 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie2: pci@1b900000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 63 0>;
-+ pinctrl-0 = <&pcie3_pins>;
++ pinctrl-0 = <&pcie2_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -259,10 +259,3 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
hs_phy_1: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
-@@ -389,6 +514,5 @@
- dr_mode = "host";
- };
- };
--
- };
- };