ipq806x: fix pcie with linux 4.9

Signed-off-by: Felix Fietkau <nbd@nbd.name>

2 files changed, 311 insertions, 3 deletions

diff --git a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
index 381f6cf..a6d7df5 100644
--- a/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/target/linux/ipq806x/files-4.9/arch/arm/boot/dts/qcom-ipq8064.dtsi
@@ -737,7 +737,7 @@
 		};
 
 		pcie0: pci@1b500000 {
-			compatible = "qcom,pcie-v0";
+			compatible = "qcom,pcie-ipq8064";
 			reg = <0x1b500000 0x1000
 			       0x1b502000 0x80
 			       0x1b600000 0x100
@@ -789,7 +789,7 @@
 		};
 
 		pcie1: pci@1b700000 {
-			compatible = "qcom,pcie-v0";
+			compatible = "qcom,pcie-ipq8064";
 			reg = <0x1b700000 0x1000
 			       0x1b702000 0x80
 			       0x1b800000 0x100
@@ -841,7 +841,7 @@
 		};
 
 		pcie2: pci@1b900000 {
-			compatible = "qcom,pcie-v0";
+			compatible = "qcom,pcie-ipq8064";
 			reg = <0x1b900000 0x1000
 			       0x1b902000 0x80
 			       0x1ba00000 0x100
diff --git a/target/linux/ipq806x/patches-4.9/0071-pcie-qcom-fixes.patch b/target/linux/ipq806x/patches-4.9/0071-pcie-qcom-fixes.patch
new file mode 100644
index 0000000..dd403e2
--- /dev/null
+++ b/target/linux/ipq806x/patches-4.9/0071-pcie-qcom-fixes.patch
@@ -0,0 +1,308 @@
+--- a/drivers/pci/host/pcie-qcom.c
++++ b/drivers/pci/host/pcie-qcom.c
+@@ -36,8 +36,50 @@
+ 
+ #include "pcie-designware.h"
+ 
++/* DBI registers */
++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0		0x818
++#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1		0x81c
++
++#define PCIE20_PLR_IATU_VIEWPORT		0x900
++#define PCIE20_PLR_IATU_REGION_OUTBOUND		(0x0 << 31)
++#define PCIE20_PLR_IATU_REGION_INDEX(x)		(x << 0)
++
++#define PCIE20_PLR_IATU_CTRL1			0x904
++#define PCIE20_PLR_IATU_TYPE_CFG0		(0x4 << 0)
++#define PCIE20_PLR_IATU_TYPE_MEM		(0x0 << 0)
++
++#define PCIE20_PLR_IATU_CTRL2			0x908
++#define PCIE20_PLR_IATU_ENABLE			BIT(31)
++
++#define PCIE20_PLR_IATU_LBAR			0x90C
++#define PCIE20_PLR_IATU_UBAR			0x910
++#define PCIE20_PLR_IATU_LAR			0x914
++#define PCIE20_PLR_IATU_LTAR			0x918
++#define PCIE20_PLR_IATU_UTAR			0x91c
++
++#define MSM_PCIE_DEV_CFG_ADDR			0x01000000
++
++/* PARF registers */
++#define PCIE20_PARF_PCS_DEEMPH			0x34
++#define PCS_DEEMPH_TX_DEEMPH_GEN1(x)		(x << 16)
++#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x)	(x << 8)
++#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x)	(x << 0)
++
++#define PCIE20_PARF_PCS_SWING			0x38
++#define PCS_SWING_TX_SWING_FULL(x)		(x << 8)
++#define PCS_SWING_TX_SWING_LOW(x)		(x << 0)
++
+ #define PCIE20_PARF_PHY_CTRL			0x40
++#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK	(0x1f << 16)
++#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)		(x << 16)
++
+ #define PCIE20_PARF_PHY_REFCLK			0x4C
++#define REF_SSP_EN				BIT(16)
++#define REF_USE_PAD				BIT(12)
++
++#define PCIE20_PARF_CONFIG_BITS			0x50
++#define PHY_RX0_EQ(x)				(x << 24)
++
+ #define PCIE20_PARF_DBI_BASE_ADDR		0x168
+ #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE		0x16c
+ #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT	0x178
+@@ -53,14 +95,18 @@ struct qcom_pcie_resources_v0 {
+ 	struct clk *iface_clk;
+ 	struct clk *core_clk;
+ 	struct clk *phy_clk;
++	struct clk *aux_clk;
++	struct clk *ref_clk;
+ 	struct reset_control *pci_reset;
+ 	struct reset_control *axi_reset;
+ 	struct reset_control *ahb_reset;
+ 	struct reset_control *por_reset;
+ 	struct reset_control *phy_reset;
++	struct reset_control *ext_reset;
+ 	struct regulator *vdda;
+ 	struct regulator *vdda_phy;
+ 	struct regulator *vdda_refclk;
++	uint8_t phy_tx0_term_offset;
+ };
+ 
+ struct qcom_pcie_resources_v1 {
+@@ -82,6 +128,7 @@ struct qcom_pcie;
+ struct qcom_pcie_ops {
+ 	int (*get_resources)(struct qcom_pcie *pcie);
+ 	int (*init)(struct qcom_pcie *pcie);
++	void (*configure)(struct qcom_pcie *pcie);
+ 	void (*deinit)(struct qcom_pcie *pcie);
+ };
+ 
+@@ -160,6 +207,14 @@ static int qcom_pcie_get_resources_v0(st
+ 	if (IS_ERR(res->phy_clk))
+ 		return PTR_ERR(res->phy_clk);
+ 
++	res->aux_clk = devm_clk_get(dev, "aux");
++	if (IS_ERR(res->aux_clk))
++		return PTR_ERR(res->aux_clk);
++
++	res->ref_clk = devm_clk_get(dev, "ref");
++	if (IS_ERR(res->ref_clk))
++		return PTR_ERR(res->ref_clk);
++
+ 	res->pci_reset = devm_reset_control_get(dev, "pci");
+ 	if (IS_ERR(res->pci_reset))
+ 		return PTR_ERR(res->pci_reset);
+@@ -180,6 +235,14 @@ static int qcom_pcie_get_resources_v0(st
+ 	if (IS_ERR(res->phy_reset))
+ 		return PTR_ERR(res->phy_reset);
+ 
++	res->ext_reset = devm_reset_control_get(dev, "ext");
++	if (IS_ERR(res->ext_reset))
++		return PTR_ERR(res->ext_reset);
++
++	if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
++				&res->phy_tx0_term_offset))
++		res->phy_tx0_term_offset = 0;
++
+ 	return 0;
+ }
+ 
+@@ -223,15 +286,69 @@ static void qcom_pcie_deinit_v0(struct q
+ 	reset_control_assert(res->axi_reset);
+ 	reset_control_assert(res->ahb_reset);
+ 	reset_control_assert(res->por_reset);
+-	reset_control_assert(res->pci_reset);
++	reset_control_assert(res->phy_reset);
++	reset_control_assert(res->ext_reset);
+ 	clk_disable_unprepare(res->iface_clk);
+ 	clk_disable_unprepare(res->core_clk);
+ 	clk_disable_unprepare(res->phy_clk);
++	clk_disable_unprepare(res->aux_clk);
++	clk_disable_unprepare(res->ref_clk);
+ 	regulator_disable(res->vdda);
+ 	regulator_disable(res->vdda_phy);
+ 	regulator_disable(res->vdda_refclk);
+ }
+ 
++static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
++{
++	struct pcie_port *pp = &pcie->pp;
++
++	/*
++	 * program and enable address translation region 0 (device config
++	 * address space); region type config;
++	 * axi config address range to device config address range
++	 */
++	writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
++	       PCIE20_PLR_IATU_REGION_INDEX(0),
++	       pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
++
++	writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
++	writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
++	writel(pp->cfg0_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
++	writel((pp->cfg0_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
++	writel((pp->cfg0_base + pp->cfg0_size - 1),
++	       pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
++	writel(busdev, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
++	writel(0, pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
++}
++
++static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
++{
++	struct pcie_port *pp = &pcie->pp;
++
++	/*
++	 * program and enable address translation region 2 (device resource
++	 * address space); region type memory;
++	 * axi device bar address range to device bar address range
++	 */
++	writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
++	       PCIE20_PLR_IATU_REGION_INDEX(2),
++	       pcie->pp.dbi_base + PCIE20_PLR_IATU_VIEWPORT);
++
++	writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL1);
++	writel(PCIE20_PLR_IATU_ENABLE, pcie->pp.dbi_base + PCIE20_PLR_IATU_CTRL2);
++	writel(pp->mem_base, pcie->pp.dbi_base + PCIE20_PLR_IATU_LBAR);
++	writel((pp->mem_base >> 32), pcie->pp.dbi_base + PCIE20_PLR_IATU_UBAR);
++	writel(pp->mem_base + pp->mem_size - 1,
++	       pcie->pp.dbi_base + PCIE20_PLR_IATU_LAR);
++	writel(pp->mem_bus_addr, pcie->pp.dbi_base + PCIE20_PLR_IATU_LTAR);
++	writel(upper_32_bits(pp->mem_bus_addr),
++	       pcie->pp.dbi_base + PCIE20_PLR_IATU_UTAR);
++
++	/* 256B PCIE buffer setting */
++	writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
++	writel(0x1, pcie->pp.dbi_base + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
++}
++
+ static int qcom_pcie_init_v0(struct qcom_pcie *pcie)
+ {
+ 	struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
+@@ -260,13 +377,19 @@ static int qcom_pcie_init_v0(struct qcom
+ 	ret = reset_control_assert(res->ahb_reset);
+ 	if (ret) {
+ 		dev_err(dev, "cannot assert ahb reset\n");
+-		goto err_assert_ahb;
++		goto err_assert_reset;
++	}
++
++	ret = reset_control_deassert(res->ext_reset);
++	if (ret) {
++		dev_err(dev, "cannot deassert ext reset\n");
++		goto err_assert_reset;
+ 	}
+ 
+ 	ret = clk_prepare_enable(res->iface_clk);
+ 	if (ret) {
+ 		dev_err(dev, "cannot prepare/enable iface clock\n");
+-		goto err_assert_ahb;
++		goto err_assert_reset;
+ 	}
+ 
+ 	ret = clk_prepare_enable(res->phy_clk);
+@@ -281,22 +404,53 @@ static int qcom_pcie_init_v0(struct qcom
+ 		goto err_clk_core;
+ 	}
+ 
++	ret = clk_prepare_enable(res->aux_clk);
++	if (ret) {
++		dev_err(dev, "cannot prepare/enable aux clock\n");
++		goto err_clk_aux;
++	}
++
++	ret = clk_prepare_enable(res->ref_clk);
++	if (ret) {
++		dev_err(dev, "cannot prepare/enable ref clock\n");
++		goto err_clk_ref;
++	}
++
+ 	ret = reset_control_deassert(res->ahb_reset);
+ 	if (ret) {
+ 		dev_err(dev, "cannot deassert ahb reset\n");
+ 		goto err_deassert_ahb;
+ 	}
++	udelay(1);
+ 
+ 	/* enable PCIe clocks and resets */
+ 	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
+ 	val &= ~BIT(0);
+ 	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
+ 
+-	/* enable external reference clock */
++	/* Set Tx termination offset */
++	val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
++	val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
++	val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset);
++	writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
++
++	/* PARF programming */
++	writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
++	       PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
++	       PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
++	       pcie->parf + PCIE20_PARF_PCS_DEEMPH);
++	writel(PCS_SWING_TX_SWING_FULL(0x78) |
++	       PCS_SWING_TX_SWING_LOW(0x78),
++	       pcie->parf + PCIE20_PARF_PCS_SWING);
++	writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
++
++	/* Enable reference clock */
+ 	val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
+-	val |= BIT(16);
++	val &= ~REF_USE_PAD;
++	val |= REF_SSP_EN;
+ 	writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
+ 
++	/* De-assert PHY, PCIe, POR and AXI resets */
+ 	ret = reset_control_deassert(res->phy_reset);
+ 	if (ret) {
+ 		dev_err(dev, "cannot deassert phy reset\n");
+@@ -327,12 +481,16 @@ static int qcom_pcie_init_v0(struct qcom
+ 	return 0;
+ 
+ err_deassert_ahb:
++	clk_disable_unprepare(res->ref_clk);
++err_clk_ref:
++	clk_disable_unprepare(res->aux_clk);
++err_clk_aux:
+ 	clk_disable_unprepare(res->core_clk);
+ err_clk_core:
+ 	clk_disable_unprepare(res->phy_clk);
+ err_clk_phy:
+ 	clk_disable_unprepare(res->iface_clk);
+-err_assert_ahb:
++err_assert_reset:
+ 	regulator_disable(res->vdda_phy);
+ err_vdda_phy:
+ 	regulator_disable(res->vdda_refclk);
+@@ -342,6 +500,12 @@ err_refclk:
+ 	return ret;
+ }
+ 
++static void qcom_pcie_configure_v0(struct qcom_pcie *pcie)
++{
++	qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
++	qcom_pcie_prog_viewport_mem2_outbound(pcie);
++}
++
+ static void qcom_pcie_deinit_v1(struct qcom_pcie *pcie)
+ {
+ 	struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
+@@ -455,6 +619,9 @@ static void qcom_pcie_host_init(struct p
+ 	if (ret)
+ 		goto err;
+ 
++	if (pcie->ops->init)
++		pcie->ops->init(pcie);
++
+ 	return;
+ err:
+ 	qcom_ep_reset_assert(pcie);
+@@ -486,6 +653,7 @@ static struct pcie_host_ops qcom_pcie_dw
+ static const struct qcom_pcie_ops ops_v0 = {
+ 	.get_resources = qcom_pcie_get_resources_v0,
+ 	.init = qcom_pcie_init_v0,
++	.configure = qcom_pcie_configure_v0,
+ 	.deinit = qcom_pcie_deinit_v0,
+ };
+