add patches to support the advanced power management on Kirkwood socs

SVN-Revision: 16250

2 files changed, 278 insertions, 0 deletions

diff --git a/target/linux/kirkwood/patches/003-gating.patch b/target/linux/kirkwood/patches/003-gating.patch
new file mode 100644
index 0000000..af8e911
--- /dev/null
+++ b/target/linux/kirkwood/patches/003-gating.patch
@@ -0,0 +1,132 @@
+From: Rabeeh Khoury <rabeeh@marvell.com>
+Date: Sun, 22 Mar 2009 15:30:32 +0000 (+0200)
+Subject: [ARM] Kirkwood: peripherals clock gating for power management
+X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=c0c3df02efed0e5dea9aa4d8313e06e1f68f2cb4;hp=039b97666e1335eac517c7d35a0fa1143af689f0
+
+[ARM] Kirkwood: peripherals clock gating for power management
+
+1. Enabling clock gating of unused peripherals
+2. PLL and PHY of the units are also disabled (when possible.
+
+Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com>
+
+[ This needs to be revisited to make power handling dynamic and per device.  -- Nico ]
+
+---
+
+--- a/arch/arm/mach-kirkwood/common.c
++++ b/arch/arm/mach-kirkwood/common.c
+@@ -788,6 +788,38 @@ static void __init kirkwood_l2_init(void
+ #endif
+ }
+ 
++void __init kirkwood_clock_gate(u32 reg)
++{
++	printk(KERN_INFO "Kirkwood: Gating clock using mask 0x%x\n", reg);
++	/* First make sure that the units are accessible */
++	writel(readl(CLOCK_GATING_CTRL) | reg, CLOCK_GATING_CTRL);
++	/* For SATA first shutdown the phy */
++	if (reg & CGC_SATA0) {
++		/* Disable PLL and IVREF */
++		writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
++		/* Disable PHY */
++		writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
++	}
++	if (reg & CGC_SATA1) {
++		/* Disable PLL and IVREF */
++		writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
++		/* Disable PHY */
++		writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
++	}
++	/* For PCI-E first shutdown the phy */
++	if (reg & CGC_PEX0) {
++		writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
++		while (1) {
++			if (readl(PCIE_STATUS) & 0x1)
++				break;
++		}
++		writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
++	}
++	/* Now gate clock the required units */
++	writel(readl(CLOCK_GATING_CTRL) & ~reg, CLOCK_GATING_CTRL);
++	return;
++}
++
+ void __init kirkwood_init(void)
+ {
+ 	printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
+--- a/arch/arm/mach-kirkwood/common.h
++++ b/arch/arm/mach-kirkwood/common.h
+@@ -22,6 +22,7 @@ struct mvsdio_platform_data;
+ void kirkwood_map_io(void);
+ void kirkwood_init(void);
+ void kirkwood_init_irq(void);
++void __init kirkwood_clock_gate(u32 reg);
+ 
+ extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
+ void kirkwood_setup_cpu_mbus(void);
+--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
++++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+@@ -39,4 +39,20 @@
+ #define L2_CONFIG_REG		(BRIDGE_VIRT_BASE | 0x0128)
+ #define L2_WRITETHROUGH		0x00000010
+ 
++#define CLOCK_GATING_CTRL	(BRIDGE_VIRT_BASE | 0x11c)
++#define CGC_GE0			0x1
++#define CGC_PEX0		0x4
++#define CGC_USB0		0x8
++#define CGC_SDIO		0x10
++#define CGC_TSU			0x20
++#define CGC_NAND_SPI		0x80
++#define CGC_XOR0		0x100
++#define CGC_AUDIO		0x200
++#define CGC_SATA0		0x4000
++#define CGC_SATA1		0x8000
++#define CGC_XOR1		0x10000
++#define CGC_CRYPTO		0x20000
++#define CGC_GE1			0x80000
++#define CGC_TDM			0x100000
++
+ #endif
+--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
++++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+@@ -64,6 +64,8 @@
+ #define BRIDGE_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x20000)
+ 
+ #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
++#define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
++#define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+ 
+ #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
+ 
+@@ -80,6 +82,11 @@
+ #define GE01_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x74000)
+ 
+ #define SATA_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x80000)
++#define SATA_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x80000)
++#define SATA0_IF_CTRL		(SATA_VIRT_BASE | 0x2050)
++#define SATA0_PHY_MODE_2	(SATA_VIRT_BASE | 0x2330)
++#define SATA1_IF_CTRL		(SATA_VIRT_BASE | 0x4050)
++#define SATA1_PHY_MODE_2	(SATA_VIRT_BASE | 0x4330)
+ 
+ #define SDIO_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x90000)
+ 
+--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
++++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
+@@ -19,6 +19,7 @@
+ #include <asm/mach-types.h>
+ #include <asm/mach/arch.h>
+ #include <mach/kirkwood.h>
++#include <mach/bridge-regs.h>
+ #include <plat/mvsdio.h>
+ #include <plat/orion_nand.h>
+ #include "common.h"
+@@ -122,6 +123,8 @@ static void __init sheevaplug_init(void)
+ 
+ 	platform_device_register(&sheevaplug_nand_flash);
+ 	platform_device_register(&sheevaplug_leds);
++	kirkwood_clock_gate(CGC_PEX0 | CGC_TSU | CGC_AUDIO | CGC_SATA0 |\
++				CGC_SATA1 | CGC_CRYPTO | CGC_GE1 | CGC_TDM);
+ }
+ 
+ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
diff --git a/target/linux/kirkwood/patches/004-cpuidle.patch b/target/linux/kirkwood/patches/004-cpuidle.patch
new file mode 100644
index 0000000..876fe89
--- /dev/null
+++ b/target/linux/kirkwood/patches/004-cpuidle.patch
@@ -0,0 +1,146 @@
+From: Rabeeh Khoury <rabeeh@marvell.com>
+Date: Tue, 24 Mar 2009 14:10:15 +0000 (+0200)
+Subject: [ARM] Kirkwood: CPU idle driver
+X-Git-Url: http://git.marvell.com/?p=orion.git;a=commitdiff_plain;h=039b97666e1335eac517c7d35a0fa1143af689f0;hp=56a50adda49b2020156616c4eb15353e0f9ad7de
+
+[ARM] Kirkwood: CPU idle driver
+
+The patch adds support for Kirkwood cpu idle.
+Two idle states are defined:
+1. Wait-for-interrupt (replacing default kirkwood wfi)
+2. Wait-for-interrupt and DDR self refresh
+
+Signed-off-by: Rabeeh Khoury <rabeeh@marvell.com>
+Signed-off-by: Nicolas Pitre <nico@marvell.com>
+---
+
+--- a/arch/arm/configs/kirkwood_defconfig
++++ b/arch/arm/configs/kirkwood_defconfig
+@@ -270,7 +270,9 @@ CONFIG_CMDLINE=""
+ #
+ # CPU Power Management
+ #
+-# CONFIG_CPU_IDLE is not set
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_CPU_IDLE_GOV_MENU=y
+ 
+ #
+ # Floating point emulation
+--- a/arch/arm/mach-kirkwood/Makefile
++++ b/arch/arm/mach-kirkwood/Makefile
+@@ -5,3 +5,5 @@ obj-$(CONFIG_MACH_RD88F6192_NAS)	+= rd88
+ obj-$(CONFIG_MACH_RD88F6281)		+= rd88f6281-setup.o
+ obj-$(CONFIG_MACH_SHEEVAPLUG)		+= sheevaplug-setup.o
+ obj-$(CONFIG_MACH_TS219)		+= ts219-setup.o
++
++obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
+--- /dev/null
++++ b/arch/arm/mach-kirkwood/cpuidle.c
+@@ -0,0 +1,96 @@
++/*
++ * arch/arm/mach-kirkwood/cpuidle.c
++ *
++ * CPU idle Marvell Kirkwood SoCs
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ *
++ * The cpu idle uses wait-for-interrupt and DDR self refresh in order
++ * to implement two idle states -
++ * #1 wait-for-interrupt
++ * #2 wait-for-interrupt and DDR self refresh
++ */
++
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
++#include <linux/cpuidle.h>
++#include <asm/io.h>
++#include <asm/proc-fns.h>
++#include <mach/kirkwood.h>
++
++#define KIRKWOOD_MAX_STATES	2
++
++static struct cpuidle_driver kirkwood_idle_driver = {
++	.name =         "kirkwood_idle",
++	.owner =        THIS_MODULE,
++};
++
++static DEFINE_PER_CPU(struct cpuidle_device, kirkwood_cpuidle_device);
++
++/* Actual code that puts the SoC in different idle states */
++static int kirkwood_enter_idle(struct cpuidle_device *dev,
++			       struct cpuidle_state *state)
++{
++	struct timeval before, after;
++	int idle_time;
++
++	local_irq_disable();
++	do_gettimeofday(&before);
++	if (state == &dev->states[0])
++		/* Wait for interrupt state */
++		cpu_do_idle();
++	else if (state == &dev->states[1]) {
++		/*
++		 * Following write will put DDR in self refresh.
++		 * Note that we have 256 cycles before DDR puts it
++		 * self in self-refresh, so the wait-for-interrupt
++		 * call afterwards won't get the DDR from self refresh
++		 * mode.
++		 */
++		writel(0x7, DDR_OPERATION_BASE);
++		cpu_do_idle();
++	}
++	do_gettimeofday(&after);
++	local_irq_enable();
++	idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
++			(after.tv_usec - before.tv_usec);
++	return idle_time;
++}
++
++/* Initialize CPU idle by registering the idle states */
++static int kirkwood_init_cpuidle(void)
++{
++	struct cpuidle_device *device;
++
++	cpuidle_register_driver(&kirkwood_idle_driver);
++
++	device = &per_cpu(kirkwood_cpuidle_device, smp_processor_id());
++	device->state_count = KIRKWOOD_MAX_STATES;
++
++	/* Wait for interrupt state */
++	device->states[0].enter = kirkwood_enter_idle;
++	device->states[0].exit_latency = 1;
++	device->states[0].target_residency = 10000;
++	device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
++	strcpy(device->states[0].name, "WFI");
++	strcpy(device->states[0].desc, "Wait for interrupt");
++
++	/* Wait for interrupt and DDR self refresh state */
++	device->states[1].enter = kirkwood_enter_idle;
++	device->states[1].exit_latency = 10;
++	device->states[1].target_residency = 10000;
++	device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
++	strcpy(device->states[1].name, "DDR SR");
++	strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
++
++	if (cpuidle_register_device(device)) {
++		printk(KERN_ERR "kirkwood_init_cpuidle: Failed registering\n");
++		return -EIO;
++	}
++	return 0;
++}
++
++device_initcall(kirkwood_init_cpuidle);
+--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
++++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+@@ -48,6 +48,7 @@
+  */
+ #define DDR_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x00000)
+ #define  DDR_WINDOW_CPU_BASE	(DDR_VIRT_BASE | 0x1500)
++#define DDR_OPERATION_BASE	(DDR_VIRT_BASE | 0x1418)
+ 
+ #define DEV_BUS_PHYS_BASE	(KIRKWOOD_REGS_PHYS_BASE | 0x10000)
+ #define DEV_BUS_VIRT_BASE	(KIRKWOOD_REGS_VIRT_BASE | 0x10000)