diff options
author | Thomas Nixon <tom@tomn.co.uk> | 2017-04-23 22:07:17 +0100 |
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committer | Mathias Kresin <dev@kresin.me> | 2017-07-07 07:13:24 +0200 |
commit | 50e3659703113df036e755e0d483172c3b809242 (patch) | |
tree | 195123601acacf16941fd02d3186980a54cec4c5 /target/linux/lantiq/dts/DM200.dts | |
parent | 08cd5b769deb4833b7a20208fa15674f52023fea (diff) | |
download | mtk-20170518-50e3659703113df036e755e0d483172c3b809242.zip mtk-20170518-50e3659703113df036e755e0d483172c3b809242.tar.gz mtk-20170518-50e3659703113df036e755e0d483172c3b809242.tar.bz2 |
lantiq: add Netgear DM200 support
Netgear DM200 is an inexpensive VDSL modem:
CPU: VRX220 MIPS 34Kc 5.6 @ 500Mhz
RAM: 64MiB
Flash: 8MiB
Ethernet: 1x100M
DSL: VDSL2+, ADSL2+
reset button, 3x bi-color LEDs
Serial port is 115200 baud, on the 4 pin header; pins from the bottom to
top are GND, RX, TX.
To upgrade from the vendor firmware, upload factory.img
The DM200 bootloader supports flashing over TFTP; hold the reset button
while powering on the device, and wait for the power light to start
flashing green before releasing. The device is now listening on
192.168.0.1/24, and can be sent a factory.img or a netgear image with a
TFTP put.
Once the image is loaded, it will be written to the flash, and the
device will reboot; this will take a few minutes.
Thanks to Edward O'Callaghan and Baptiste Jonglez, who implemented their
own ports for this device and provided valuable feedback.
Signed-off-by: Thomas Nixon <tom@tomn.co.uk>
Diffstat (limited to 'target/linux/lantiq/dts/DM200.dts')
-rw-r--r-- | target/linux/lantiq/dts/DM200.dts | 214 |
1 files changed, 214 insertions, 0 deletions
diff --git a/target/linux/lantiq/dts/DM200.dts b/target/linux/lantiq/dts/DM200.dts new file mode 100644 index 0000000..050d558 --- /dev/null +++ b/target/linux/lantiq/dts/DM200.dts @@ -0,0 +1,214 @@ +/dts-v1/; + +#include "vr9.dtsi" + +#include <dt-bindings/input/input.h> + +/ { + model = "DM200 - Netgear DM200"; + + chosen { + bootargs = "console=ttyLTQ0,115200"; + }; + + aliases { + led-boot = &power_green; + led-failsafe = &power_amber; + led-running = &power_green; + + led-dsl = &dsl_green; + }; + + memory@0 { + reg = <0x0 0x4000000>; + }; + + fpi@10000000 { + gpio: pinmux@E100B10 { + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux { + mdio { + lantiq,groups = "mdio"; + lantiq,function = "mdio"; + }; + }; + + pins_spi_default: pins_spi_default { + spi_in { + lantiq,groups = "spi_di"; + lantiq,function = "spi"; + }; + spi_out { + lantiq,groups = "spi_do", "spi_clk", "spi_cs4"; + lantiq,function = "spi"; + lantiq,output = <1>; + }; + }; + }; + + pcie@d900000 { + status = "disabled"; + }; + }; + + gphy-xrx200 { + compatible = "lantiq,phy-xrx200"; + firmware = "lantiq/vr9_phy22f_a2x.bin"; + phys = [ 01 ]; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <100>; + reset { + label = "reset"; + gpios = <&gpio 7 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; + + gpio_export { + compatible = "gpio-export"; + #size-cells = <0>; + + annexa { + gpio-export,name = "annexa"; + gpio-export,output = <0>; + gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; + }; + annexb { + gpio-export,name = "annexb"; + gpio-export,output = <0>; + gpios = <&gpio 15 GPIO_ACTIVE_HIGH>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + power_amber: power_amber { + label = "dm200:amber:power"; + gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + }; + power_green: power_green { + label = "dm200:green:power"; + gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; + + lan_amber { + label = "dm200:amber:lan"; + gpios = <&gpio 33 GPIO_ACTIVE_HIGH>; + }; + lan_green { + label = "dm200:green:lan"; + gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; + }; + + dsl_amber { + label = "dm200:amber:dsl"; + gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; + }; + dsl_green: dsl_green { + label = "dm200:green:dsl"; + gpios = <&gpio 36 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&spi { + pinctrl-names = "default"; + pinctrl-0 = <&pins_spi_default>; + + status = "ok"; + + m25p80@4 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + reg = <4 0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x0 0x20000>; + label = "uboot"; + read-only; + }; + + partition@20000 { + reg = <0x20000 0x10000>; + label = "gphyfirmware"; + read-only; + }; + + partition@30000 { + reg = <0x30000 0x7b0000>; + label = "firmware"; + }; + + partition@7e0000 { + reg = <0x7e0000 0x10000>; + label = "sysconfig"; + read-only; + }; + + partition@7f0000 { + reg = <0x7f0000 0x2000>; + label = "ubootconfig"; + read-only; + }; + + partition@7f2000 { + reg = <0x7f2000 0x1000>; + label = "ART"; + read-only; + }; + + partition@7f3000 { + reg = <0x7f3000 0x1000>; + label = "pot"; + read-only; + }; + + partition@7f4000 { + reg = <0x7f4000 0xc000>; + label = "ret"; + read-only; + }; + }; + }; +}; + +ð0 { + lan: interface@0 { + compatible = "lantiq,xrx200-pdi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + ethernet@4 { + compatible = "lantiq,xrx200-pdi-port"; + reg = <4>; + phy-mode = "mii"; + phy-handle = <&phy13>; + }; + }; + + mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "lantiq,xrx200-mdio"; + phy13: ethernet-phy@13 { + reg = <0x13>; + compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22"; + }; + }; +}; |