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author | John Crispin <john@openwrt.org> | 2013-04-25 19:03:13 +0000 |
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committer | John Crispin <john@openwrt.org> | 2013-04-25 19:03:13 +0000 |
commit | 46306c2e470063be7497c701511626791eccd6c0 (patch) | |
tree | 3b960af63722f03d519d042758fb1f2672cf5a0e /target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c | |
parent | fd79eb4e7c04b03d0301120c04311e54995e8d24 (diff) | |
download | mtk-20170518-46306c2e470063be7497c701511626791eccd6c0.zip mtk-20170518-46306c2e470063be7497c701511626791eccd6c0.tar.gz mtk-20170518-46306c2e470063be7497c701511626791eccd6c0.tar.bz2 |
lantiq: add lzma-loader source
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 36438
Diffstat (limited to 'target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c')
-rw-r--r-- | target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c b/target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c new file mode 100644 index 0000000..2f4dd6b --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/board-ar71xx.c @@ -0,0 +1,56 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + */ + +#include <stddef.h> +#include "config.h" +#include "ar71xx_regs.h" + +#define READREG(r) *(volatile unsigned int *)(r) +#define WRITEREG(r,v) *(volatile unsigned int *)(r) = v + +#define KSEG1ADDR(_x) (((_x) & 0x1fffffff) | 0xa0000000) + +#define UART_BASE 0xb8020000 + +#define UART_TX 0 +#define UART_LSR 5 + +#define UART_LSR_THRE 0x20 + +#define UART_READ(r) READREG(UART_BASE + 4 * (r)) +#define UART_WRITE(r,v) WRITEREG(UART_BASE + 4 * (r), (v)) + +void board_putc(int ch) +{ + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); + UART_WRITE(UART_TX, ch); + while (((UART_READ(UART_LSR)) & UART_LSR_THRE) == 0); +} + +#ifdef CONFIG_BOARD_TL_WR1043ND_V1 +static void tlwr1043nd_init(void) +{ + unsigned int reg = KSEG1ADDR(AR71XX_RESET_BASE); + unsigned int t; + + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); + t |= AR71XX_RESET_GE0_PHY; + WRITEREG(reg + AR913X_RESET_REG_RESET_MODULE, t); + /* flush write */ + t = READREG(reg + AR913X_RESET_REG_RESET_MODULE); +} +#else +static inline void tlwr1043nd_init(void) {} +#endif + +void board_init(void) +{ + tlwr1043nd_init(); +} |