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author | John Crispin <john@openwrt.org> | 2013-04-25 19:03:13 +0000 |
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committer | John Crispin <john@openwrt.org> | 2013-04-25 19:03:13 +0000 |
commit | 46306c2e470063be7497c701511626791eccd6c0 (patch) | |
tree | 3b960af63722f03d519d042758fb1f2672cf5a0e /target/linux/lantiq/image/lzma-loader/src/cache.c | |
parent | fd79eb4e7c04b03d0301120c04311e54995e8d24 (diff) | |
download | mtk-20170518-46306c2e470063be7497c701511626791eccd6c0.zip mtk-20170518-46306c2e470063be7497c701511626791eccd6c0.tar.gz mtk-20170518-46306c2e470063be7497c701511626791eccd6c0.tar.bz2 |
lantiq: add lzma-loader source
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 36438
Diffstat (limited to 'target/linux/lantiq/image/lzma-loader/src/cache.c')
-rw-r--r-- | target/linux/lantiq/image/lzma-loader/src/cache.c | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/target/linux/lantiq/image/lzma-loader/src/cache.c b/target/linux/lantiq/image/lzma-loader/src/cache.c new file mode 100644 index 0000000..28cc848 --- /dev/null +++ b/target/linux/lantiq/image/lzma-loader/src/cache.c @@ -0,0 +1,43 @@ +/* + * LZMA compressed kernel loader for Atheros AR7XXX/AR9XXX based boards + * + * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org> + * + * The cache manipulation routine has been taken from the U-Boot project. + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, <wd@denx.de> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + */ + +#include "cache.h" +#include "cacheops.h" +#include "config.h" + +#define cache_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips3\n\t \n" \ + " cache %0, %1 \n" \ + " .set pop \n" \ + : \ + : "i" (op), "R" (*(unsigned char *)(addr))) + +void flush_cache(unsigned long start_addr, unsigned long size) +{ + unsigned long lsize = CONFIG_CACHELINE_SIZE; + unsigned long addr = start_addr & ~(lsize - 1); + unsigned long aend = (start_addr + size - 1) & ~(lsize - 1); + + while (1) { + cache_op(Hit_Writeback_Inv_D, addr); + cache_op(Hit_Invalidate_I, addr); + if (addr == aend) + break; + addr += lsize; + } +} |