* update patches to 3.0

* add basic vr9 support
* backport 3.1 fixes
* backport 3.2 queue (falcon)

SVN-Revision: 28405

1 files changed, 0 insertions, 163 deletions

diff --git a/target/linux/lantiq/patches-3.0/180-falcon-linux3.0.patch b/target/linux/lantiq/patches-3.0/180-falcon-linux3.0.patch
deleted file mode 100644
index 3dd7964..0000000
--- a/target/linux/lantiq/patches-3.0/180-falcon-linux3.0.patch
+++ /dev/null
@@ -1,163 +0,0 @@
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -52,6 +52,7 @@
- #define ltq_eiu_w32(x, y)	ltq_w32((x), ltq_eiu_membase + (y))
- #define ltq_eiu_r32(x)		ltq_r32(ltq_eiu_membase + (x))
- 
-+#ifdef CONFIG_SOC_XWAY
- static unsigned short ltq_eiu_irq[MAX_EIU] = {
- 	LTQ_EIU_IR0,
- 	LTQ_EIU_IR1,
-@@ -60,6 +61,7 @@ static unsigned short ltq_eiu_irq[MAX_EI
- 	LTQ_EIU_IR4,
- 	LTQ_EIU_IR5,
- };
-+#endif
- 
- static struct resource ltq_icu_resource = {
- 	.name	= "icu",
-@@ -68,15 +70,19 @@ static struct resource ltq_icu_resource
- 	.flags	= IORESOURCE_MEM,
- };
- 
-+#ifdef CONFIG_SOC_XWAY
- static struct resource ltq_eiu_resource = {
- 	.name	= "eiu",
- 	.start	= LTQ_EIU_BASE_ADDR,
- 	.end	= LTQ_EIU_BASE_ADDR + LTQ_ICU_SIZE - 1,
- 	.flags	= IORESOURCE_MEM,
- };
-+#endif
- 
- static void __iomem *ltq_icu_membase;
-+#ifdef CONFIG_SOC_XWAY
- static void __iomem *ltq_eiu_membase;
-+#endif
- 
- void ltq_disable_irq(struct irq_data *d)
- {
-@@ -122,6 +128,7 @@ void ltq_enable_irq(struct irq_data *d)
- 	ltq_icu_w32(ltq_icu_r32(ier) | (1 << irq_nr), ier);
- }
- 
-+#ifdef CONFIG_SOC_XWAY
- static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
- {
- 	int i;
-@@ -161,6 +168,7 @@ static void ltq_shutdown_eiu_irq(struct
- 		}
- 	}
- }
-+#endif
- 
- static struct irq_chip ltq_irq_type = {
- 	"icu",
-@@ -172,6 +180,7 @@ static struct irq_chip ltq_irq_type = {
- 	.irq_mask_ack = ltq_mask_and_ack_irq,
- };
- 
-+#ifdef CONFIG_SOC_XWAY
- static struct irq_chip ltq_eiu_type = {
- 	"eiu",
- 	.irq_startup = ltq_startup_eiu_irq,
-@@ -183,6 +192,7 @@ static struct irq_chip ltq_eiu_type = {
- 	.irq_mask = ltq_disable_irq,
- 	.irq_mask_ack = ltq_mask_and_ack_irq,
- };
-+#endif
- 
- static void ltq_hw_irqdispatch(int module)
- {
-@@ -198,10 +208,12 @@ static void ltq_hw_irqdispatch(int modul
- 	irq = __fls(irq);
- 	do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
- 
-+#ifdef CONFIG_SOC_XWAY
- 	/* if this is a EBU irq, we need to ack it or get a deadlock */
- 	if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0))
- 		ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10,
- 			LTQ_EBU_PCC_ISTAT);
-+#endif
- }
- 
- #define DEFINE_HWx_IRQDISPATCH(x)					\
-@@ -264,6 +276,7 @@ void __init arch_init_irq(void)
- 	if (!ltq_icu_membase)
- 		panic("Failed to remap icu memory\n");
- 
-+#ifdef CONFIG_SOC_XWAY
- 	if (insert_resource(&iomem_resource, &ltq_eiu_resource) < 0)
- 		panic("Failed to insert eiu memory\n");
- 
-@@ -275,6 +288,7 @@ void __init arch_init_irq(void)
- 				resource_size(&ltq_eiu_resource));
- 	if (!ltq_eiu_membase)
- 		panic("Failed to remap eiu memory\n");
-+#endif
- 
- 	/* make sure all irqs are turned off by default */
- 	for (i = 0; i < 5; i++)
-@@ -300,6 +314,7 @@ void __init arch_init_irq(void)
- 
- 	for (i = INT_NUM_IRQ0;
- 		i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
-+#ifdef CONFIG_SOC_XWAY
- 		if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) ||
- 			(i == LTQ_EIU_IR2))
- 			irq_set_chip_and_handler(i, &ltq_eiu_type,
-@@ -310,6 +325,7 @@ void __init arch_init_irq(void)
- 			irq_set_chip_and_handler(i, &ltq_eiu_type,
- 				handle_level_irq);
- 		else
-+#endif
- 			irq_set_chip_and_handler(i, &ltq_irq_type,
- 				handle_level_irq);
- 
---- a/arch/mips/lantiq/clk.c
-+++ b/arch/mips/lantiq/clk.c
-@@ -46,6 +46,7 @@ static struct clk cpu_clk_generic[] = {
- 	},
- };
- 
-+#ifdef CONFIG_SOC_XWAY
- static struct resource ltq_cgu_resource = {
- 	.name	= "cgu",
- 	.start	= LTQ_CGU_BASE_ADDR,
-@@ -55,6 +56,7 @@ static struct resource ltq_cgu_resource
- 
- /* remapped clock register range */
- void __iomem *ltq_cgu_membase;
-+#endif
- 
- void clk_init(void)
- {
-@@ -131,6 +133,7 @@ void __init plat_time_init(void)
- {
- 	struct clk *clk;
- 
-+#ifdef CONFIG_SOC_XWAY
- 	if (insert_resource(&iomem_resource, &ltq_cgu_resource) < 0)
- 		panic("Failed to insert cgu memory\n");
- 
-@@ -144,6 +147,7 @@ void __init plat_time_init(void)
- 		pr_err("Failed to remap cgu memory\n");
- 		unreachable();
- 	}
-+#endif
- 	clk = clk_get(0, "cpu");
- 	mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution();
- 	write_c0_compare(read_c0_count());
---- a/arch/mips/lantiq/early_printk.c
-+++ b/arch/mips/lantiq/early_printk.c
-@@ -13,7 +13,11 @@
- #include <lantiq_soc.h>
- 
- /* no ioremap possible at this early stage, lets use KSEG1 instead  */
-+#ifdef CONFIG_SOC_FALCON
-+#define LTQ_ASC_BASE	KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
-+#else
- #define LTQ_ASC_BASE	KSEG1ADDR(LTQ_ASC1_BASE_ADDR)
-+#endif
- #define ASC_BUF		1024
- #define LTQ_ASC_FSTAT	((u32 *)(LTQ_ASC_BASE + 0x0048))
- #define LTQ_ASC_TBUF	((u32 *)(LTQ_ASC_BASE + 0x0020))