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authorJohn Crispin <john@openwrt.org>2015-03-16 07:39:52 +0000
committerJohn Crispin <john@openwrt.org>2015-03-16 07:39:52 +0000
commit257671615b5a915e7fe5767990487bbccaf2b4a1 (patch)
tree959a849b8ece8315d25df194fa68a7a79b0ff5f0 /target/linux/lantiq/patches-3.14/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch
parent7648d80c901faedb43f296411e9686d7e9eda592 (diff)
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lantiq: drop 3.14 support
Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 44812
Diffstat (limited to 'target/linux/lantiq/patches-3.14/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch')
-rw-r--r--target/linux/lantiq/patches-3.14/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch44
1 files changed, 0 insertions, 44 deletions
diff --git a/target/linux/lantiq/patches-3.14/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch b/target/linux/lantiq/patches-3.14/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch
deleted file mode 100644
index 6a7785b..0000000
--- a/target/linux/lantiq/patches-3.14/0014-MTD-lantiq-xway-the-latched-command-should-be-persis.patch
+++ /dev/null
@@ -1,44 +0,0 @@
-From b454cefd675fc1bd3d8c690c1bd1d8f4678e9922 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 28 Jul 2013 18:06:39 +0200
-Subject: [PATCH 14/36] MTD: lantiq: xway: the latched command should be
- persistent
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mtd/nand/xway_nand.c | 12 ++++++------
- 1 file changed, 6 insertions(+), 6 deletions(-)
-
---- a/drivers/mtd/nand/xway_nand.c
-+++ b/drivers/mtd/nand/xway_nand.c
-@@ -54,6 +54,8 @@
- #define NAND_CON_CSMUX (1 << 1)
- #define NAND_CON_NANDM 1
-
-+static u32 xway_latchcmd;
-+
- static void xway_reset_chip(struct nand_chip *chip)
- {
- unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
-@@ -94,17 +96,15 @@ static void xway_cmd_ctrl(struct mtd_inf
- unsigned long flags;
-
- if (ctrl & NAND_CTRL_CHANGE) {
-- nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
- if (ctrl & NAND_CLE)
-- nandaddr |= NAND_WRITE_CMD;
-- else
-- nandaddr |= NAND_WRITE_ADDR;
-- this->IO_ADDR_W = (void __iomem *) nandaddr;
-+ xway_latchcmd = NAND_WRITE_CMD;
-+ else if (ctrl & NAND_ALE)
-+ xway_latchcmd = NAND_WRITE_ADDR;
- }
-
- if (cmd != NAND_CMD_NONE) {
- spin_lock_irqsave(&ebu_lock, flags);
-- writeb(cmd, this->IO_ADDR_W);
-+ writeb(cmd, (void __iomem *) (nandaddr | xway_latchcmd));
- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
- ;
- spin_unlock_irqrestore(&ebu_lock, flags);