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author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
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committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch | |
parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
download | mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch')
-rw-r--r-- | target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch b/target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch new file mode 100644 index 0000000..7bcfd51 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/1086-mtd-spi-nor-wait-until-lock-unlock-operations-are-re.patch @@ -0,0 +1,66 @@ +From 3a06c61b48fbc23046928275e37a693e1055ae74 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Ezequiel=20Garc=C3=ADa?= <ezequiel@vanguardiasur.com.ar> +Date: Mon, 28 Dec 2015 17:54:51 -0300 +Subject: [PATCH 086/113] mtd: spi-nor: wait until lock/unlock operations are + ready + +On Micron and Numonyx devices, the status register write command +(WRSR), raises a work-in-progress bit (WIP) on the status register. +The datasheets for these devices specify that while the status +register write is in progress, the status register WIP bit can still +be read to check the end of the operation. + +This commit adds a wait_till_ready call on lock/unlock operations, +which is required for Micron and Numonyx but should be harmless for +others. This is needed to prevent applications from issuing erase or +program operations before the unlock operation is completed. + +Reported-by: Stas Sergeev <stsp@list.ru> +Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> +Signed-off-by: Brian Norris <computersforpeace@gmail.com> +--- + drivers/mtd/spi-nor/spi-nor.c | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -481,6 +481,7 @@ static int stm_lock(struct spi_nor *nor, + int status_old, status_new; + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + u8 shift = ffs(mask) - 1, pow, val; ++ int ret; + + status_old = read_sr(nor); + if (status_old < 0) +@@ -519,7 +520,10 @@ static int stm_lock(struct spi_nor *nor, + return -EINVAL; + + write_enable(nor); +- return write_sr(nor, status_new); ++ ret = write_sr(nor, status_new); ++ if (ret) ++ return ret; ++ return spi_nor_wait_till_ready(nor); + } + + /* +@@ -533,6 +537,7 @@ static int stm_unlock(struct spi_nor *no + int status_old, status_new; + u8 mask = SR_BP2 | SR_BP1 | SR_BP0; + u8 shift = ffs(mask) - 1, pow, val; ++ int ret; + + status_old = read_sr(nor); + if (status_old < 0) +@@ -569,7 +574,10 @@ static int stm_unlock(struct spi_nor *no + return -EINVAL; + + write_enable(nor); +- return write_sr(nor, status_new); ++ ret = write_sr(nor, status_new); ++ if (ret) ++ return ret; ++ return spi_nor_wait_till_ready(nor); + } + + /* |