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author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
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committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch | |
parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
download | mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch')
-rw-r--r-- | target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch | 82 |
1 files changed, 82 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch b/target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch new file mode 100644 index 0000000..faa806e --- /dev/null +++ b/target/linux/layerscape/patches-4.4/1091-mtd-spi-nor-change-return-value-of-read-write.patch @@ -0,0 +1,82 @@ +From 0a8079b232e9188ba267e37e20f192bed6c2b29b Mon Sep 17 00:00:00 2001 +From: Michal Suchanek <hramrach@gmail.com> +Date: Wed, 2 Dec 2015 10:38:19 +0000 +Subject: [PATCH 091/113] mtd: spi-nor: change return value of read/write + +Change the return value of spi-nor device read and write methods to +allow returning amount of data transferred and errors as +read(2)/write(2) does. + +Signed-off-by: Michal Suchanek <hramrach@gmail.com> +Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com> +--- + drivers/mtd/devices/m25p80.c | 5 +++-- + drivers/mtd/spi-nor/fsl-quadspi.c | 5 +++-- + include/linux/mtd/spi-nor.h | 4 ++-- + 3 files changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/mtd/devices/m25p80.c ++++ b/drivers/mtd/devices/m25p80.c +@@ -73,7 +73,7 @@ static int m25p80_write_reg(struct spi_n + return spi_write(spi, flash->command, len + 1); + } + +-static void m25p80_write(struct spi_nor *nor, loff_t to, size_t len, ++static ssize_t m25p80_write(struct spi_nor *nor, loff_t to, size_t len, + size_t *retlen, const u_char *buf) + { + struct m25p *flash = nor->priv; +@@ -101,6 +101,7 @@ static void m25p80_write(struct spi_nor + spi_sync(spi, &m); + + *retlen += m.actual_length - cmd_sz; ++ return 0; + } + + static inline unsigned int m25p80_rx_nbits(struct spi_nor *nor) +@@ -119,7 +120,7 @@ static inline unsigned int m25p80_rx_nbi + * Read an address range from the nor chip. The address range + * may be any size provided it is within the physical boundaries. + */ +-static int m25p80_read(struct spi_nor *nor, loff_t from, size_t len, ++static ssize_t m25p80_read(struct spi_nor *nor, loff_t from, size_t len, + size_t *retlen, u_char *buf) + { + struct m25p *flash = nor->priv; +--- a/drivers/mtd/spi-nor/fsl-quadspi.c ++++ b/drivers/mtd/spi-nor/fsl-quadspi.c +@@ -868,7 +868,7 @@ static int fsl_qspi_write_reg(struct spi + return ret; + } + +-static void fsl_qspi_write(struct spi_nor *nor, loff_t to, ++static ssize_t fsl_qspi_write(struct spi_nor *nor, loff_t to, + size_t len, size_t *retlen, const u_char *buf) + { + struct fsl_qspi *q = nor->priv; +@@ -878,9 +878,10 @@ static void fsl_qspi_write(struct spi_no + + /* invalid the data in the AHB buffer. */ + fsl_qspi_invalid(q); ++ return 0; + } + +-static int fsl_qspi_read(struct spi_nor *nor, loff_t from, ++static ssize_t fsl_qspi_read(struct spi_nor *nor, loff_t from, + size_t len, size_t *retlen, u_char *buf) + { + struct fsl_qspi *q = nor->priv; +--- a/include/linux/mtd/spi-nor.h ++++ b/include/linux/mtd/spi-nor.h +@@ -170,9 +170,9 @@ struct spi_nor { + int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); + int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); + +- int (*read)(struct spi_nor *nor, loff_t from, ++ ssize_t (*read)(struct spi_nor *nor, loff_t from, + size_t len, size_t *retlen, u_char *read_buf); +- void (*write)(struct spi_nor *nor, loff_t to, ++ ssize_t (*write)(struct spi_nor *nor, loff_t to, + size_t len, size_t *retlen, const u_char *write_buf); + int (*erase)(struct spi_nor *nor, loff_t offs); + |