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author | Yutang Jiang <yutang.jiang@nxp.com> | 2016-10-29 00:18:23 +0800 |
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committer | John Crispin <john@phrozen.org> | 2016-10-31 17:00:10 +0100 |
commit | 15a14cf1665ef3d8b5c77cce69b52d131340e3b3 (patch) | |
tree | bd544b24bd3e7fc7efc61f80e1755274971c5582 /target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch | |
parent | c6c731fe311f7da42777ffd31804a4f6aa3f8e19 (diff) | |
download | mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.zip mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.gz mtk-20170518-15a14cf1665ef3d8b5c77cce69b52d131340e3b3.tar.bz2 |
layerscape: add 64b/32b target for ls1012ardb device
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
development platform, with a complete debugging environment.
The LS1012ARDB board supports the QorIQ LS1012A processor and is
optimized to support the high-bandwidth DDR3L memory and
a full complement of high-speed SerDes ports.
LEDE/OPENWRT will auto strip executable program file while make. So we
need select CONFIG_NO_STRIP=y while make menuconfig to avoid the ppfe network
fiemware be destroyed, then run make to build ls1012ardb firmware.
The fsl-quadspi flash with jffs2 fs is unstable and arise some failed message.
This issue have noticed the IP owner for investigate, hope he can solve it
earlier. So the ls1012ardb now also provide a xx-firmware.ext4.bin as default
firmware, and the uboot bootcmd will run wrtboot_ext4rfs for "rootfstype=ext4"
bootargs.
Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>
Diffstat (limited to 'target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch')
-rw-r--r-- | target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch b/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch new file mode 100644 index 0000000..733b62c --- /dev/null +++ b/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch @@ -0,0 +1,41 @@ +From e892dea7229d56b75c46a76b9039f9e179584a91 Mon Sep 17 00:00:00 2001 +From: Yunhui Cui <B56489@freescale.com> +Date: Mon, 1 Feb 2016 18:48:49 +0800 +Subject: [PATCH 100/113] mtd:spi_nor: Disable Micron flash HW protection + +For Micron family ,The status register write enable/disable bit, +provides hardware data protection for the device. +When the enable/disable bit is set to 1, the status register +nonvolatile bits become read-only and the WRITE STATUS REGISTER +operation will not execute. + +Signed-off-by: Yunhui Cui <B56489@freescale.com> +--- + drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -39,6 +39,7 @@ + + #define SPI_NOR_MAX_ID_LEN 6 + #define SPI_NOR_MAX_ADDR_WIDTH 4 ++#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f + + struct flash_info { + char *name; +@@ -1237,6 +1238,14 @@ int spi_nor_scan(struct spi_nor *nor, co + if (ret) + return ret; + ++ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) { ++ ret = read_sr(nor); ++ ret &= SPI_NOR_MICRON_WRITE_ENABLE; ++ ++ write_enable(nor); ++ write_sr(nor, ret); ++ } ++ + if (!mtd->name) + mtd->name = dev_name(dev); + mtd->priv = nor; |