layerscape: add 64b/32b target for ls1043ardb device

Add support for NXP layerscape ls1043ardb 64b/32b Dev board.

LS1043a is an SoC with 4x64-bit up to 1.6 GHz ARMv8 A53 cores.
ls1043ardb support features as: 2GB DDR4, 128MB NOR/512MB NAND, USB3.0, eSDHC,
I2C, GPIO, PCIe/Mini-PCIe, 6x1G/1x10G network port, etc.

64b/32b ls1043ardb target is using 4.4 kernel, and rcw/u-boot/fman images from
NXP QorIQ SDK release.

All of 4.4 kernel patches porting from SDK release or upstream.

QorIQ SDK ISOs can be downloaded from this location:
http://www.nxp.com/products/software-and-tools/run-time-software/linux-sdk/linux-sdk-for-qoriq-processors:SDKLINUX

Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com>

1 files changed, 56 insertions, 0 deletions

diff --git a/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch b/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch
new file mode 100644
index 0000000..bd2d90e
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/8037-ls1043a-Add-support-for-reset.patch
@@ -0,0 +1,56 @@
+From 5d7f8473e3472c16703bf5692d0b13f47d08c70a Mon Sep 17 00:00:00 2001
+From: Shaohui Xie <Shaohui.Xie@freescale.com>
+Date: Fri, 22 Jan 2016 12:01:28 +0800
+Subject: [PATCH 37/70] ls1043a: Add support for reset
+
+The reset in ls1043a is similar to ls2085a, but accessed in big endian,
+so we modify the existing driver to handle endianness, if driver probes
+property 'big-endian' in DTS, driver works in big endian mode,
+otherwise, driver works in little endian by default.
+
+Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
+---
+ drivers/power/reset/ls-reboot.c |   18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+--- a/drivers/power/reset/ls-reboot.c
++++ b/drivers/power/reset/ls-reboot.c
+@@ -28,6 +28,7 @@
+ struct	ls_reboot_priv {
+ 	struct device *dev;
+ 	u32 *rstcr;
++	bool is_big_endian;
+ };
+ 
+ static struct ls_reboot_priv	*ls_reboot_priv;
+@@ -39,9 +40,15 @@ static void ls_reboot(enum reboot_mode r
+ 	unsigned long timeout;
+ 
+ 	if (ls_reboot_priv) {
+-		val = readl(priv->rstcr);
+-		val |= 0x02;
+-		writel(val, priv->rstcr);
++		if (priv->is_big_endian) {
++			val = ioread32be(priv->rstcr);
++			val |= 0x02;
++			iowrite32be(val, priv->rstcr);
++		} else {
++			val = readl(priv->rstcr);
++			val |= 0x02;
++			writel(val, priv->rstcr);
++		}
+ 	}
+ 
+ 	timeout = jiffies + HZ;
+@@ -66,6 +73,11 @@ static int ls_reboot_probe(struct platfo
+ 		return -ENODEV;
+ 	}
+ 
++	if (of_get_property(pdev->dev.of_node, "big-endian", NULL))
++		ls_reboot_priv->is_big_endian = true;
++	else
++		ls_reboot_priv->is_big_endian = false;
++
+ 	ls_reboot_priv->dev = &pdev->dev;
+ 
+ 	arm_pm_restart = ls_reboot;