diff options
| author | Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk> | 2018-04-24 12:19:43 +0000 |
|---|---|---|
| committer | Mathias Kresin <dev@kresin.me> | 2018-04-26 08:53:54 +0200 |
| commit | 9aa196e0f260986991dc8ea65a219f81aed0197e (patch) | |
| tree | 99abd0b8596eb91fb0837c0e49772fc202429cad /target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch | |
| parent | bdb0de1bbce235244bcd0503c71886409379f4fc (diff) | |
| download | mtk-20170518-9aa196e0f260986991dc8ea65a219f81aed0197e.zip mtk-20170518-9aa196e0f260986991dc8ea65a219f81aed0197e.tar.gz mtk-20170518-9aa196e0f260986991dc8ea65a219f81aed0197e.tar.bz2 | |
kernel: bump 4.9 to 4.9.96
Refresh patches, following required reworking:
ar71xx/patches-4.9/930-chipidea-pullup.patch
layerscape/patches-4.9/302-dts-support-layercape.patch
sunxi/patches-4.9/0052-stmmac-form-4-12.patch
Fixes for CVEs:
CVE-2018-1108
CVE-2018-1092
Tested on: ar71xx Archer C7 v2
Signed-off-by: Kevin Darbyshire-Bryant <ldir@darbyshire-bryant.me.uk>
Tested-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
Tested-by: Arjen de Korte <build+openwrt@de-korte.org>
Diffstat (limited to 'target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch | 8 |
1 files changed, 1 insertions, 7 deletions
diff --git a/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch b/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch index 361f43c..37dc5ee 100644 --- a/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch +++ b/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch @@ -340,7 +340,7 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> reg = <0x0 0x1570e08 0x0 0x8>; msi-controller; interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; -@@ -137,16 +144,17 @@ +@@ -137,11 +144,12 @@ compatible = "fsl,ifc", "simple-bus"; reg = <0x0 0x1530000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; @@ -354,12 +354,6 @@ Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> big-endian; }; - esdhc: esdhc@1560000 { -- compatible = "fsl,esdhc"; -+ compatible = "fsl,ls1021a-esdhc","fsl,esdhc"; - reg = <0x0 0x1560000 0x0 0x10000>; - interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <0>; @@ -163,7 +171,7 @@ <0x0 0x20220520 0x0 0x4>; reg-names = "ahci", "sata-ecc"; |