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| author | John Crispin <john@openwrt.org> | 2015-11-02 10:18:50 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2015-11-02 10:18:50 +0000 |
| commit | 25afe99b31f4ef3d835f96545e370770c230ac44 (patch) | |
| tree | 5dbe83834a0a67121c557b7549a13221317f07eb /target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch | |
| parent | 12e0d2737f558e886cf698e939f1758ab6a64947 (diff) | |
| download | mtk-20170518-25afe99b31f4ef3d835f96545e370770c230ac44.zip mtk-20170518-25afe99b31f4ef3d835f96545e370770c230ac44.tar.gz mtk-20170518-25afe99b31f4ef3d835f96545e370770c230ac44.tar.bz2 | |
mediatek: add support for the new MT7623 Arm SoC
the support is still WIP. next steps are to make the pmic and ethernet work.
this is the first commit to make sure nothing gets lost.
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 47354
Diffstat (limited to 'target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch')
| -rw-r--r-- | target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch b/target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch new file mode 100644 index 0000000..1236a96 --- /dev/null +++ b/target/linux/mediatek/patches/0027-dt-bindings-pwm-add-Mediatek-display-PWM-bindings.patch @@ -0,0 +1,47 @@ +From 908a87b47af8303c9aa8fb6aa183ca9f8b544d78 Mon Sep 17 00:00:00 2001 +From: YH Huang <yh.huang@mediatek.com> +Date: Mon, 11 May 2015 17:26:21 +0800 +Subject: [PATCH 27/76] dt-bindings: pwm: add Mediatek display PWM bindings + +Document the device-tree binding of Mediatek display PWM. + +Signed-off-by: YH Huang <yh.huang@mediatek.com> +--- + .../devicetree/bindings/pwm/pwm-disp-mediatek.txt | 25 ++++++++++++++++++++ + 1 file changed, 25 insertions(+) + create mode 100644 Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt + +diff --git a/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt +new file mode 100644 +index 0000000..ef54e9d +--- /dev/null ++++ b/Documentation/devicetree/bindings/pwm/pwm-disp-mediatek.txt +@@ -0,0 +1,25 @@ ++Mediatek display PWM controller ++ ++Required properties: ++ - compatible: should be "mediatek,<name>-disp-pwm" ++ - "mediatek,mt8173-disp-pwm": found on mt8173 SoC ++ - "mediatek,mt6595-disp-pwm": found on mt6595 SoC ++ - reg: physical base address and length of the controller's registers ++ - #pwm-cells: must be 2. See pwm.txt in this directory ++ for a description of the cell format ++ - clocks: phandle and clock specifier of the PWM reference clock ++ - clock-names: must contain the following ++ - "main": clock used to generate PWM signals ++ - "mm": sync signals from the modules of mmsys ++ ++Example: ++ pwm0: pwm@1401e000 { ++ compatible = "mediatek,mt8173-disp-pwm", ++ "mediatek,mt6595-disp-pwm"; ++ reg = <0 0x1401e000 0 0x1000>; ++ #pwm-cells = <2>; ++ clocks = <&mmsys MM_DISP_PWM026M>, ++ <&mmsys MM_DISP_PWM0MM>; ++ clock-names = "main", ++ "mm"; ++ }; +-- +1.7.10.4 + |