mediatek: bump to v4.4

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 49064

1 files changed, 0 insertions, 144 deletions

diff --git a/target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch b/target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch
deleted file mode 100644
index 54ae45b..0000000
--- a/target/linux/mediatek/patches/0032-dt-bindings-mediatek-Add-MT8173-cpufreq-driver-bindi.patch
+++ /dev/null
@@ -1,144 +0,0 @@
-From d83532fe7eb9cc7b8cc39dd9f2bbd9873d4e390b Mon Sep 17 00:00:00 2001
-From: "pi-cheng.chen" <pi-cheng.chen@linaro.org>
-Date: Mon, 8 Jun 2015 20:29:20 +0800
-Subject: [PATCH 32/76] dt-bindings: mediatek: Add MT8173 cpufreq driver
- binding
-
-This patch adds device tree binding document for MT8173 cpufreq driver.
-
-Signed-off-by: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
----
- .../devicetree/bindings/cpufreq/cpufreq-mt8173.txt |  127 ++++++++++++++++++++
- 1 file changed, 127 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
-
---- /dev/null
-+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mt8173.txt
-@@ -0,0 +1,127 @@
-+
-+Mediatek MT8173 cpufreq driver
-+-------------------
-+
-+Mediatek MT8173 cpufreq driver for CPU frequency scaling.
-+
-+Required properties:
-+- clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
-+- clock-names: Should contain the following:
-+	"cpu"		- The multiplexer for clock input of CPU cluster.
-+	"intermediate"	- A parent of "cpu" clock which is used as "intermediate" clock
-+			  source (usually MAINPLL) when the original CPU PLL is under
-+			  transition and not stable yet.
-+- operating-points: Table of frequencies and voltage CPU could be transitioned into,
-+		    Frequency should be in KHz units and voltage should be in microvolts.
-+- proc-supply: Regulator for Vproc of CPU cluster.
-+
-+Optional properties:
-+- sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
-+	       needs to do "voltage trace" to step by step scale up/down Vproc and
-+	       Vsram to fit SoC specific needs. When absent, the voltage scaling
-+	       flow is handled by hardware, hence no software "voltage trace" is
-+	       needed.
-+
-+Example:
-+--------
-+	cpu0: cpu@0 {
-+		device_type = "cpu";
-+		compatible = "arm,cortex-a53";
-+		reg = <0x000>;
-+		enable-method = "psci";
-+		cpu-idle-states = <&CPU_SLEEP_0>;
-+		clocks = <&infracfg CLK_INFRA_CA53SEL>,
-+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-+		clock-names = "cpu", "intermediate";
-+		operating-points = <
-+			507000	859000
-+			702000	908000
-+			1001000	983000
-+			1105000	1009000
-+			1183000	1028000
-+			1404000	1083000
-+			1508000	1109000
-+			1573000	1125000
-+		>;
-+	};
-+
-+	cpu1: cpu@1 {
-+		device_type = "cpu";
-+		compatible = "arm,cortex-a53";
-+		reg = <0x001>;
-+		enable-method = "psci";
-+		cpu-idle-states = <&CPU_SLEEP_0>;
-+		clocks = <&infracfg CLK_INFRA_CA53SEL>,
-+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-+		clock-names = "cpu", "intermediate";
-+		operating-points = <
-+			507000	859000
-+			702000	908000
-+			1001000	983000
-+			1105000	1009000
-+			1183000	1028000
-+			1404000	1083000
-+			1508000	1109000
-+			1573000	1125000
-+		>;
-+	};
-+
-+	cpu2: cpu@100 {
-+		device_type = "cpu";
-+		compatible = "arm,cortex-a57";
-+		reg = <0x100>;
-+		enable-method = "psci";
-+		cpu-idle-states = <&CPU_SLEEP_0>;
-+		clocks = <&infracfg CLK_INFRA_CA57SEL>,
-+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-+		clock-names = "cpu", "intermediate";
-+		operating-points = <
-+			507000	828000
-+			702000	867000
-+			1001000	927000
-+			1209000	968000
-+			1404000	1007000
-+			1612000	1049000
-+			1807000	1089000
-+			1989000	1125000
-+		>;
-+	};
-+
-+	cpu3: cpu@101 {
-+		device_type = "cpu";
-+		compatible = "arm,cortex-a57";
-+		reg = <0x101>;
-+		enable-method = "psci";
-+		cpu-idle-states = <&CPU_SLEEP_0>;
-+		clocks = <&infracfg CLK_INFRA_CA57SEL>,
-+			 <&apmixedsys CLK_APMIXED_MAINPLL>;
-+		clock-names = "cpu", "intermediate";
-+		operating-points = <
-+			507000	828000
-+			702000	867000
-+			1001000	927000
-+			1209000	968000
-+			1404000	1007000
-+			1612000	1049000
-+			1807000	1089000
-+			1989000	1125000
-+		>;
-+	};
-+
-+	&cpu0 {
-+		proc-supply = <&mt6397_vpca15_reg>;
-+	};
-+
-+	&cpu1 {
-+		proc-supply = <&mt6397_vpca15_reg>;
-+	};
-+
-+	&cpu2 {
-+		proc-supply = <&da9211_vcpu_reg>;
-+		sram-supply = <&mt6397_vsramca7_reg>;
-+	};
-+
-+	&cpu3 {
-+		proc-supply = <&da9211_vcpu_reg>;
-+		sram-supply = <&mt6397_vsramca7_reg>;
-+	};