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authorFelix Fietkau <nbd@openwrt.org>2015-05-25 21:15:37 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-05-25 21:15:37 +0000
commit7b85e8e316e9338a29ea5398c35961fc40ef354a (patch)
tree4bb1258c11c5303e51e9b7b7d6660ad64dee382d /target/linux/mpc85xx/files/arch/powerpc
parent4eeeb916613273d8cf0c97c1ba44fd2366ea8d9a (diff)
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mpc85xx: TL-WDR4900: Fix port 6 being shown as up (10MBit/half) in LUCI/swconfig
Currently port 6 is shown as up 10MBit/half in LUCI and swconfig. Reason is that all bits in the port 6 config are zero. This means that also the aneg flag is not set and in this case ar8216_read_port_link hardcodes the link to be up. This is no real problem but a little annoying. To fix this initialize port 6 with the aneg bit enabled. This causes ar8216_read_port_link to evaluate the link status bit which is always zero for port 6 as no PHY is connected to this port. And it doesn't hurt as port 6 isn't connected to anything on TL-WDR4900. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> SVN-Revision: 45749
Diffstat (limited to 'target/linux/mpc85xx/files/arch/powerpc')
-rw-r--r--target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts1
1 files changed, 1 insertions, 0 deletions
diff --git a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
index 7e48e23..2beb39c 100644
--- a/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
+++ b/target/linux/mpc85xx/files/arch/powerpc/boot/dts/tl-wdr4900-v1.dts
@@ -103,6 +103,7 @@
0x00058 0xcf35cf35 /* LED_CTRL2 */
0x0005c 0x03ffff00 /* LED_CTRL3 */
0x0007c 0x0000007e /* PORT0_STATUS */
+ 0x00094 0x00000200 /* PORT6_STATUS */
>;
};
};