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authorLuka Perkov <luka@openwrt.org>2014-02-11 02:07:38 +0000
committerLuka Perkov <luka@openwrt.org>2014-02-11 02:07:38 +0000
commit69d323f23119ce6986c2803f34d95869144a00e6 (patch)
tree15747b34c6f9a8dfb622f3d61cbffe043f67e573 /target/linux/mvebu/patches-3.10/0046-bus-mvebu-mbus-Add-new-API-for-the-PCIe-memory-and-I.patch
parent31fb795fd01ac711ff6ca881271fdd4268e34570 (diff)
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mvebu: backport mainline patches from kernel 3.11
This is a backport of the patches accepted to the Linux mainline related to mvebu SoC (Armada XP and Armada 370) between Linux v3.10, and Linux v3.11. This work mainly covers: * Enabling USB storage, and PCI to mvebu_defconfig. * Add support for NOR flash. * Some PCI device tree related updates, and bus parsing. * Adding Armada XP & 370 PCI driver, and update some clock gating specifics. * Introduce Marvell EBU Device Bus driver. * Enaling USB in the armada*.dts. * Enabling, and updating the mvebu-mbus. * Some SATA and Ethernet related fixes. Signed-off-by: Seif Mazareeb <seif.mazareeb@gmail.com> CC: Luka Perkov <luka@openwrt.org> SVN-Revision: 39564
Diffstat (limited to 'target/linux/mvebu/patches-3.10/0046-bus-mvebu-mbus-Add-new-API-for-the-PCIe-memory-and-I.patch')
-rw-r--r--target/linux/mvebu/patches-3.10/0046-bus-mvebu-mbus-Add-new-API-for-the-PCIe-memory-and-I.patch121
1 files changed, 121 insertions, 0 deletions
diff --git a/target/linux/mvebu/patches-3.10/0046-bus-mvebu-mbus-Add-new-API-for-the-PCIe-memory-and-I.patch b/target/linux/mvebu/patches-3.10/0046-bus-mvebu-mbus-Add-new-API-for-the-PCIe-memory-and-I.patch
new file mode 100644
index 0000000..973ffde
--- /dev/null
+++ b/target/linux/mvebu/patches-3.10/0046-bus-mvebu-mbus-Add-new-API-for-the-PCIe-memory-and-I.patch
@@ -0,0 +1,121 @@
+From c9646c891dbd07061a9ff5e061f9f9e54c571349 Mon Sep 17 00:00:00 2001
+From: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Date: Tue, 9 Jul 2013 10:41:53 -0300
+Subject: [PATCH 046/203] bus: mvebu-mbus: Add new API for the PCIe memory and
+ IO aperture
+
+We add two optional properties to the MBus DT binding, to encode
+the PCIe memory and IO aperture. This allows such information to
+be retrieved by -for instance- the pci driver to allocate the
+MBus decoding windows.
+
+Correspondingly, and in order to retrieve this information,
+we add two new APIs.
+
+Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
+Tested-by: Andrew Lunn <andrew@lunn.ch>
+Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+---
+ drivers/bus/mvebu-mbus.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++++
+ include/linux/mbus.h | 4 ++++
+ 2 files changed, 53 insertions(+)
+
+--- a/drivers/bus/mvebu-mbus.c
++++ b/drivers/bus/mvebu-mbus.c
+@@ -142,6 +142,8 @@ struct mvebu_mbus_state {
+ struct dentry *debugfs_root;
+ struct dentry *debugfs_sdram;
+ struct dentry *debugfs_devs;
++ struct resource pcie_mem_aperture;
++ struct resource pcie_io_aperture;
+ const struct mvebu_mbus_soc_data *soc;
+ int hw_io_coherency;
+ };
+@@ -821,6 +823,20 @@ int mvebu_mbus_del_window(phys_addr_t ba
+ return 0;
+ }
+
++void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
++{
++ if (!res)
++ return;
++ *res = mbus_state.pcie_mem_aperture;
++}
++
++void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
++{
++ if (!res)
++ return;
++ *res = mbus_state.pcie_io_aperture;
++}
++
+ static __init int mvebu_mbus_debugfs_init(void)
+ {
+ struct mvebu_mbus_state *s = &mbus_state;
+@@ -1023,6 +1039,35 @@ static int __init mbus_dt_setup(struct m
+ return 0;
+ }
+
++static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
++ struct resource *mem,
++ struct resource *io)
++{
++ u32 reg[2];
++ int ret;
++
++ /*
++ * These are optional, so we clear them and they'll
++ * be zero if they are missing from the DT.
++ */
++ memset(mem, 0, sizeof(struct resource));
++ memset(io, 0, sizeof(struct resource));
++
++ ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
++ if (!ret) {
++ mem->start = reg[0];
++ mem->end = mem->start + reg[1];
++ mem->flags = IORESOURCE_MEM;
++ }
++
++ ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
++ if (!ret) {
++ io->start = reg[0];
++ io->end = io->start + reg[1];
++ io->flags = IORESOURCE_IO;
++ }
++}
++
+ int __init mvebu_mbus_dt_init(void)
+ {
+ struct resource mbuswins_res, sdramwins_res;
+@@ -1062,6 +1107,10 @@ int __init mvebu_mbus_dt_init(void)
+ return -EINVAL;
+ }
+
++ /* Get optional pcie-{mem,io}-aperture properties */
++ mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
++ &mbus_state.pcie_io_aperture);
++
+ ret = mvebu_mbus_common_init(&mbus_state,
+ mbuswins_res.start,
+ resource_size(&mbuswins_res),
+--- a/include/linux/mbus.h
++++ b/include/linux/mbus.h
+@@ -11,6 +11,8 @@
+ #ifndef __LINUX_MBUS_H
+ #define __LINUX_MBUS_H
+
++struct resource;
++
+ struct mbus_dram_target_info
+ {
+ /*
+@@ -59,6 +61,8 @@ static inline const struct mbus_dram_tar
+ }
+ #endif
+
++void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
++void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
+ int mvebu_mbus_add_window_remap_flags(const char *devname, phys_addr_t base,
+ size_t size, phys_addr_t remap,
+ unsigned int flags);