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authorStijn Tintel <stijn@linux-ipv6.be>2016-08-22 19:05:45 +0200
committerStijn Tintel <stijn@linux-ipv6.be>2016-08-23 10:51:17 +0300
commit8072264b96785184b76aa46bcd08b4f9cdfada42 (patch)
tree3a50dec26a5eb09091897a3ab98a4cfc1de170f4 /target/linux/mvebu
parent861f566e340dcf5fedd52c0ff3b31501fd3b3f1b (diff)
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kernel: update kernel 4.4 to version 4.4.19
Refresh patches for all targets that support kernel 4.4. Compile-tested on all targets that use kernel 4.4 and aren't marked broken. Runtime-tested on ar71xx, octeon and x86/64. Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Diffstat (limited to 'target/linux/mvebu')
-rw-r--r--target/linux/mvebu/patches-4.4/024-mvebu-make-device-IO-strongly-ordered.patch47
-rw-r--r--target/linux/mvebu/patches-4.4/105-linksys_armada_385_fix_crypto_sram.patch13
2 files changed, 0 insertions, 60 deletions
diff --git a/target/linux/mvebu/patches-4.4/024-mvebu-make-device-IO-strongly-ordered.patch b/target/linux/mvebu/patches-4.4/024-mvebu-make-device-IO-strongly-ordered.patch
deleted file mode 100644
index dc66997..0000000
--- a/target/linux/mvebu/patches-4.4/024-mvebu-make-device-IO-strongly-ordered.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-On Cortex-A9 based Marvell SoCs, when HW I/O coherency is enabled, all
-non-RAM space needs to be mapped strongly ordered.
-In upstream this was added for PCIe I/O only, this change expands it
-to cover all device memory. Fixes issues with CESA.
-Based on patch from Thomas Petazzoni.
-
-Signed-off-by: Felix Fietkau <nbd@nbd.name>
-
---- a/arch/arm/mach-mvebu/coherency.c
-+++ b/arch/arm/mach-mvebu/coherency.c
-@@ -162,22 +162,16 @@ exit:
- }
-
- /*
-- * This ioremap hook is used on Armada 375/38x to ensure that PCIe
-+ * This ioremap hook is used on Armada 375/38x to ensure that all non-RAM
- * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
-- * is needed as a workaround for a deadlock issue between the PCIe
-+ * is needed as a workaround for a deadlock issue between the bus
- * interface and the cache controller.
- */
- static void __iomem *
--armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
-- unsigned int mtype, void *caller)
-+armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
-+ unsigned int mtype, void *caller)
- {
-- struct resource pcie_mem;
--
-- mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
--
-- if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
-- mtype = MT_UNCACHED;
--
-+ mtype = MT_UNCACHED;
- return __arm_ioremap_caller(phys_addr, size, mtype, caller);
- }
-
-@@ -186,7 +180,7 @@ static void __init armada_375_380_cohere
- struct device_node *cache_dn;
-
- coherency_cpu_base = of_iomap(np, 0);
-- arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
-+ arch_ioremap_caller = armada_wa_ioremap_caller;
-
- /*
- * We should switch the PL310 to I/O coherency mode only if
diff --git a/target/linux/mvebu/patches-4.4/105-linksys_armada_385_fix_crypto_sram.patch b/target/linux/mvebu/patches-4.4/105-linksys_armada_385_fix_crypto_sram.patch
deleted file mode 100644
index 3963c35..0000000
--- a/target/linux/mvebu/patches-4.4/105-linksys_armada_385_fix_crypto_sram.patch
+++ /dev/null
@@ -1,13 +0,0 @@
---- a/arch/arm/boot/dts/armada-385-linksys.dtsi
-+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
-@@ -58,8 +58,8 @@
- soc {
- ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
- MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
-- MBUS_ID(0x09, 0x09) 0 0xf1100000 0x10000
-- MBUS_ID(0x09, 0x05) 0 0xf1110000 0x10000>;
-+ MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
-+ MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
-
- internal-regs {
-