ramips: add preliminary Archer C20i support

Signed-off-by: Felix Fietkau <nbd@openwrt.org>

SVN-Revision: 43898

1 files changed, 111 insertions, 0 deletions

diff --git a/target/linux/ramips/dts/ArcherC20i.dts b/target/linux/ramips/dts/ArcherC20i.dts
new file mode 100644
index 0000000..a5037c9
--- /dev/null
+++ b/target/linux/ramips/dts/ArcherC20i.dts
@@ -0,0 +1,111 @@
+/dts-v1/;
+
+/include/ "mt7620a.dtsi"
+
+/ {
+	compatible = "ralink,mt7620a-soc";
+	model = "TP-Link Archer C20i";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	palmbus@10000000 {
+		gpio2: gpio@660 {
+			status = "okay";
+		};
+
+		spi@b00 {
+			status = "okay";
+
+			m25p80@0 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				compatible = "en25q64";
+				reg = <0 0>;
+				linux,modalias = "m25p80", "mx25l6405d";
+				spi-max-frequency = <10000000>;
+
+				partition@0 {
+					label = "u-boot";
+					reg = <0x0 0x20000>;
+					read-only;
+				};
+
+				partition@20000 {
+					label = "firmware";
+					reg = <0x20000 0x7a0000>;
+				};
+
+				partition@7c0000 {
+					label = "config";
+					reg = <0x7c0000 0x10000>;
+				};
+
+				rom: partition@7d0000 {
+					label = "rom";
+					reg = <0x7d0000 0x10000>;
+				};
+
+				partition@7e0000 {
+					label = "romfile";
+					reg = <0x7e0000 0x10000>;
+				};
+
+				radio: partition@7f0000 {
+					label = "radio";
+					reg = <0x7f0000 0x10000>;
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		state_default: pinctrl0 {
+			gpio {
+				ralink,group = "i2c", "uartf", "rgmii1", "rgmii2", "wled", "nd_sd";
+				ralink,function = "gpio";
+			};
+		};
+	};
+
+	ethernet@10100000 {
+		pinctrl-names = "default";
+		pinctrl-0 = <&ephy_pins>;
+
+		mtd-mac-address = <&rom 0xf100>;
+		ralink,port-map = "wllll";
+	};
+
+	gsw@10110000 {
+		ralink,port4 = "ephy";
+	};
+
+	wmac@10180000 {
+		ralink,mtd-eeprom = <&radio 0>;
+	};
+
+	pcie@10140000 {
+		status = "okay";
+
+		pcie-bridge {
+			mt76@0,0 {
+				reg = <0x0000 0 0 0 0>;
+				device_type = "pci";
+				mediatek,mtd-eeprom = <&radio 32768>;
+				mediatek,2ghz = <0>;
+			};
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+	};
+
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		poll-interval = <20>;
+	};
+};