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authorFelix Fietkau <nbd@openwrt.org>2015-01-18 20:16:44 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-01-18 20:16:44 +0000
commit69ee1807edca271e31804efb033fee92c111b738 (patch)
treecb8e692777d6e817565cf1ccba6348d1d94063c2 /target/linux/ramips/dts/rt2880.dtsi
parenta5b578c2d9a9c0384b395fc57ccd071e7cff2ede (diff)
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ralink: add ethernet fe and esw reset control bit
Signed-off-by: michael lee <igvtee@gmail.com> SVN-Revision: 44042
Diffstat (limited to 'target/linux/ramips/dts/rt2880.dtsi')
-rw-r--r--target/linux/ramips/dts/rt2880.dtsi8
1 files changed, 8 insertions, 0 deletions
diff --git a/target/linux/ramips/dts/rt2880.dtsi b/target/linux/ramips/dts/rt2880.dtsi
index 646cb6a..feabe42 100644
--- a/target/linux/ramips/dts/rt2880.dtsi
+++ b/target/linux/ramips/dts/rt2880.dtsi
@@ -149,6 +149,11 @@
};
};
+ rstctrl: rstctrl {
+ compatible = "ralink,rt2880-reset";
+ #reset-cells = <1>;
+ };
+
ethernet@400000 {
compatible = "ralink,rt2880-eth";
reg = <0x00400000 10000>;
@@ -156,6 +161,9 @@
#address-cells = <1>;
#size-cells = <0>;
+ resets = <&rstctrl 18>;
+ reset-names = "fe";
+
interrupt-parent = <&cpuintc>;
interrupts = <5>;