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| author | John Crispin <john@openwrt.org> | 2013-08-14 18:15:15 +0000 |
|---|---|---|
| committer | John Crispin <john@openwrt.org> | 2013-08-14 18:15:15 +0000 |
| commit | 9e5b0cc19cebf6ed876c7eace13b887b46e518c0 (patch) | |
| tree | f246f12adca3e91f5e3708e97c7a4add05cc0ce3 /target/linux/ramips/patches-3.10/0014-MIPS-ralink-mt7620-add-spi-clock-definition.patch | |
| parent | 2864fb107f00531df0b114d52334d3e00fa5d6c2 (diff) | |
| download | mtk-20170518-9e5b0cc19cebf6ed876c7eace13b887b46e518c0.zip mtk-20170518-9e5b0cc19cebf6ed876c7eace13b887b46e518c0.tar.gz mtk-20170518-9e5b0cc19cebf6ed876c7eace13b887b46e518c0.tar.bz2 | |
ramips: update v3.10 patches
Sync the patches with those sent upstream for v3.12.
Signed-off-by: John Crispin <blogic@openwrt.org>
SVN-Revision: 37778
Diffstat (limited to 'target/linux/ramips/patches-3.10/0014-MIPS-ralink-mt7620-add-spi-clock-definition.patch')
| -rw-r--r-- | target/linux/ramips/patches-3.10/0014-MIPS-ralink-mt7620-add-spi-clock-definition.patch | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/target/linux/ramips/patches-3.10/0014-MIPS-ralink-mt7620-add-spi-clock-definition.patch b/target/linux/ramips/patches-3.10/0014-MIPS-ralink-mt7620-add-spi-clock-definition.patch new file mode 100644 index 0000000..16b89dc --- /dev/null +++ b/target/linux/ramips/patches-3.10/0014-MIPS-ralink-mt7620-add-spi-clock-definition.patch @@ -0,0 +1,22 @@ +From d0da9f08ef37e9f639e3b7995d722684da2410a2 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 23 May 2013 18:46:25 +0200 +Subject: [PATCH 14/25] MIPS: ralink: mt7620: add spi clock definition + +The definition of the spi clock is missing. + +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/ralink/mt7620.c | 1 + + 1 file changed, 1 insertion(+) + +--- a/arch/mips/ralink/mt7620.c ++++ b/arch/mips/ralink/mt7620.c +@@ -167,6 +167,7 @@ void __init ralink_clk_init(void) + ralink_clk_add("cpu", cpu_rate); + ralink_clk_add("10000100.timer", 40000000); + ralink_clk_add("10000500.uart", 40000000); ++ ralink_clk_add("10000b00.spi", 40000000); + ralink_clk_add("10000c00.uartlite", 40000000); + } + |