ramips: add ralink v3.10 support

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 37331

34 files changed, 13977 insertions, 0 deletions

diff --git a/target/linux/ramips/patches-3.10/0001-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch b/target/linux/ramips/patches-3.10/0001-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
new file mode 100644
index 0000000..26556b6
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0001-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch
@@ -0,0 +1,78 @@
+From a1f29e15505226c6bc3a714daf91edccfc3a9e13 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:08:11 +0200
+Subject: [PATCH 01/33] MIPS: use set_mode() to enable/disable the cevt-r4k
+ irq
+
+ Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/kernel/cevt-r4k.c |   39 ++++++++++++++++++++++++++-------------
+ 1 file changed, 26 insertions(+), 13 deletions(-)
+
+diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
+index 02033ea..da4a003 100644
+--- a/arch/mips/kernel/cevt-r4k.c
++++ b/arch/mips/kernel/cevt-r4k.c
+@@ -38,12 +38,6 @@ static int mips_next_event(unsigned long delta,
+ 
+ #endif /* CONFIG_MIPS_MT_SMTC */
+ 
+-void mips_set_clock_mode(enum clock_event_mode mode,
+-				struct clock_event_device *evt)
+-{
+-	/* Nothing to do ...  */
+-}
+-
+ DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+ int cp0_timer_irq_installed;
+ 
+@@ -90,6 +84,32 @@ struct irqaction c0_compare_irqaction = {
+ 	.name = "timer",
+ };
+ 
++void mips_set_clock_mode(enum clock_event_mode mode,
++				struct clock_event_device *evt)
++{
++	switch (mode) {
++	case CLOCK_EVT_MODE_ONESHOT:
++		if (cp0_timer_irq_installed)
++			break;
++
++		cp0_timer_irq_installed = 1;
++
++		setup_irq(evt->irq, &c0_compare_irqaction);
++		break;
++
++	case CLOCK_EVT_MODE_SHUTDOWN:
++		if (!cp0_timer_irq_installed)
++			break;
++
++		cp0_timer_irq_installed = 0;
++		free_irq(evt->irq, &c0_compare_irqaction);
++		break;
++
++	default:
++		pr_err("Unhandeled mips clock_mode\n");
++		break;
++	}
++}
+ 
+ void mips_event_handler(struct clock_event_device *dev)
+ {
+@@ -215,13 +235,6 @@ int __cpuinit r4k_clockevent_init(void)
+ #endif
+ 	clockevents_register_device(cd);
+ 
+-	if (cp0_timer_irq_installed)
+-		return 0;
+-
+-	cp0_timer_irq_installed = 1;
+-
+-	setup_irq(irq, &c0_compare_irqaction);
+-
+ 	return 0;
+ }
+ 
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0002-MIPS-ralink-add-pinmux-driver.patch b/target/linux/ramips/patches-3.10/0002-MIPS-ralink-add-pinmux-driver.patch
new file mode 100644
index 0000000..f515bb3
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0002-MIPS-ralink-add-pinmux-driver.patch
@@ -0,0 +1,141 @@
+From 9a3055dad80db43aeb22b247512e18e8f06bf54c Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 22 Apr 2013 23:11:42 +0200
+Subject: [PATCH 02/33] MIPS: ralink: add pinmux driver
+
+Add code to setup the pinmux on ralonk SoC. The SoC has a single 32 bit register
+for this functionality with simple on/off bits. Building a full featured pinctrl
+driver would be overkill.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile |    2 +-
+ arch/mips/ralink/common.h |    2 ++
+ arch/mips/ralink/of.c     |    2 ++
+ arch/mips/ralink/pinmux.c |   77 +++++++++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 82 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/ralink/pinmux.c
+
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 38cf1a8..341b4de 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -6,7 +6,7 @@
+ # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
+ # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ 
+-obj-y := prom.o of.o reset.o clk.o irq.o
++obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
+ 
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+diff --git a/arch/mips/ralink/common.h b/arch/mips/ralink/common.h
+index 83144c3..f113fd6 100644
+--- a/arch/mips/ralink/common.h
++++ b/arch/mips/ralink/common.h
+@@ -50,4 +50,6 @@ extern void prom_soc_init(struct ralink_soc_info *soc_info);
+ 
+ __iomem void *plat_of_remap_node(const char *node);
+ 
++void ralink_pinmux(void);
++
+ #endif /* _RALINK_COMMON_H__ */
+diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
+index 6b5f340..b25c1f2 100644
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -110,6 +110,8 @@ static int __init plat_of_setup(void)
+ 	if (of_platform_populate(NULL, of_ids, NULL, NULL))
+ 		panic("failed to populate DT\n");
+ 
++	ralink_pinmux();
++
+ 	return 0;
+ }
+ 
+diff --git a/arch/mips/ralink/pinmux.c b/arch/mips/ralink/pinmux.c
+new file mode 100644
+index 0000000..1720216
+--- /dev/null
++++ b/arch/mips/ralink/pinmux.c
+@@ -0,0 +1,77 @@
++/*
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/kernel.h>
++#include <linux/of.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "common.h"
++
++#define SYSC_REG_GPIO_MODE	0x60
++
++static int ralink_mux_mask(const char *name, struct ralink_pinmux_grp *grps, u32* mask)
++{
++	for (; grps && grps->name; grps++)
++		if (!strcmp(grps->name, name)) {
++			*mask = grps->mask;
++			return 0;
++		}
++
++	return -1;
++}
++
++void ralink_pinmux(void)
++{
++	const __be32 *wdt;
++	struct device_node *np;
++	struct property *prop;
++	const char *uart, *pin;
++	u32 mode = 0;
++	int m;
++
++	np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-sysc");
++	if (!np)
++		return;
++
++	of_property_for_each_string(np, "ralink,gpiomux", prop, pin) {
++		if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
++			mode |= m;
++			pr_debug("pinmux: registered gpiomux \"%s\"\n", pin);
++		} else {
++			pr_err("pinmux: failed to load \"%s\"\n", pin);
++		}
++	}
++
++	of_property_for_each_string(np, "ralink,pinmux", prop, pin) {
++		if (!ralink_mux_mask(pin, rt_gpio_pinmux.mode, &m)) {
++			mode &= ~m;
++			pr_debug("pinmux: registered pinmux \"%s\"\n", pin);
++		} else {
++			pr_err("pinmux: failed to load group \"%s\"\n", pin);
++		}
++	}
++
++	of_property_read_string(np, "ralink,uartmux", &uart);
++	if (uart) {
++		mode &= ~(rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift);
++		if (ralink_mux_mask(uart, rt_gpio_pinmux.uart, &m)) {
++			pr_err("pinmux: failed to load uartmux \"%s\"\n", uart);
++			mode |= rt_gpio_pinmux.uart_mask << rt_gpio_pinmux.uart_shift;
++		} else {
++			mode |= m << rt_gpio_pinmux.uart_shift;
++			pr_debug("pinmux: registered uartmux \"%s\"\n", uart);
++		}
++	}
++
++	wdt = of_get_property(np, "ralink,wdtmux", NULL);
++	if (wdt && *wdt && rt_gpio_pinmux.wdt_reset)
++		rt_gpio_pinmux.wdt_reset();
++
++	rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
++}
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0003-MIPS-ralink-add-support-for-periodic-timer-irq.patch b/target/linux/ramips/patches-3.10/0003-MIPS-ralink-add-support-for-periodic-timer-irq.patch
new file mode 100644
index 0000000..2d80095
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0003-MIPS-ralink-add-support-for-periodic-timer-irq.patch
@@ -0,0 +1,228 @@
+From 298e990777004a6a72b1c95af5a2cd984c56135d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 23 Mar 2013 19:44:41 +0100
+Subject: [PATCH 03/33] MIPS: ralink: add support for periodic timer irq
+
+Adds a driver for the periodic timer found on Ralink SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile |    2 +-
+ arch/mips/ralink/timer.c  |  192 +++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 193 insertions(+), 1 deletion(-)
+ create mode 100644 arch/mips/ralink/timer.c
+
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 341b4de..cae7d88 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -6,7 +6,7 @@
+ # Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
+ # Copyright (C) 2013 John Crispin <blogic@openwrt.org>
+ 
+-obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o
++obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
+ 
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
+new file mode 100644
+index 0000000..0a6856c
+--- /dev/null
++++ b/arch/mips/ralink/timer.c
+@@ -0,0 +1,192 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++*/
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/interrupt.h>
++#include <linux/timer.h>
++#include <linux/of_gpio.h>
++#include <linux/clk.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define TIMER_REG_TMRSTAT		0x00
++#define TIMER_REG_TMR0LOAD		0x10
++#define TIMER_REG_TMR0CTL		0x18
++
++#define TMRSTAT_TMR0INT			BIT(0)
++
++#define TMR0CTL_ENABLE			BIT(7)
++#define TMR0CTL_MODE_PERIODIC		BIT(4)
++#define TMR0CTL_PRESCALER		1
++#define TMR0CTL_PRESCALE_VAL		(0xf - TMR0CTL_PRESCALER)
++#define TMR0CTL_PRESCALE_DIV		(65536 / BIT(TMR0CTL_PRESCALER))
++
++struct rt_timer {
++	struct device	*dev;
++	void __iomem	*membase;
++	int		irq;
++	unsigned long	timer_freq;
++	unsigned long	timer_div;
++};
++
++static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
++{
++	__raw_writel(val, rt->membase + reg);
++}
++
++static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
++{
++	return __raw_readl(rt->membase + reg);
++}
++
++static irqreturn_t rt_timer_irq(int irq, void *_rt)
++{
++	struct rt_timer *rt =  (struct rt_timer *) _rt;
++
++	rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
++	rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
++
++	return IRQ_HANDLED;
++}
++
++
++static int rt_timer_request(struct rt_timer *rt)
++{
++	int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
++						dev_name(rt->dev), rt);
++	if (err) {
++		dev_err(rt->dev, "failed to request irq\n");
++	} else {
++		u32 t = TMR0CTL_MODE_PERIODIC | TMR0CTL_PRESCALE_VAL;
++		rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
++	}
++	return err;
++}
++
++static void rt_timer_free(struct rt_timer *rt)
++{
++	free_irq(rt->irq, rt);
++}
++
++static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
++{
++	if (rt->timer_freq < divisor)
++		rt->timer_div = rt->timer_freq;
++	else
++		rt->timer_div = divisor;
++
++	rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
++
++	return 0;
++}
++
++static int rt_timer_enable(struct rt_timer *rt)
++{
++	u32 t;
++
++	rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
++
++	t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
++	t |= TMR0CTL_ENABLE;
++	rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
++
++	return 0;
++}
++
++static void rt_timer_disable(struct rt_timer *rt)
++{
++	u32 t;
++
++	t = rt_timer_r32(rt, TIMER_REG_TMR0CTL);
++	t &= ~TMR0CTL_ENABLE;
++	rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
++}
++
++static int rt_timer_probe(struct platform_device *pdev)
++{
++	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	struct rt_timer *rt;
++	struct clk *clk;
++
++	if (!res) {
++		dev_err(&pdev->dev, "no memory resource found\n");
++		return -EINVAL;
++	}
++
++	rt = devm_kzalloc(&pdev->dev, sizeof(*rt), GFP_KERNEL);
++	if (!rt) {
++		dev_err(&pdev->dev, "failed to allocate memory\n");
++		return -ENOMEM;
++	}
++
++	rt->irq = platform_get_irq(pdev, 0);
++	if (!rt->irq) {
++		dev_err(&pdev->dev, "failed to load irq\n");
++		return -ENOENT;
++	}
++
++	rt->membase = devm_request_and_ioremap(&pdev->dev, res);
++	if (!rt->membase) {
++		dev_err(&pdev->dev, "failed to ioremap\n");
++		return -ENOMEM;
++	}
++
++	clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(clk)) {
++		dev_err(&pdev->dev, "failed get clock rate\n");
++		return PTR_ERR(clk);
++	}
++
++	rt->timer_freq = clk_get_rate(clk) / TMR0CTL_PRESCALE_DIV;
++	if (!rt->timer_freq)
++		return -EINVAL;
++
++	rt->dev = &pdev->dev;
++	platform_set_drvdata(pdev, rt);
++
++	rt_timer_request(rt);
++	rt_timer_config(rt, 2);
++	rt_timer_enable(rt);
++
++	dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
++
++	return 0;
++}
++
++static int rt_timer_remove(struct platform_device *pdev)
++{
++	struct rt_timer *rt = platform_get_drvdata(pdev);
++
++	rt_timer_disable(rt);
++	rt_timer_free(rt);
++
++	return 0;
++}
++
++static const struct of_device_id rt_timer_match[] = {
++	{ .compatible = "ralink,rt2880-timer" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt_timer_match);
++
++static struct platform_driver rt_timer_driver = {
++	.probe = rt_timer_probe,
++	.remove = rt_timer_remove,
++	.driver = {
++		.name		= "rt-timer",
++		.owner          = THIS_MODULE,
++		.of_match_table	= rt_timer_match
++	},
++};
++
++module_platform_driver(rt_timer_driver);
++
++MODULE_DESCRIPTION("Ralink RT2880 timer");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
++MODULE_LICENSE("GPL");
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0004-MIPS-ralink-add-rt_sysc_m32-helper.patch b/target/linux/ramips/patches-3.10/0004-MIPS-ralink-add-rt_sysc_m32-helper.patch
new file mode 100644
index 0000000..7466c4d
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0004-MIPS-ralink-add-rt_sysc_m32-helper.patch
@@ -0,0 +1,31 @@
+From 3af962f91035ae4500e63c758c49f1c067bdae09 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 19 May 2013 00:42:23 +0200
+Subject: [PATCH 04/33] MIPS: ralink: add rt_sysc_m32 helper
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/ralink_regs.h |    7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+index 5a508f9..bd93014 100644
+--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
++++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
+@@ -26,6 +26,13 @@ static inline u32 rt_sysc_r32(unsigned reg)
+ 	return __raw_readl(rt_sysc_membase + reg);
+ }
+ 
++static inline void rt_sysc_m32(u32 clr, u32 set, unsigned reg)
++{
++	u32 val = rt_sysc_r32(reg) & ~clr;
++
++	__raw_writel(val | set, rt_sysc_membase + reg);
++}
++
+ static inline void rt_memc_w32(u32 val, unsigned reg)
+ {
+ 	__raw_writel(val, rt_memc_membase + reg);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0005-MIPS-ralink-make-mt7620-ram-detect-verbose.patch b/target/linux/ramips/patches-3.10/0005-MIPS-ralink-make-mt7620-ram-detect-verbose.patch
new file mode 100644
index 0000000..c777419
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0005-MIPS-ralink-make-mt7620-ram-detect-verbose.patch
@@ -0,0 +1,39 @@
+From 3f6b346e1dd83c4f43d94aefa0520ffdfafd5f0b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 20 May 2013 20:30:11 +0200
+Subject: [PATCH 05/33] MIPS: ralink: make mt7620 ram detect verbose
+
+Make the code print which of SDRAM, DDR1 or DDR2 was detected.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c |    3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+index 0018b1a..ccdec5a 100644
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -214,16 +214,19 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+ 
+ 	switch (dram_type) {
+ 	case SYSCFG0_DRAM_TYPE_SDRAM:
++		pr_info("Board has SDRAM\n");
+ 		soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
+ 		soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
+ 		break;
+ 
+ 	case SYSCFG0_DRAM_TYPE_DDR1:
++		pr_info("Board has DDR1\n");
+ 		soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
+ 		soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
+ 		break;
+ 
+ 	case SYSCFG0_DRAM_TYPE_DDR2:
++		pr_info("Board has DDR2\n");
+ 		soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
+ 		soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
+ 		break;
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch b/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch
new file mode 100644
index 0000000..c2d959d
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0006-MIPS-ralink-add-verbose-pmu-info.patch
@@ -0,0 +1,64 @@
+From 74339d6eab7a37f7c629b737bf686d30e5014ce2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 20 May 2013 20:57:09 +0200
+Subject: [PATCH 06/33] MIPS: ralink: add verbose pmu info
+
+Print the PMU and LDO settings on boot.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c |   26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+index ccdec5a..62356a0 100644
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -20,6 +20,22 @@
+ 
+ #include "common.h"
+ 
++/* analog */
++#define PMU0_CFG		0x88
++#define PMU_SW_SET		BIT(28)
++#define A_DCDC_EN		BIT(24)
++#define A_SSC_PERI		BIT(19)
++#define A_SSC_GEN		BIT(18)
++#define A_SSC_M			0x3
++#define A_SSC_S			16
++#define A_DLY_M			0x7
++#define A_DLY_S			8
++#define A_VTUNE_M		0xff
++
++/* digital */
++#define PMU1_CFG		0x8C
++#define DIG_SW_SEL		BIT(25)
++
+ /* does the board have sdram or ddram */
+ static int dram_type;
+ 
+@@ -187,6 +203,8 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+ 	u32 n1;
+ 	u32 rev;
+ 	u32 cfg0;
++	u32 pmu0;
++	u32 pmu1;
+ 
+ 	n0 = __raw_readl(sysc + SYSC_REG_CHIP_NAME0);
+ 	n1 = __raw_readl(sysc + SYSC_REG_CHIP_NAME1);
+@@ -234,4 +252,12 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+ 		BUG();
+ 	}
+ 	soc_info->mem_base = MT7620_DRAM_BASE;
++
++	pmu0 = __raw_readl(sysc + PMU0_CFG);
++	pmu1 = __raw_readl(sysc + PMU1_CFG);
++
++	pr_info("Analog PMU set to %s control\n",
++		(pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
++	pr_info("Digital PMU set to %s control\n",
++		(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
+ }
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0007-MIPS-ralink-adds-a-bootrom-dumper-module.patch b/target/linux/ramips/patches-3.10/0007-MIPS-ralink-adds-a-bootrom-dumper-module.patch
new file mode 100644
index 0000000..d22a1c9
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0007-MIPS-ralink-adds-a-bootrom-dumper-module.patch
@@ -0,0 +1,83 @@
+From 71409a190a0c8e3597cae7d46321742e29d8994b Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Tue, 21 May 2013 15:50:31 +0200
+Subject: [PATCH 07/33] MIPS: ralink: adds a bootrom dumper module
+
+This patch adds a trivial driver that allows userland to extract the bootrom of
+a SoC via debugfs.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile  |    2 ++
+ arch/mips/ralink/bootrom.c |   48 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 50 insertions(+)
+ create mode 100644 arch/mips/ralink/bootrom.c
+
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index cae7d88..5fa6129 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -15,4 +15,6 @@ obj-$(CONFIG_SOC_MT7620) += mt7620.o
+ 
+ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+ 
++obj-$(CONFIG_DEBUG_FS) += bootrom.o
++
+ obj-y += dts/
+diff --git a/arch/mips/ralink/bootrom.c b/arch/mips/ralink/bootrom.c
+new file mode 100644
+index 0000000..f926f6f
+--- /dev/null
++++ b/arch/mips/ralink/bootrom.c
+@@ -0,0 +1,48 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/debugfs.h>
++#include <linux/seq_file.h>
++
++#define BOOTROM_OFFSET	0x10118000
++#define BOOTROM_SIZE	0x8000
++
++static void __iomem *membase = (void __iomem*) KSEG1ADDR(BOOTROM_OFFSET);
++
++static int bootrom_show(struct seq_file *s, void *unused)
++{
++	seq_write(s, membase, BOOTROM_SIZE);
++
++	return 0;
++}
++
++static int bootrom_open(struct inode *inode, struct file *file)
++{
++	return single_open(file, bootrom_show, NULL);
++}
++
++static const struct file_operations bootrom_file_ops = {
++	.open		= bootrom_open,
++	.read		= seq_read,
++	.llseek		= seq_lseek,
++	.release	= single_release,
++};
++
++static int bootrom_setup(void)
++{
++	if (!debugfs_create_file("bootrom", 0444,
++			NULL, NULL, &bootrom_file_ops)) {
++		pr_err("Failed to create bootrom debugfs file\n");
++
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++postcore_initcall(bootrom_setup);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0008-MIPS-ralink-add-illegal-access-driver.patch b/target/linux/ramips/patches-3.10/0008-MIPS-ralink-add-illegal-access-driver.patch
new file mode 100644
index 0000000..b79d5cd
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0008-MIPS-ralink-add-illegal-access-driver.patch
@@ -0,0 +1,121 @@
+From 46446fcfc6e823005ebe71357b5995524e75542c Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 16 May 2013 23:28:23 +0200
+Subject: [PATCH 08/33] MIPS: ralink: add illegal access driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Makefile  |    2 +
+ arch/mips/ralink/ill_acc.c |   87 ++++++++++++++++++++++++++++++++++++++++++++
+ 2 files changed, 89 insertions(+)
+ create mode 100644 arch/mips/ralink/ill_acc.c
+
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 5fa6129..03af636 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -8,6 +8,8 @@
+ 
+ obj-y := prom.o of.o reset.o clk.o irq.o pinmux.o timer.o
+ 
++obj-$(CONFIG_RALINK_ILL_ACC) += ill_acc.o
++
+ obj-$(CONFIG_SOC_RT288X) += rt288x.o
+ obj-$(CONFIG_SOC_RT305X) += rt305x.o
+ obj-$(CONFIG_SOC_RT3883) += rt3883.o
+diff --git a/arch/mips/ralink/ill_acc.c b/arch/mips/ralink/ill_acc.c
+new file mode 100644
+index 0000000..4a3f696
+--- /dev/null
++++ b/arch/mips/ralink/ill_acc.c
+@@ -0,0 +1,87 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/interrupt.h>
++#include <linux/of_platform.h>
++#include <linux/of_irq.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define REG_ILL_ACC_ADDR	0x10
++#define REG_ILL_ACC_TYPE	0x14
++
++#define ILL_INT_STATUS		BIT(31)
++#define ILL_ACC_WRITE		BIT(30)
++#define ILL_ACC_LEN_M		0xff
++#define ILL_ACC_OFF_M		0xf
++#define ILL_ACC_OFF_S		16
++#define ILL_ACC_ID_M		0x7
++#define ILL_ACC_ID_S		8
++
++#define	DRV_NAME		"ill_acc"
++
++static const char *ill_acc_ids[] = {
++	"cpu", "dma", "ppe", "pdma rx","pdma tx", "pci/e", "wmac", "usb",
++};
++
++static irqreturn_t ill_acc_irq_handler(int irq, void *_priv)
++{
++	struct device *dev = (struct device *) _priv;
++	u32 addr = rt_memc_r32(REG_ILL_ACC_ADDR);
++	u32 type = rt_memc_r32(REG_ILL_ACC_TYPE);
++
++	dev_err(dev, "illegal %s access from %s - addr:0x%08x offset:%d len:%d\n",
++		(type & ILL_ACC_WRITE) ? ("write") : ("read"),
++		ill_acc_ids[(type >> ILL_ACC_ID_S) & ILL_ACC_ID_M],
++		addr, (type >> ILL_ACC_OFF_S) & ILL_ACC_OFF_M,
++		type & ILL_ACC_LEN_M);
++
++	rt_memc_w32(REG_ILL_ACC_TYPE, REG_ILL_ACC_TYPE);
++
++	return IRQ_HANDLED;
++}
++
++static int __init ill_acc_of_setup(void)
++{
++	struct platform_device *pdev;
++	struct device_node *np;
++	int irq;
++
++	/* somehow this driver breaks on RT5350 */
++	if (of_machine_is_compatible("ralink,rt5350-soc"))
++		return -EINVAL;
++
++	np = of_find_compatible_node(NULL, NULL, "ralink,rt3050-memc");
++	if (!np)
++		return -EINVAL;
++
++	pdev = of_find_device_by_node(np);
++	if (!pdev) {
++		pr_err("%s: failed to lookup pdev\n", np->name);
++		return -EINVAL;
++	}
++
++	irq = irq_of_parse_and_map(np, 0);
++        if (!irq) {
++		dev_err(&pdev->dev, "failed to get irq\n");
++		return -EINVAL;
++	}
++
++	if (request_irq(irq, ill_acc_irq_handler, 0, "ill_acc", &pdev->dev)) {
++		dev_err(&pdev->dev, "failed to request irq\n");
++		return -EINVAL;
++	}
++
++	rt_memc_w32(ILL_INT_STATUS, REG_ILL_ACC_TYPE);
++
++	dev_info(&pdev->dev, "irq registered\n");
++
++	return 0;
++}
++
++arch_initcall(ill_acc_of_setup);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0009-MIPS-ralink-workaround-DTB-memory-issue.patch b/target/linux/ramips/patches-3.10/0009-MIPS-ralink-workaround-DTB-memory-issue.patch
new file mode 100644
index 0000000..cf7168b
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0009-MIPS-ralink-workaround-DTB-memory-issue.patch
@@ -0,0 +1,29 @@
+From 070a389ae536a75b9184784f625949c215c533b6 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 23 May 2013 18:50:56 +0200
+Subject: [PATCH 09/33] MIPS: ralink: workaround DTB memory issue
+
+If the DTB is too big a bug happens on boot when init ram is freed.
+This is a temporary fix until the real cause is found.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/of.c |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
+index b25c1f2..8efb02b 100644
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -74,7 +74,7 @@ void __init device_tree_init(void)
+ 	unflatten_device_tree();
+ 
+ 	/* free the space reserved for the dt blob */
+-	free_bootmem(base, size);
++	//free_bootmem(base, size);
+ }
+ 
+ void __init plat_mem_setup(void)
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch b/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
new file mode 100644
index 0000000..ebb5898
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0010-MIPS-ralink-add-spi-clock-definition-to-mt7620a.patch
@@ -0,0 +1,25 @@
+From 5340673ba16e3c8c9c1406d5ab84aca82e83e2ce Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 23 May 2013 18:46:25 +0200
+Subject: [PATCH 10/33] MIPS: ralink: add spi clock definition to mt7620a
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c |    1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+index 62356a0..96422e5 100644
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -183,6 +183,7 @@ void __init ralink_clk_init(void)
+ 	ralink_clk_add("cpu", cpu_rate);
+ 	ralink_clk_add("10000100.timer", 40000000);
+ 	ralink_clk_add("10000500.uart", 40000000);
++	ralink_clk_add("10000b00.spi", 40000000);
+ 	ralink_clk_add("10000c00.uartlite", 40000000);
+ }
+ 
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0011-PCI-MIPS-adds-rt2880-pci-support.patch b/target/linux/ramips/patches-3.10/0011-PCI-MIPS-adds-rt2880-pci-support.patch
new file mode 100644
index 0000000..6641985
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0011-PCI-MIPS-adds-rt2880-pci-support.patch
@@ -0,0 +1,329 @@
+From 5d57ace094803c95230643941a47d749ff81d022 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 21 Mar 2013 18:27:29 +0100
+Subject: [PATCH 11/33] PCI: MIPS: adds rt2880 pci support
+
+Add support for the pci found on the rt2880 SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile     |    1 +
+ arch/mips/pci/pci-rt2880.c |  281 ++++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/Kconfig   |    1 +
+ 3 files changed, 283 insertions(+)
+ create mode 100644 arch/mips/pci/pci-rt2880.c
+
+diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
+index 2cb1d31..77974ba 100644
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -41,6 +41,7 @@ obj-$(CONFIG_SIBYTE_BCM1x80)	+= pci-bcm1480.o pci-bcm1480ht.o
+ obj-$(CONFIG_SNI_RM)		+= fixup-sni.o ops-sni.o
+ obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
++obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
+ obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
+ obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
+diff --git a/arch/mips/pci/pci-rt2880.c b/arch/mips/pci/pci-rt2880.c
+new file mode 100644
+index 0000000..e2c4730
+--- /dev/null
++++ b/arch/mips/pci/pci-rt2880.c
+@@ -0,0 +1,281 @@
++/*
++ *  Ralink RT288x SoC PCI register definitions
++ *
++ *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
++ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_platform.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++
++#include <asm/mach-ralink/rt288x.h>
++
++#define RT2880_PCI_BASE		0x00440000
++#define RT288X_CPU_IRQ_PCI	4
++
++#define RT2880_PCI_MEM_BASE	0x20000000
++#define RT2880_PCI_MEM_SIZE	0x10000000
++#define RT2880_PCI_IO_BASE	0x00460000
++#define RT2880_PCI_IO_SIZE	0x00010000
++
++#define RT2880_PCI_REG_PCICFG_ADDR	0x00
++#define RT2880_PCI_REG_PCIMSK_ADDR	0x0c
++#define RT2880_PCI_REG_BAR0SETUP_ADDR	0x10
++#define RT2880_PCI_REG_IMBASEBAR0_ADDR	0x18
++#define RT2880_PCI_REG_CONFIG_ADDR	0x20
++#define RT2880_PCI_REG_CONFIG_DATA	0x24
++#define RT2880_PCI_REG_MEMBASE		0x28
++#define RT2880_PCI_REG_IOBASE		0x2c
++#define RT2880_PCI_REG_ID		0x30
++#define RT2880_PCI_REG_CLASS		0x34
++#define RT2880_PCI_REG_SUBID		0x38
++#define RT2880_PCI_REG_ARBCTL		0x80
++
++static void __iomem *rt2880_pci_base;
++static DEFINE_SPINLOCK(rt2880_pci_lock);
++
++static u32 rt2880_pci_reg_read(u32 reg)
++{
++	return readl(rt2880_pci_base + reg);
++}
++
++static void rt2880_pci_reg_write(u32 val, u32 reg)
++{
++	writel(val, rt2880_pci_base + reg);
++}
++
++static inline u32 rt2880_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
++					 unsigned int func, unsigned int where)
++{
++	return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
++		0x80000000);
++}
++
++static int rt2880_pci_config_read(struct pci_bus *bus, unsigned int devfn,
++				  int where, int size, u32 *val)
++{
++	unsigned long flags;
++	u32 address;
++	u32 data;
++
++	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
++					 PCI_FUNC(devfn), where);
++
++	spin_lock_irqsave(&rt2880_pci_lock, flags);
++	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
++	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++
++	switch (size) {
++	case 1:
++		*val = (data >> ((where & 3) << 3)) & 0xff;
++		break;
++	case 2:
++		*val = (data >> ((where & 3) << 3)) & 0xffff;
++		break;
++	case 4:
++		*val = data;
++		break;
++	}
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int rt2880_pci_config_write(struct pci_bus *bus, unsigned int devfn,
++				   int where, int size, u32 val)
++{
++	unsigned long flags;
++	u32 address;
++	u32 data;
++
++	address = rt2880_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
++					 PCI_FUNC(devfn), where);
++
++	spin_lock_irqsave(&rt2880_pci_lock, flags);
++	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++	data = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
++
++	switch (size) {
++	case 1:
++		data = (data & ~(0xff << ((where & 3) << 3))) |
++		       (val << ((where & 3) << 3));
++		break;
++	case 2:
++		data = (data & ~(0xffff << ((where & 3) << 3))) |
++		       (val << ((where & 3) << 3));
++		break;
++	case 4:
++		data = val;
++		break;
++	}
++
++	rt2880_pci_reg_write(data, RT2880_PCI_REG_CONFIG_DATA);
++	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static struct pci_ops rt2880_pci_ops = {
++	.read	= rt2880_pci_config_read,
++	.write	= rt2880_pci_config_write,
++};
++
++static struct resource rt2880_pci_mem_resource = {
++	.name	= "PCI MEM space",
++	.start	= RT2880_PCI_MEM_BASE,
++	.end	= RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
++	.flags	= IORESOURCE_MEM,
++};
++
++static struct resource rt2880_pci_io_resource = {
++	.name	= "PCI IO space",
++	.start	= RT2880_PCI_IO_BASE,
++	.end	= RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
++	.flags	= IORESOURCE_IO,
++};
++
++static struct pci_controller rt2880_pci_controller = {
++	.pci_ops	= &rt2880_pci_ops,
++	.mem_resource	= &rt2880_pci_mem_resource,
++	.io_resource	= &rt2880_pci_io_resource,
++};
++
++static inline u32 rt2880_pci_read_u32(unsigned long reg)
++{
++	unsigned long flags;
++	u32 address;
++	u32 ret;
++
++	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
++
++	spin_lock_irqsave(&rt2880_pci_lock, flags);
++	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++	ret = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
++	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++
++	return ret;
++}
++
++static inline void rt2880_pci_write_u32(unsigned long reg, u32 val)
++{
++	unsigned long flags;
++	u32 address;
++
++	address = rt2880_pci_get_cfgaddr(0, 0, 0, reg);
++
++	spin_lock_irqsave(&rt2880_pci_lock, flags);
++	rt2880_pci_reg_write(address, RT2880_PCI_REG_CONFIG_ADDR);
++	rt2880_pci_reg_write(val, RT2880_PCI_REG_CONFIG_DATA);
++	spin_unlock_irqrestore(&rt2880_pci_lock, flags);
++}
++
++int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	u16 cmd;
++	int irq = -1;
++
++	if (dev->bus->number != 0)
++		return irq;
++
++	switch (PCI_SLOT(dev->devfn)) {
++	case 0x00:
++		rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
++		(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
++		break;
++	case 0x11:
++		irq = RT288X_CPU_IRQ_PCI;
++		break;
++	default:
++		printk("%s:%s[%d] trying to alloc unknown pci irq\n",
++		       __FILE__, __func__, __LINE__);
++		BUG();
++		break;
++	}
++
++	pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
++	pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
++	pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
++	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
++	       PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK |
++	       PCI_COMMAND_SERR | PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
++	pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
++	pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE,
++			      dev->irq);
++	return irq;
++}
++
++static int rt288x_pci_probe(struct platform_device *pdev)
++{
++	void __iomem *io_map_base;
++	int i;
++
++	rt2880_pci_base = ioremap_nocache(RT2880_PCI_BASE, PAGE_SIZE);
++
++	io_map_base = ioremap(RT2880_PCI_IO_BASE, RT2880_PCI_IO_SIZE);
++	rt2880_pci_controller.io_map_base = (unsigned long) io_map_base;
++	set_io_port_base((unsigned long) io_map_base);
++
++	ioport_resource.start = RT2880_PCI_IO_BASE;
++	ioport_resource.end = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1;
++
++	rt2880_pci_reg_write(0, RT2880_PCI_REG_PCICFG_ADDR);
++	for(i = 0; i < 0xfffff; i++) {}
++
++	rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
++	rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
++	rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
++	rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
++	rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
++	rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
++	rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);
++	rt2880_pci_reg_write(0x28801814, RT2880_PCI_REG_SUBID);
++	rt2880_pci_reg_write(0x000c0000, RT2880_PCI_REG_PCIMSK_ADDR);
++
++	rt2880_pci_write_u32(PCI_BASE_ADDRESS_0, 0x08000000);
++	(void) rt2880_pci_read_u32(PCI_BASE_ADDRESS_0);
++
++	register_pci_controller(&rt2880_pci_controller);
++	return 0;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
++
++static const struct of_device_id rt288x_pci_match[] = {
++	{ .compatible = "ralink,rt288x-pci" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt288x_pci_match);
++
++static struct platform_driver rt288x_pci_driver = {
++	.probe = rt288x_pci_probe,
++	.driver = {
++		.name = "rt288x-pci",
++		.owner = THIS_MODULE,
++		.of_match_table = rt288x_pci_match,
++	},
++};
++
++int __init pcibios_init(void)
++{
++	int ret = platform_driver_register(&rt288x_pci_driver);
++	if (ret)
++		pr_info("rt288x-pci: Error registering platform driver!");
++	return ret;
++}
++
++arch_initcall(pcibios_init);
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 026e823..cd13da8 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -8,6 +8,7 @@ choice
+ 
+ 	config SOC_RT288X
+ 		bool "RT288x"
++		select HW_HAS_PCI
+ 
+ 	config SOC_RT305X
+ 		bool "RT305x"
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0012-PCI-MIPS-adds-rt3883-pci-support.patch b/target/linux/ramips/patches-3.10/0012-PCI-MIPS-adds-rt3883-pci-support.patch
new file mode 100644
index 0000000..ababca7
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0012-PCI-MIPS-adds-rt3883-pci-support.patch
@@ -0,0 +1,688 @@
+From b43e77699154356a39796d95ef316699dafe409d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 21 Mar 2013 17:34:08 +0100
+Subject: [PATCH 12/33] PCI: MIPS: adds rt3883 pci support
+
+Add support for the pcie found on the rt3883 SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile     |    1 +
+ arch/mips/pci/pci-rt3883.c |  640 ++++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/Kconfig   |    1 +
+ 3 files changed, 642 insertions(+)
+ create mode 100644 arch/mips/pci/pci-rt3883.c
+
+diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
+index 77974ba..3cbfd9b 100644
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -42,6 +42,7 @@ obj-$(CONFIG_SNI_RM)		+= fixup-sni.o ops-sni.o
+ obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
++obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
+ obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
+ obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
+diff --git a/arch/mips/pci/pci-rt3883.c b/arch/mips/pci/pci-rt3883.c
+new file mode 100644
+index 0000000..212c90b
+--- /dev/null
++++ b/arch/mips/pci/pci-rt3883.c
+@@ -0,0 +1,640 @@
++/*
++ *  Ralink RT3662/RT3883 SoC PCI support
++ *
++ *  Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  Parts of this file are based on Ralink's 2.6.21 BSP
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ralink/rt3883.h>
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define RT3883_MEMORY_BASE		0x00000000
++#define RT3883_MEMORY_SIZE		0x02000000
++
++#define RT3883_PCI_REG_PCICFG		0x00
++#define   RT3883_PCICFG_P2P_BR_DEVNUM_M 0xf
++#define   RT3883_PCICFG_P2P_BR_DEVNUM_S 16
++#define   RT3883_PCICFG_PCIRST		BIT(1)
++#define RT3883_PCI_REG_PCIRAW		0x04
++#define RT3883_PCI_REG_PCIINT		0x08
++#define RT3883_PCI_REG_PCIENA		0x0c
++
++#define RT3883_PCI_REG_CFGADDR		0x20
++#define RT3883_PCI_REG_CFGDATA		0x24
++#define RT3883_PCI_REG_MEMBASE		0x28
++#define RT3883_PCI_REG_IOBASE		0x2c
++#define RT3883_PCI_REG_ARBCTL		0x80
++
++#define RT3883_PCI_REG_BASE(_x)		(0x1000 + (_x) * 0x1000)
++#define RT3883_PCI_REG_BAR0SETUP(_x)	(RT3883_PCI_REG_BASE((_x)) + 0x10)
++#define RT3883_PCI_REG_IMBASEBAR0(_x)	(RT3883_PCI_REG_BASE((_x)) + 0x18)
++#define RT3883_PCI_REG_ID(_x)		(RT3883_PCI_REG_BASE((_x)) + 0x30)
++#define RT3883_PCI_REG_CLASS(_x)	(RT3883_PCI_REG_BASE((_x)) + 0x34)
++#define RT3883_PCI_REG_SUBID(_x)	(RT3883_PCI_REG_BASE((_x)) + 0x38)
++#define RT3883_PCI_REG_STATUS(_x)	(RT3883_PCI_REG_BASE((_x)) + 0x50)
++
++#define RT3883_PCI_MODE_NONE	0
++#define RT3883_PCI_MODE_PCI	BIT(0)
++#define RT3883_PCI_MODE_PCIE	BIT(1)
++#define RT3883_PCI_MODE_BOTH	(RT3883_PCI_MODE_PCI | RT3883_PCI_MODE_PCIE)
++
++#define RT3883_PCI_IRQ_COUNT	32
++
++#define RT3883_P2P_BR_DEVNUM	1
++
++struct rt3883_pci_controller {
++	void __iomem *base;
++	spinlock_t lock;
++
++	struct irq_domain *irq_domain;
++
++	struct pci_controller pci_controller;
++	struct resource io_res;
++	struct resource mem_res;
++
++	bool pcie_ready;
++	unsigned char p2p_devnum;
++};
++
++static inline struct rt3883_pci_controller *
++pci_bus_to_rt3883_controller(struct pci_bus *bus)
++{
++	struct pci_controller *hose;
++
++	hose = (struct pci_controller *) bus->sysdata;
++	return container_of(hose, struct rt3883_pci_controller, pci_controller);
++}
++
++static inline u32 rt3883_pci_r32(struct rt3883_pci_controller *rpc,
++				 unsigned reg)
++{
++	return ioread32(rpc->base + reg);
++}
++
++static inline void rt3883_pci_w32(struct rt3883_pci_controller *rpc,
++				  u32 val, unsigned reg)
++{
++	iowrite32(val, rpc->base + reg);
++}
++
++static inline u32 rt3883_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
++					 unsigned int func, unsigned int where)
++{
++	return ((bus << 16) | (slot << 11) | (func << 8) | (where & 0xfc) |
++		0x80000000);
++}
++
++static u32 rt3883_pci_read_cfg32(struct rt3883_pci_controller *rpc,
++			       unsigned bus, unsigned slot,
++			       unsigned func, unsigned reg)
++{
++	unsigned long flags;
++	u32 address;
++	u32 ret;
++
++	address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
++
++	spin_lock_irqsave(&rpc->lock, flags);
++	rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
++	ret = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
++	spin_unlock_irqrestore(&rpc->lock, flags);
++
++	return ret;
++}
++
++static void rt3883_pci_write_cfg32(struct rt3883_pci_controller *rpc,
++				 unsigned bus, unsigned slot,
++				 unsigned func, unsigned reg, u32 val)
++{
++	unsigned long flags;
++	u32 address;
++
++	address = rt3883_pci_get_cfgaddr(bus, slot, func, reg);
++
++	spin_lock_irqsave(&rpc->lock, flags);
++	rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
++	rt3883_pci_w32(rpc, val, RT3883_PCI_REG_CFGDATA);
++	spin_unlock_irqrestore(&rpc->lock, flags);
++}
++
++static void rt3883_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
++{
++	struct rt3883_pci_controller *rpc;
++	u32 pending;
++
++	rpc = irq_get_handler_data(irq);
++
++	pending = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIINT) &
++		  rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
++
++	if (!pending) {
++		spurious_interrupt();
++		return;
++	}
++
++	while (pending) {
++		unsigned bit = __ffs(pending);
++
++		irq = irq_find_mapping(rpc->irq_domain, bit);
++		generic_handle_irq(irq);
++
++		pending &= ~BIT(bit);
++	}
++}
++
++static void rt3883_pci_irq_unmask(struct irq_data *d)
++{
++	struct rt3883_pci_controller *rpc;
++	u32 t;
++
++	rpc = irq_data_get_irq_chip_data(d);
++
++	t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
++	rt3883_pci_w32(rpc, t | BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
++	/* flush write */
++	rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
++}
++
++static void rt3883_pci_irq_mask(struct irq_data *d)
++{
++	struct rt3883_pci_controller *rpc;
++	u32 t;
++
++	rpc = irq_data_get_irq_chip_data(d);
++
++	t = rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
++	rt3883_pci_w32(rpc, t & ~BIT(d->hwirq), RT3883_PCI_REG_PCIENA);
++	/* flush write */
++	rt3883_pci_r32(rpc, RT3883_PCI_REG_PCIENA);
++}
++
++static struct irq_chip rt3883_pci_irq_chip = {
++	.name		= "RT3883 PCI",
++	.irq_mask	= rt3883_pci_irq_mask,
++	.irq_unmask	= rt3883_pci_irq_unmask,
++	.irq_mask_ack	= rt3883_pci_irq_mask,
++};
++
++static int rt3883_pci_irq_map(struct irq_domain *d, unsigned int irq,
++			      irq_hw_number_t hw)
++{
++	irq_set_chip_and_handler(irq, &rt3883_pci_irq_chip, handle_level_irq);
++	irq_set_chip_data(irq, d->host_data);
++
++	return 0;
++}
++
++static const struct irq_domain_ops rt3883_pci_irq_domain_ops = {
++	.map = rt3883_pci_irq_map,
++	.xlate = irq_domain_xlate_onecell,
++};
++
++static int rt3883_pci_irq_init(struct device *dev,
++			       struct rt3883_pci_controller *rpc)
++{
++	struct device_node *np = dev->of_node;
++	struct device_node *intc_np;
++	int irq;
++	int err;
++
++	intc_np = of_get_child_by_name(np, "interrupt-controller");
++	if (!intc_np) {
++		dev_err(dev, "no %s child node found", "interrupt-controller");
++		return -ENODEV;
++	}
++
++	irq = irq_of_parse_and_map(intc_np, 0);
++	if (irq == 0) {
++		dev_err(dev, "%s has no IRQ", of_node_full_name(intc_np));
++		err = -EINVAL;
++		goto err_put_intc;
++	}
++
++	/* disable all interrupts */
++	rt3883_pci_w32(rpc, 0, RT3883_PCI_REG_PCIENA);
++
++	rpc->irq_domain =
++		irq_domain_add_linear(intc_np, RT3883_PCI_IRQ_COUNT,
++				      &rt3883_pci_irq_domain_ops,
++				      rpc);
++	if (!rpc->irq_domain) {
++		dev_err(dev, "unable to add IRQ domain\n");
++		err = -ENODEV;
++		goto err_put_intc;
++	}
++
++	irq_set_handler_data(irq, rpc);
++	irq_set_chained_handler(irq, rt3883_pci_irq_handler);
++
++	return 0;
++
++err_put_intc:
++	of_node_put(intc_np);
++	return err;
++}
++
++static int rt3883_pci_config_read(struct pci_bus *bus, unsigned int devfn,
++				  int where, int size, u32 *val)
++{
++	struct rt3883_pci_controller *rpc;
++	unsigned long flags;
++	u32 address;
++	u32 data;
++
++	rpc = pci_bus_to_rt3883_controller(bus);
++
++	if (!rpc->pcie_ready && bus->number == 1)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
++					 PCI_FUNC(devfn), where);
++
++	spin_lock_irqsave(&rpc->lock, flags);
++	rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
++	data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
++	spin_unlock_irqrestore(&rpc->lock, flags);
++
++	switch (size) {
++	case 1:
++		*val = (data >> ((where & 3) << 3)) & 0xff;
++		break;
++	case 2:
++		*val = (data >> ((where & 3) << 3)) & 0xffff;
++		break;
++	case 4:
++		*val = data;
++		break;
++	}
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int rt3883_pci_config_write(struct pci_bus *bus, unsigned int devfn,
++				   int where, int size, u32 val)
++{
++	struct rt3883_pci_controller *rpc;
++	unsigned long flags;
++	u32 address;
++	u32 data;
++
++	rpc = pci_bus_to_rt3883_controller(bus);
++
++	if (!rpc->pcie_ready && bus->number == 1)
++		return PCIBIOS_DEVICE_NOT_FOUND;
++
++	address = rt3883_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
++					 PCI_FUNC(devfn), where);
++
++	spin_lock_irqsave(&rpc->lock, flags);
++	rt3883_pci_w32(rpc, address, RT3883_PCI_REG_CFGADDR);
++	data = rt3883_pci_r32(rpc, RT3883_PCI_REG_CFGDATA);
++
++	switch (size) {
++	case 1:
++		data = (data & ~(0xff << ((where & 3) << 3))) |
++		       (val << ((where & 3) << 3));
++		break;
++	case 2:
++		data = (data & ~(0xffff << ((where & 3) << 3))) |
++		       (val << ((where & 3) << 3));
++		break;
++	case 4:
++		data = val;
++		break;
++	}
++
++	rt3883_pci_w32(rpc, data, RT3883_PCI_REG_CFGDATA);
++	spin_unlock_irqrestore(&rpc->lock, flags);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static struct pci_ops rt3883_pci_ops = {
++	.read	= rt3883_pci_config_read,
++	.write	= rt3883_pci_config_write,
++};
++
++static void rt3883_pci_preinit(struct rt3883_pci_controller *rpc, unsigned mode)
++{
++	u32 syscfg1;
++	u32 rstctrl;
++	u32 clkcfg1;
++	u32 t;
++
++	rstctrl = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
++	syscfg1 = rt_sysc_r32(RT3883_SYSC_REG_SYSCFG1);
++	clkcfg1 = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
++
++	if (mode & RT3883_PCI_MODE_PCIE) {
++		rstctrl |= RT3883_RSTCTRL_PCIE;
++		rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
++
++		/* setup PCI PAD drive mode */
++		syscfg1 &= ~(0x30);
++		syscfg1 |= (2 << 4);
++		rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
++
++		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
++		t &= ~BIT(31);
++		rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
++
++		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
++		t &= 0x80ffffff;
++		rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
++
++		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN1);
++		t |= 0xa << 24;
++		rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN1);
++
++		t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
++		t |= BIT(31);
++		rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
++
++		msleep(50);
++
++		rstctrl &= ~RT3883_RSTCTRL_PCIE;
++		rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
++	}
++
++	syscfg1 |= (RT3883_SYSCFG1_PCIE_RC_MODE | RT3883_SYSCFG1_PCI_HOST_MODE);
++
++	clkcfg1 &= ~(RT3883_CLKCFG1_PCI_CLK_EN | RT3883_CLKCFG1_PCIE_CLK_EN);
++
++	if (mode & RT3883_PCI_MODE_PCI) {
++		clkcfg1 |= RT3883_CLKCFG1_PCI_CLK_EN;
++		rstctrl &= ~RT3883_RSTCTRL_PCI;
++	}
++
++	if (mode & RT3883_PCI_MODE_PCIE) {
++		clkcfg1 |= RT3883_CLKCFG1_PCIE_CLK_EN;
++		rstctrl &= ~RT3883_RSTCTRL_PCIE;
++	}
++
++	rt_sysc_w32(syscfg1, RT3883_SYSC_REG_SYSCFG1);
++	rt_sysc_w32(rstctrl, RT3883_SYSC_REG_RSTCTRL);
++	rt_sysc_w32(clkcfg1, RT3883_SYSC_REG_CLKCFG1);
++
++	msleep(500);
++
++	/*
++	 * setup the device number of the P2P bridge
++	 * and de-assert the reset line
++	 */
++	t = (RT3883_P2P_BR_DEVNUM << RT3883_PCICFG_P2P_BR_DEVNUM_S);
++	rt3883_pci_w32(rpc, t, RT3883_PCI_REG_PCICFG);
++
++	/* flush write */
++	rt3883_pci_r32(rpc, RT3883_PCI_REG_PCICFG);
++	msleep(500);
++
++	if (mode & RT3883_PCI_MODE_PCIE) {
++		msleep(500);
++
++		t = rt3883_pci_r32(rpc, RT3883_PCI_REG_STATUS(1));
++
++		rpc->pcie_ready = t & BIT(0);
++
++		if (!rpc->pcie_ready) {
++			/* reset the PCIe block */
++			t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
++			t |= RT3883_RSTCTRL_PCIE;
++			rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
++			t &= ~RT3883_RSTCTRL_PCIE;
++			rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
++
++			/* turn off PCIe clock */
++			t = rt_sysc_r32(RT3883_SYSC_REG_CLKCFG1);
++			t &= ~RT3883_CLKCFG1_PCIE_CLK_EN;
++			rt_sysc_w32(t, RT3883_SYSC_REG_CLKCFG1);
++
++			t = rt_sysc_r32(RT3883_SYSC_REG_PCIE_CLK_GEN0);
++			t &= ~0xf000c080;
++			rt_sysc_w32(t, RT3883_SYSC_REG_PCIE_CLK_GEN0);
++		}
++	}
++
++	/* enable PCI arbiter */
++	rt3883_pci_w32(rpc, 0x79, RT3883_PCI_REG_ARBCTL);
++}
++
++static inline void
++rt3883_dump_pci_config(struct rt3883_pci_controller *rpc,
++		       int bus, int slot)
++{
++	int i;
++
++	for (i = 0; i < 16; i++) {
++		u32 val;
++
++		val = rt3883_pci_read_cfg32(rpc, bus, slot, 0, i << 2);
++		pr_info("pci %02x:%02x.0 0x%02x = %08x\n",
++		        bus, slot, i << 2, val);
++	}
++}
++
++static int rt3883_pci_probe(struct platform_device *pdev)
++{
++	struct rt3883_pci_controller *rpc;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct resource *res;
++	struct device_node *child;
++	u32 val;
++	int err;
++	int mode;
++
++	rpc = devm_kzalloc(dev, sizeof(*rpc), GFP_KERNEL);
++	if (!rpc)
++		return -ENOMEM;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res)
++		return -EINVAL;
++
++	rpc->base = devm_ioremap_resource(dev, res);
++	if (IS_ERR(rpc->base))
++		return PTR_ERR(rpc->base);
++
++	rpc->pci_controller.of_node = of_get_child_by_name(np, "host-bridge");
++	if (!rpc->pci_controller.of_node) {
++		dev_err(dev, "no %s child node found", "host-bridge");
++		return -ENODEV;
++	}
++
++	mode = RT3883_PCI_MODE_NONE;
++	for_each_child_of_node(rpc->pci_controller.of_node, child) {
++		u32 slot;
++
++		if (!of_device_is_available(child))
++			continue;
++
++		if (of_property_read_u32(child, "ralink,pci-slot",
++					 &slot)) {
++			dev_err(dev, "no '%s' property found for %s\n",
++				"ralink,pci-slot",
++				of_node_full_name(child));
++			continue;
++		}
++
++		switch (slot) {
++		case 1:
++			mode |= RT3883_PCI_MODE_PCIE;
++			break;
++
++		case 17:
++		case 18:
++			mode |= RT3883_PCI_MODE_PCI;
++			break;
++		}
++	}
++
++	if (mode == RT3883_PCI_MODE_NONE) {
++		dev_err(dev, "unable to determine PCI mode\n");
++		err = -EINVAL;
++		goto err_put_hb_node;
++	}
++
++	dev_info(dev, "mode:%s%s\n",
++		 (mode & RT3883_PCI_MODE_PCI) ? " PCI" : "",
++		 (mode & RT3883_PCI_MODE_PCIE) ? " PCIe" : "");
++
++	rt3883_pci_preinit(rpc, mode);
++
++	rpc->pci_controller.pci_ops = &rt3883_pci_ops;
++	rpc->pci_controller.io_resource = &rpc->io_res;
++	rpc->pci_controller.mem_resource = &rpc->mem_res;
++
++	/* Load PCI I/O and memory resources from DT */
++	pci_load_of_ranges(&rpc->pci_controller,
++			   rpc->pci_controller.of_node);
++
++	rt3883_pci_w32(rpc, rpc->mem_res.start, RT3883_PCI_REG_MEMBASE);
++	rt3883_pci_w32(rpc, rpc->io_res.start, RT3883_PCI_REG_IOBASE);
++
++	ioport_resource.start = rpc->io_res.start;
++	ioport_resource.end = rpc->io_res.end;
++
++	/* PCI */
++	rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(0));
++	rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(0));
++	rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(0));
++	rt3883_pci_w32(rpc, 0x00800001, RT3883_PCI_REG_CLASS(0));
++	rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(0));
++
++	/* PCIe */
++	rt3883_pci_w32(rpc, 0x03ff0000, RT3883_PCI_REG_BAR0SETUP(1));
++	rt3883_pci_w32(rpc, RT3883_MEMORY_BASE, RT3883_PCI_REG_IMBASEBAR0(1));
++	rt3883_pci_w32(rpc, 0x08021814, RT3883_PCI_REG_ID(1));
++	rt3883_pci_w32(rpc, 0x06040001, RT3883_PCI_REG_CLASS(1));
++	rt3883_pci_w32(rpc, 0x28801814, RT3883_PCI_REG_SUBID(1));
++
++	err = rt3883_pci_irq_init(dev, rpc);
++	if (err)
++		goto err_put_hb_node;
++
++	/* PCIe */
++	val = rt3883_pci_read_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND);
++	val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
++	rt3883_pci_write_cfg32(rpc, 0, 0x01, 0, PCI_COMMAND, val);
++
++	/* PCI */
++	val = rt3883_pci_read_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND);
++	val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
++	rt3883_pci_write_cfg32(rpc, 0, 0x00, 0, PCI_COMMAND, val);
++
++	if (mode == RT3883_PCI_MODE_PCIE) {
++		rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(0));
++		rt3883_pci_w32(rpc, 0x03ff0001, RT3883_PCI_REG_BAR0SETUP(1));
++
++		rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
++				       PCI_BASE_ADDRESS_0,
++				       RT3883_MEMORY_BASE);
++		/* flush write */
++		rt3883_pci_read_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
++				      PCI_BASE_ADDRESS_0);
++	} else {
++		rt3883_pci_write_cfg32(rpc, 0, RT3883_P2P_BR_DEVNUM, 0,
++				       PCI_IO_BASE, 0x00000101);
++	}
++
++	register_pci_controller(&rpc->pci_controller);
++
++	return 0;
++
++err_put_hb_node:
++	of_node_put(rpc->pci_controller.of_node);
++	return err;
++}
++
++int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	struct rt3883_pci_controller *rpc;
++	struct of_irq dev_irq;
++	int err;
++	int irq;
++
++	rpc = pci_bus_to_rt3883_controller(dev->bus);
++	err = of_irq_map_pci(dev, &dev_irq);
++	if (err) {
++		pr_err("pci %s: unable to get irq map, err=%d\n",
++		       pci_name((struct pci_dev *) dev), err);
++		return 0;
++	}
++
++	irq = irq_create_of_mapping(dev_irq.controller,
++				    dev_irq.specifier,
++				    dev_irq.size);
++
++	if (irq == 0)
++		pr_crit("pci %s: no irq found for pin %u\n",
++			pci_name((struct pci_dev *) dev), pin);
++	else
++		pr_info("pci %s: using irq %d for pin %u\n",
++			pci_name((struct pci_dev *) dev), irq, pin);
++
++	return irq;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
++
++static const struct of_device_id rt3883_pci_ids[] = {
++	{ .compatible = "ralink,rt3883-pci" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt3883_pci_ids);
++
++static struct platform_driver rt3883_pci_driver = {
++	.probe = rt3883_pci_probe,
++	.driver = {
++		.name = "rt3883-pci",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(rt3883_pci_ids),
++	},
++};
++
++static int __init rt3883_pci_init(void)
++{
++	return platform_driver_register(&rt3883_pci_driver);
++}
++
++postcore_initcall(rt3883_pci_init);
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index cd13da8..592e5f9 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -20,6 +20,7 @@ choice
+ 		bool "RT3883"
+ 		select USB_ARCH_HAS_OHCI
+ 		select USB_ARCH_HAS_EHCI
++		select HW_HAS_PCI
+ 
+ 	config SOC_MT7620
+ 		bool "MT7620"
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0013-PCI-MIPS-adds-mt7620a-pcie-driver.patch b/target/linux/ramips/patches-3.10/0013-PCI-MIPS-adds-mt7620a-pcie-driver.patch
new file mode 100644
index 0000000..1da472c
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0013-PCI-MIPS-adds-mt7620a-pcie-driver.patch
@@ -0,0 +1,409 @@
+From ded577553b06a85c12a89b8fbcfa2b51f30bc037 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 18 May 2013 22:06:15 +0200
+Subject: [PATCH 13/33] PCI: MIPS: adds mt7620a pcie driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/pci/Makefile      |    1 +
+ arch/mips/pci/pci-mt7620a.c |  363 +++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/Kconfig    |    1 +
+ 3 files changed, 365 insertions(+)
+ create mode 100644 arch/mips/pci/pci-mt7620a.c
+
+diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
+index 3cbfd9b..025d3a7 100644
+--- a/arch/mips/pci/Makefile
++++ b/arch/mips/pci/Makefile
+@@ -43,6 +43,7 @@ obj-$(CONFIG_LANTIQ)		+= fixup-lantiq.o
+ obj-$(CONFIG_PCI_LANTIQ)	+= pci-lantiq.o ops-lantiq.o
+ obj-$(CONFIG_SOC_RT2880)	+= pci-rt2880.o
+ obj-$(CONFIG_SOC_RT3883)	+= pci-rt3883.o
++obj-$(CONFIG_SOC_MT7620)	+= pci-mt7620a.o
+ obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
+ obj-$(CONFIG_TANBAC_TB0226)	+= fixup-tb0226.o
+ obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
+diff --git a/arch/mips/pci/pci-mt7620a.c b/arch/mips/pci/pci-mt7620a.c
+new file mode 100644
+index 0000000..271763c
+--- /dev/null
++++ b/arch/mips/pci/pci-mt7620a.c
+@@ -0,0 +1,363 @@
++/*
++ *  Ralink MT7620A SoC PCI support
++ *
++ *  Copyright (C) 2007-2013 Bruce Chang
++ *  Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#include <linux/types.h>
++#include <linux/pci.h>
++#include <linux/io.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/interrupt.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_pci.h>
++#include <linux/reset.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define RALINK_PCI_MM_MAP_BASE		0x20000000
++#define RALINK_PCI_IO_MAP_BASE		0x10160000
++
++#define RALINK_INT_PCIE0		4
++#define RALINK_SYSTEM_CONTROL_BASE	0xb0000000
++#define RALINK_SYSCFG1			0x14
++#define RALINK_CLKCFG1			0x30
++#define RALINK_GPIOMODE			0x60
++#define RALINK_PCIE_CLK_GEN		0x7c
++#define RALINK_PCIE_CLK_GEN1		0x80
++#define PCIEPHY0_CFG			0x90
++#define PPLL_CFG1			0x9c
++#define PPLL_DRV			0xa0
++#define RALINK_PCI_HOST_MODE_EN		(1<<7)
++#define RALINK_PCIE_RC_MODE_EN		(1<<8)
++#define RALINK_PCIE_RST			(1<<23)
++#define RALINK_PCI_RST			(1<<24)
++#define RALINK_PCI_CLK_EN		(1<<19)
++#define RALINK_PCIE_CLK_EN		(1<<21)
++#define PCI_SLOTx2			(1<<11)
++#define PCI_SLOTx1			(2<<11)
++#define PDRV_SW_SET			(1<<31)
++#define LC_CKDRVPD_			(1<<19)
++
++#define RALINK_PCI_CONFIG_ADDR		0x20
++#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
++#define MEMORY_BASE			0x0
++#define RALINK_PCIE0_RST		(1<<26)
++#define RALINK_PCI_BASE			0xB0140000
++#define RALINK_PCI_MEMBASE		0x28
++#define RALINK_PCI_IOBASE		0x2C
++
++#define RT6855_PCIE0_OFFSET		0x2000
++
++#define RALINK_PCI_PCICFG_ADDR		0x00
++#define RALINK_PCI0_BAR0SETUP_ADDR	0x10
++#define RALINK_PCI0_IMBASEBAR0_ADDR	0x18
++#define RALINK_PCI0_ID			0x30
++#define RALINK_PCI0_CLASS		0x34
++#define RALINK_PCI0_SUBID		0x38
++#define RALINK_PCI0_STATUS		0x50
++#define RALINK_PCI_PCIMSK_ADDR		0x0C
++
++#define RALINK_PCIE0_CLK_EN		(1 << 26)
++
++#define BUSY				0x80000000
++#define WAITRETRY_MAX			10
++#define WRITE_MODE			(1UL << 23)
++#define DATA_SHIFT			0
++#define ADDR_SHIFT			8
++
++
++static void __iomem *bridge_base;
++static void __iomem *pcie_base;
++
++static struct reset_control *rstpcie0;
++
++static inline void bridge_w32(u32 val, unsigned reg)
++{
++	iowrite32(val, bridge_base + reg);
++}
++
++static inline u32 bridge_r32(unsigned reg)
++{
++	return ioread32(bridge_base + reg);
++}
++
++static inline void pcie_w32(u32 val, unsigned reg)
++{
++	iowrite32(val, pcie_base + reg);
++}
++
++static inline u32 pcie_r32(unsigned reg)
++{
++	return ioread32(pcie_base + reg);
++}
++
++static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
++{
++	u32 val = pcie_r32(reg);
++	val &= ~clr;
++	val |= set;
++	pcie_w32(val, reg);
++}
++
++int wait_pciephy_busy(void)
++{
++	unsigned long reg_value = 0x0, retry = 0;
++
++	while (1) {
++		//reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
++		reg_value = pcie_r32(PCIEPHY0_CFG);
++
++		if (reg_value & BUSY)
++			mdelay(100);
++		else
++			break;
++		if (retry++ > WAITRETRY_MAX){
++			printk("PCIE-PHY retry failed.\n");
++			return -1;
++		}
++	}
++	return 0;
++}
++
++static void pcie_phy(unsigned long addr, unsigned long val)
++{
++	wait_pciephy_busy();
++	pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT), PCIEPHY0_CFG);
++	mdelay(1);
++	wait_pciephy_busy();
++}
++
++static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
++{
++	unsigned int slot = PCI_SLOT(devfn);
++	u8 func = PCI_FUNC(devfn);
++	u32 address;
++	u32 data;
++
++	address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
++	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
++
++	switch (size) {
++	case 1:
++		*val = (data >> ((where & 3) << 3)) & 0xff;
++		break;
++	case 2:
++		*val = (data >> ((where & 3) << 3)) & 0xffff;
++		break;
++	case 4:
++		*val = data;
++		break;
++	}
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
++{
++	unsigned int slot = PCI_SLOT(devfn);
++	u8 func = PCI_FUNC(devfn);
++	u32 address;
++	u32 data;
++
++	address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
++	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
++
++	switch (size) {
++	case 1:
++		data = (data & ~(0xff << ((where & 3) << 3))) |
++			(val << ((where & 3) << 3));
++		break;
++	case 2:
++		data = (data & ~(0xffff << ((where & 3) << 3))) |
++			(val << ((where & 3) << 3));
++		break;
++	case 4:
++		data = val;
++		break;
++	}
++
++	bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
++
++	return PCIBIOS_SUCCESSFUL;
++}
++
++struct pci_ops mt7620a_pci_ops= {
++	.read	= pci_config_read,
++	.write	= pci_config_write,
++};
++
++static struct resource mt7620a_res_pci_mem1 = {
++	.name	= "pci memory",
++	.start	= RALINK_PCI_MM_MAP_BASE,
++	.end	= (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
++	.flags	= IORESOURCE_MEM,
++};
++static struct resource mt7620a_res_pci_io1 = {
++	.name	= "pci io",
++	.start	= RALINK_PCI_IO_MAP_BASE,
++	.end	= (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
++	.flags	= IORESOURCE_IO,
++};
++
++struct pci_controller mt7620a_controller = {
++	.pci_ops	= &mt7620a_pci_ops,
++	.mem_resource	= &mt7620a_res_pci_mem1,
++	.io_resource	= &mt7620a_res_pci_io1,
++	.mem_offset	= 0x00000000UL,
++	.io_offset	= 0x00000000UL,
++	.io_map_base	= 0xa0000000,
++};
++
++static int mt7620a_pci_probe(struct platform_device *pdev)
++{
++	struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++
++	rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
++	if (IS_ERR(rstpcie0))
++		return PTR_ERR(rstpcie0);
++
++	bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
++        if (!bridge_base)
++		return -ENOMEM;
++
++	pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
++        if (!pcie_base)
++		return -ENOMEM;
++
++	iomem_resource.start = 0;
++	iomem_resource.end= ~0;
++	ioport_resource.start= 0;
++	ioport_resource.end = ~0;
++
++	/* PCIE: bypass PCIe DLL */
++	pcie_phy(0x0, 0x80);
++	pcie_phy(0x1, 0x04);
++	/* PCIE: Elastic buffer control */
++	pcie_phy(0x68, 0xB4);
++
++	reset_control_assert(rstpcie0);
++	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
++	rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
++	rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
++
++	reset_control_deassert(rstpcie0);
++	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
++
++	mdelay(100);
++
++	if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
++		printk("MT7620 PPLL unlock\n");
++		reset_control_assert(rstpcie0);
++		rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
++		return 0;
++	}
++	rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
++
++	mdelay(100);
++	reset_control_assert(rstpcie0);
++	rt_sysc_m32(0x30, 2 << 4, RALINK_SYSCFG1);
++
++	rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
++	rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
++
++	mdelay(50);
++	reset_control_deassert(rstpcie0);
++	pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
++	mdelay(100);
++
++	if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
++		reset_control_assert(rstpcie0);
++		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
++		rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
++		printk("PCIE0 no card, disable it(RST&CLK)\n");
++	}
++
++	bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
++	bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
++
++	pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
++	pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
++	pcie_w32(0x08021814, RALINK_PCI0_ID);
++	pcie_w32(0x06040001, RALINK_PCI0_CLASS);
++	pcie_w32(0x28801814, RALINK_PCI0_SUBID);
++	pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
++
++	register_pci_controller(&mt7620a_controller);
++
++	return 0;
++}
++
++int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
++{
++	const struct resource *res;
++	u16 cmd;
++	u32 val;
++	int i, irq = 0;
++
++	if ((dev->bus->number == 0) && (slot == 0)) {
++		pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
++		pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, MEMORY_BASE);
++		pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
++	} else if ((dev->bus->number == 1) && (slot == 0x0)) {
++		irq = RALINK_INT_PCIE0;
++	} else {
++		printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
++		return 0;
++	}
++
++	for (i = 0; i < 6; i++) {
++		res = &dev->resource[i];
++	}
++
++	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
++	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
++	pci_read_config_word(dev, PCI_COMMAND, &cmd);
++
++	// FIXME
++	cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
++	pci_write_config_word(dev, PCI_COMMAND, cmd);
++	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
++	//pci_write_config_byte(dev, PCI_INTERRUPT_PIN, dev->irq);
++
++	return irq;
++}
++
++int pcibios_plat_dev_init(struct pci_dev *dev)
++{
++	return 0;
++}
++
++static const struct of_device_id mt7620a_pci_ids[] = {
++	{ .compatible = "ralink,mt7620a-pci" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
++
++static struct platform_driver mt7620a_pci_driver = {
++	.probe = mt7620a_pci_probe,
++	.driver = {
++		.name = "mt7620a-pci",
++		.owner = THIS_MODULE,
++		.of_match_table = of_match_ptr(mt7620a_pci_ids),
++	},
++};
++
++static int __init mt7620a_pci_init(void)
++{
++	return platform_driver_register(&mt7620a_pci_driver);
++}
++
++arch_initcall(mt7620a_pci_init);
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 592e5f9..992e365 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -24,6 +24,7 @@ choice
+ 
+ 	config SOC_MT7620
+ 		bool "MT7620"
++		select HW_HAS_PCI
+ 
+ endchoice
+ 
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0014-NET-multi-phy-support.patch b/target/linux/ramips/patches-3.10/0014-NET-multi-phy-support.patch
new file mode 100644
index 0000000..94f63aa
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0014-NET-multi-phy-support.patch
@@ -0,0 +1,61 @@
+From 7407b7d178e783074861a73da858b099f870270d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sat, 11 May 2013 23:40:19 +0200
+Subject: [PATCH 14/33] NET: multi phy support
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/net/phy/phy.c |    9 ++++++---
+ include/linux/phy.h   |    2 +-
+ 2 files changed, 7 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
+index 38f0b31..ad64a75 100644
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -773,7 +773,8 @@ void phy_state_machine(struct work_struct *work)
+ 			 * negotiation for now */
+ 			if (!phydev->link) {
+ 				phydev->state = PHY_NOLINK;
+-				netif_carrier_off(phydev->attached_dev);
++				if (!phydev->no_auto_carrier_off)
++					netif_carrier_off(phydev->attached_dev);
+ 				phydev->adjust_link(phydev->attached_dev);
+ 				break;
+ 			}
+@@ -843,7 +844,8 @@ void phy_state_machine(struct work_struct *work)
+ 				netif_carrier_on(phydev->attached_dev);
+ 			} else {
+ 				phydev->state = PHY_NOLINK;
+-				netif_carrier_off(phydev->attached_dev);
++				if (!phydev->no_auto_carrier_off)
++					netif_carrier_off(phydev->attached_dev);
+ 			}
+ 
+ 			phydev->adjust_link(phydev->attached_dev);
+@@ -855,7 +857,8 @@ void phy_state_machine(struct work_struct *work)
+ 		case PHY_HALTED:
+ 			if (phydev->link) {
+ 				phydev->link = 0;
+-				netif_carrier_off(phydev->attached_dev);
++				if (!phydev->no_auto_carrier_off)
++					netif_carrier_off(phydev->attached_dev);
+ 				phydev->adjust_link(phydev->attached_dev);
+ 			}
+ 			break;
+diff --git a/include/linux/phy.h b/include/linux/phy.h
+index 9e11039..9a8ca78 100644
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -298,7 +298,7 @@ struct phy_device {
+ 
+ 	struct phy_c45_device_ids c45_ids;
+ 	bool is_c45;
+-
++	bool no_auto_carrier_off;
+ 	enum phy_state state;
+ 
+ 	u32 dev_flags;
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0015-NET-add-of_get_mac_address_mtd.patch b/target/linux/ramips/patches-3.10/0015-NET-add-of_get_mac_address_mtd.patch
new file mode 100644
index 0000000..1bc2977
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0015-NET-add-of_get_mac_address_mtd.patch
@@ -0,0 +1,83 @@
+From 2a41724b2d0af9b4444572c4302570a3af377715 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:26:15 +0200
+Subject: [PATCH 15/33] NET: add of_get_mac_address_mtd()
+
+Many embedded devices have information such as mac addresses stored inside mtd
+devices. This patch allows us to add a property inside a node describing a
+network interface. The new property points at a mtd partition with an offset
+where the mac address can be found.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/of/of_net.c    |   37 +++++++++++++++++++++++++++++++++++++
+ include/linux/of_net.h |    1 +
+ 2 files changed, 38 insertions(+)
+
+diff --git a/drivers/of/of_net.c b/drivers/of/of_net.c
+index ffab033..15f4a71 100644
+--- a/drivers/of/of_net.c
++++ b/drivers/of/of_net.c
+@@ -10,6 +10,7 @@
+ #include <linux/of_net.h>
+ #include <linux/phy.h>
+ #include <linux/export.h>
++#include <linux/mtd/mtd.h>
+ 
+ /**
+  * It maps 'enum phy_interface_t' found in include/linux/phy.h
+@@ -92,3 +93,39 @@ const void *of_get_mac_address(struct device_node *np)
+ 	return NULL;
+ }
+ EXPORT_SYMBOL(of_get_mac_address);
++
++int of_get_mac_address_mtd(struct device_node *np, void *mac)
++{
++	struct device_node *mtd_np = NULL;
++	size_t retlen;
++	int size, ret;
++	struct mtd_info *mtd;
++	const char *part;
++	const __be32 *list;
++	phandle phandle;
++
++	list = of_get_property(np, "mtd-mac-address", &size);
++	if (!list || (size != (2 * sizeof(*list))))
++		return -ENOENT;
++
++	phandle = be32_to_cpup(list++);
++	if (phandle)
++		mtd_np = of_find_node_by_phandle(phandle);
++
++	if (!mtd_np)
++		return -ENOENT;
++
++	part = of_get_property(mtd_np, "label", NULL);
++	if (!part)
++		part = mtd_np->name;
++
++	mtd = get_mtd_device_nm(part);
++	if (IS_ERR(mtd))
++		return PTR_ERR(mtd);
++
++	ret = mtd_read(mtd, be32_to_cpup(list), 6, &retlen, (u_char *) mac);
++	put_mtd_device(mtd);
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(of_get_mac_address_mtd);
+diff --git a/include/linux/of_net.h b/include/linux/of_net.h
+index 61bf53b..6e6b4a9 100644
+--- a/include/linux/of_net.h
++++ b/include/linux/of_net.h
+@@ -11,6 +11,7 @@
+ #include <linux/of.h>
+ extern const int of_get_phy_mode(struct device_node *np);
+ extern const void *of_get_mac_address(struct device_node *np);
++extern int of_get_mac_address_mtd(struct device_node *np, void *mac);
+ #else
+ static inline const int of_get_phy_mode(struct device_node *np)
+ {
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0016-NET-MIPS-add-ralink-SoC-ethernet-driver.patch b/target/linux/ramips/patches-3.10/0016-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
new file mode 100644
index 0000000..fbd45b8
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0016-NET-MIPS-add-ralink-SoC-ethernet-driver.patch
@@ -0,0 +1,4792 @@
+From ad11aedcc16574c0b3d3f5e40c67227d1846b94e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 22 Apr 2013 23:20:03 +0200
+Subject: [PATCH 16/33] NET: MIPS: add ralink SoC ethernet driver
+
+Add support for Ralink FE and ESW.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../include/asm/mach-ralink/rt305x_esw_platform.h  |   27 +
+ arch/mips/ralink/rt305x.c                          |    1 +
+ drivers/net/ethernet/Kconfig                       |    1 +
+ drivers/net/ethernet/Makefile                      |    1 +
+ drivers/net/ethernet/ralink/Kconfig                |   31 +
+ drivers/net/ethernet/ralink/Makefile               |   18 +
+ drivers/net/ethernet/ralink/esw_rt3052.c           | 1463 ++++++++++++++++++++
+ drivers/net/ethernet/ralink/esw_rt3052.h           |   32 +
+ drivers/net/ethernet/ralink/gsw_mt7620a.c          | 1027 ++++++++++++++
+ drivers/net/ethernet/ralink/gsw_mt7620a.h          |   29 +
+ drivers/net/ethernet/ralink/mdio.c                 |  245 ++++
+ drivers/net/ethernet/ralink/mdio.h                 |   29 +
+ drivers/net/ethernet/ralink/mdio_rt2880.c          |  232 ++++
+ drivers/net/ethernet/ralink/mdio_rt2880.h          |   26 +
+ drivers/net/ethernet/ralink/ralink_soc_eth.c       |  735 ++++++++++
+ drivers/net/ethernet/ralink/ralink_soc_eth.h       |  374 +++++
+ drivers/net/ethernet/ralink/soc_mt7620.c           |  111 ++
+ drivers/net/ethernet/ralink/soc_rt2880.c           |   51 +
+ drivers/net/ethernet/ralink/soc_rt305x.c           |  113 ++
+ drivers/net/ethernet/ralink/soc_rt3883.c           |   60 +
+ 20 files changed, 4606 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
+ create mode 100644 drivers/net/ethernet/ralink/Kconfig
+ create mode 100644 drivers/net/ethernet/ralink/Makefile
+ create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.c
+ create mode 100644 drivers/net/ethernet/ralink/esw_rt3052.h
+ create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.c
+ create mode 100644 drivers/net/ethernet/ralink/gsw_mt7620a.h
+ create mode 100644 drivers/net/ethernet/ralink/mdio.c
+ create mode 100644 drivers/net/ethernet/ralink/mdio.h
+ create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.c
+ create mode 100644 drivers/net/ethernet/ralink/mdio_rt2880.h
+ create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.c
+ create mode 100644 drivers/net/ethernet/ralink/ralink_soc_eth.h
+ create mode 100644 drivers/net/ethernet/ralink/soc_mt7620.c
+ create mode 100644 drivers/net/ethernet/ralink/soc_rt2880.c
+ create mode 100644 drivers/net/ethernet/ralink/soc_rt305x.c
+ create mode 100644 drivers/net/ethernet/ralink/soc_rt3883.c
+
+diff --git a/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
+new file mode 100644
+index 0000000..2098c5c
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/rt305x_esw_platform.h
+@@ -0,0 +1,27 @@
++/*
++ *  Ralink RT305x SoC platform device registration
++ *
++ *  Copyright (C) 2010 Gabor Juhos <juhosg@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ */
++
++#ifndef _RT305X_ESW_PLATFORM_H
++#define _RT305X_ESW_PLATFORM_H
++
++enum {
++	RT305X_ESW_VLAN_CONFIG_NONE = 0,
++	RT305X_ESW_VLAN_CONFIG_LLLLW,
++	RT305X_ESW_VLAN_CONFIG_WLLLL,
++};
++
++struct rt305x_esw_platform_data
++{
++	u8 vlan_config;
++	u32 reg_initval_fct2;
++	u32 reg_initval_fpa2;
++};
++
++#endif /* _RT305X_ESW_PLATFORM_H */
+diff --git a/arch/mips/ralink/rt305x.c b/arch/mips/ralink/rt305x.c
+index ca7ee3a..1a6b458 100644
+--- a/arch/mips/ralink/rt305x.c
++++ b/arch/mips/ralink/rt305x.c
+@@ -221,6 +221,7 @@ void __init ralink_clk_init(void)
+ 	}
+ 
+ 	ralink_clk_add("cpu", cpu_rate);
++	ralink_clk_add("sys", sys_rate);
+ 	ralink_clk_add("10000b00.spi", sys_rate);
+ 	ralink_clk_add("10000100.timer", wdt_rate);
+ 	ralink_clk_add("10000120.watchdog", wdt_rate);
+diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
+index ed956e0..0b3caa1 100644
+--- a/drivers/net/ethernet/Kconfig
++++ b/drivers/net/ethernet/Kconfig
+@@ -135,6 +135,7 @@ config ETHOC
+ source "drivers/net/ethernet/packetengines/Kconfig"
+ source "drivers/net/ethernet/pasemi/Kconfig"
+ source "drivers/net/ethernet/qlogic/Kconfig"
++source "drivers/net/ethernet/ralink/Kconfig"
+ source "drivers/net/ethernet/realtek/Kconfig"
+ source "drivers/net/ethernet/renesas/Kconfig"
+ source "drivers/net/ethernet/rdc/Kconfig"
+diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
+index 8268d85..508c494 100644
+--- a/drivers/net/ethernet/Makefile
++++ b/drivers/net/ethernet/Makefile
+@@ -53,6 +53,7 @@ obj-$(CONFIG_ETHOC) += ethoc.o
+ obj-$(CONFIG_NET_PACKET_ENGINE) += packetengines/
+ obj-$(CONFIG_NET_VENDOR_PASEMI) += pasemi/
+ obj-$(CONFIG_NET_VENDOR_QLOGIC) += qlogic/
++obj-$(CONFIG_NET_RALINK) += ralink/
+ obj-$(CONFIG_NET_VENDOR_REALTEK) += realtek/
+ obj-$(CONFIG_SH_ETH) += renesas/
+ obj-$(CONFIG_NET_VENDOR_RDC) += rdc/
+diff --git a/drivers/net/ethernet/ralink/Kconfig b/drivers/net/ethernet/ralink/Kconfig
+new file mode 100644
+index 0000000..ca2c9ad
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/Kconfig
+@@ -0,0 +1,31 @@
++config NET_RALINK
++	tristate "Ralink RT288X/RT3X5X/RT3662/RT3883/MT7620 ethernet driver"
++	depends on RALINK
++	help
++	  This driver supports the ethernet mac inside the ralink wisocs
++
++if NET_RALINK
++
++config NET_RALINK_MDIO
++	def_bool NET_RALINK
++	depends on (SOC_RT288X || SOC_RT3883 || SOC_MT7620)
++	select PHYLIB
++
++config NET_RALINK_MDIO_RT2880
++	def_bool NET_RALINK
++	depends on (SOC_RT288X || SOC_RT3883)
++	select NET_RALINK_MDIO
++
++config NET_RALINK_ESW_RT3052
++	def_bool NET_RALINK
++	depends on SOC_RT305X
++	select PHYLIB
++	select SWCONFIG
++
++config NET_RALINK_GSW_MT7620
++	def_bool NET_RALINK
++	depends on SOC_MT7620
++	select NET_RALINK_MDIO
++	select PHYLIB
++	select SWCONFIG
++endif
+diff --git a/drivers/net/ethernet/ralink/Makefile b/drivers/net/ethernet/ralink/Makefile
+new file mode 100644
+index 0000000..a38fa21
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/Makefile
+@@ -0,0 +1,18 @@
++#
++# Makefile for the Ralink SoCs built-in ethernet macs
++#
++
++ralink-eth-y					+= ralink_soc_eth.o
++
++ralink-eth-$(CONFIG_NET_RALINK_MDIO)		+= mdio.o
++ralink-eth-$(CONFIG_NET_RALINK_MDIO_RT2880)	+= mdio_rt2880.o
++
++ralink-eth-$(CONFIG_NET_RALINK_ESW_RT3052)	+= esw_rt3052.o
++ralink-eth-$(CONFIG_NET_RALINK_GSW_MT7620)	+= gsw_mt7620a.o
++
++ralink-eth-$(CONFIG_SOC_RT288X)			+= soc_rt2880.o
++ralink-eth-$(CONFIG_SOC_RT305X)			+= soc_rt305x.o
++ralink-eth-$(CONFIG_SOC_RT3883)			+= soc_rt3883.o
++ralink-eth-$(CONFIG_SOC_MT7620)			+= soc_mt7620.o
++
++obj-$(CONFIG_NET_RALINK)			+= ralink-eth.o
+diff --git a/drivers/net/ethernet/ralink/esw_rt3052.c b/drivers/net/ethernet/ralink/esw_rt3052.c
+new file mode 100644
+index 0000000..b937062
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/esw_rt3052.c
+@@ -0,0 +1,1463 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/platform_device.h>
++#include <linux/of_device.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_mdio.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "ralink_soc_eth.h"
++
++#include <linux/ioport.h>
++#include <linux/switch.h>
++#include <linux/mii.h>
++
++#include <ralink_regs.h>
++#include <asm/mach-ralink/rt305x.h>
++#include <asm/mach-ralink/rt305x_esw_platform.h>
++
++/*
++ * HW limitations for this switch:
++ * - No large frame support (PKT_MAX_LEN at most 1536)
++ * - Can't have untagged vlan and tagged vlan on one port at the same time,
++ *   though this might be possible using the undocumented PPE.
++ */
++
++#define RT305X_ESW_REG_ISR		0x00
++#define RT305X_ESW_REG_IMR		0x04
++#define RT305X_ESW_REG_FCT0		0x08
++#define RT305X_ESW_REG_PFC1		0x14
++#define RT305X_ESW_REG_ATS		0x24
++#define RT305X_ESW_REG_ATS0		0x28
++#define RT305X_ESW_REG_ATS1		0x2c
++#define RT305X_ESW_REG_ATS2		0x30
++#define RT305X_ESW_REG_PVIDC(_n)	(0x40 + 4 * (_n))
++#define RT305X_ESW_REG_VLANI(_n)	(0x50 + 4 * (_n))
++#define RT305X_ESW_REG_VMSC(_n)		(0x70 + 4 * (_n))
++#define RT305X_ESW_REG_POA		0x80
++#define RT305X_ESW_REG_FPA		0x84
++#define RT305X_ESW_REG_SOCPC		0x8c
++#define RT305X_ESW_REG_POC0		0x90
++#define RT305X_ESW_REG_POC1		0x94
++#define RT305X_ESW_REG_POC2		0x98
++#define RT305X_ESW_REG_SGC		0x9c
++#define RT305X_ESW_REG_STRT		0xa0
++#define RT305X_ESW_REG_PCR0		0xc0
++#define RT305X_ESW_REG_PCR1		0xc4
++#define RT305X_ESW_REG_FPA2		0xc8
++#define RT305X_ESW_REG_FCT2		0xcc
++#define RT305X_ESW_REG_SGC2		0xe4
++#define RT305X_ESW_REG_P0LED		0xa4
++#define RT305X_ESW_REG_P1LED		0xa8
++#define RT305X_ESW_REG_P2LED		0xac
++#define RT305X_ESW_REG_P3LED		0xb0
++#define RT305X_ESW_REG_P4LED		0xb4
++#define RT305X_ESW_REG_PXPC(_x)		(0xe8 + (4 * _x))
++#define RT305X_ESW_REG_P1PC		0xec
++#define RT305X_ESW_REG_P2PC		0xf0
++#define RT305X_ESW_REG_P3PC		0xf4
++#define RT305X_ESW_REG_P4PC		0xf8
++#define RT305X_ESW_REG_P5PC		0xfc
++
++#define RT305X_ESW_LED_LINK		0
++#define RT305X_ESW_LED_100M		1
++#define RT305X_ESW_LED_DUPLEX		2
++#define RT305X_ESW_LED_ACTIVITY		3
++#define RT305X_ESW_LED_COLLISION	4
++#define RT305X_ESW_LED_LINKACT		5
++#define RT305X_ESW_LED_DUPLCOLL		6
++#define RT305X_ESW_LED_10MACT		7
++#define RT305X_ESW_LED_100MACT		8
++/* Additional led states not in datasheet: */
++#define RT305X_ESW_LED_BLINK		10
++#define RT305X_ESW_LED_ON		12
++
++#define RT305X_ESW_LINK_S		25
++#define RT305X_ESW_DUPLEX_S		9
++#define RT305X_ESW_SPD_S		0
++
++#define RT305X_ESW_PCR0_WT_NWAY_DATA_S	16
++#define RT305X_ESW_PCR0_WT_PHY_CMD	BIT(13)
++#define RT305X_ESW_PCR0_CPU_PHY_REG_S	8
++
++#define RT305X_ESW_PCR1_WT_DONE		BIT(0)
++
++#define RT305X_ESW_ATS_TIMEOUT		(5 * HZ)
++#define RT305X_ESW_PHY_TIMEOUT		(5 * HZ)
++
++#define RT305X_ESW_PVIDC_PVID_M		0xfff
++#define RT305X_ESW_PVIDC_PVID_S		12
++
++#define RT305X_ESW_VLANI_VID_M		0xfff
++#define RT305X_ESW_VLANI_VID_S		12
++
++#define RT305X_ESW_VMSC_MSC_M		0xff
++#define RT305X_ESW_VMSC_MSC_S		8
++
++#define RT305X_ESW_SOCPC_DISUN2CPU_S	0
++#define RT305X_ESW_SOCPC_DISMC2CPU_S	8
++#define RT305X_ESW_SOCPC_DISBC2CPU_S	16
++#define RT305X_ESW_SOCPC_CRC_PADDING	BIT(25)
++
++#define RT305X_ESW_POC0_EN_BP_S		0
++#define RT305X_ESW_POC0_EN_FC_S		8
++#define RT305X_ESW_POC0_DIS_RMC2CPU_S	16
++#define RT305X_ESW_POC0_DIS_PORT_M	0x7f
++#define RT305X_ESW_POC0_DIS_PORT_S	23
++
++#define RT305X_ESW_POC2_UNTAG_EN_M	0xff
++#define RT305X_ESW_POC2_UNTAG_EN_S	0
++#define RT305X_ESW_POC2_ENAGING_S	8
++#define RT305X_ESW_POC2_DIS_UC_PAUSE_S	16
++
++#define RT305X_ESW_SGC2_DOUBLE_TAG_M	0x7f
++#define RT305X_ESW_SGC2_DOUBLE_TAG_S	0
++#define RT305X_ESW_SGC2_LAN_PMAP_M	0x3f
++#define RT305X_ESW_SGC2_LAN_PMAP_S	24
++
++#define RT305X_ESW_PFC1_EN_VLAN_M	0xff
++#define RT305X_ESW_PFC1_EN_VLAN_S	16
++#define RT305X_ESW_PFC1_EN_TOS_S	24
++
++#define RT305X_ESW_VLAN_NONE		0xfff
++
++#define RT305X_ESW_GSC_BC_STROM_MASK	0x3
++#define RT305X_ESW_GSC_BC_STROM_SHIFT	4
++
++#define RT305X_ESW_GSC_LED_FREQ_MASK	0x3
++#define RT305X_ESW_GSC_LED_FREQ_SHIFT	23
++
++#define RT305X_ESW_POA_LINK_MASK	0x1f
++#define RT305X_ESW_POA_LINK_SHIFT	25
++
++#define RT305X_ESW_PORT_ST_CHG		BIT(26)
++#define RT305X_ESW_PORT0		0
++#define RT305X_ESW_PORT1		1
++#define RT305X_ESW_PORT2		2
++#define RT305X_ESW_PORT3		3
++#define RT305X_ESW_PORT4		4
++#define RT305X_ESW_PORT5		5
++#define RT305X_ESW_PORT6		6
++
++#define RT305X_ESW_PORTS_NONE		0
++
++#define RT305X_ESW_PMAP_LLLLLL		0x3f
++#define RT305X_ESW_PMAP_LLLLWL		0x2f
++#define RT305X_ESW_PMAP_WLLLLL		0x3e
++
++#define RT305X_ESW_PORTS_INTERNAL					\
++		(BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) |	\
++		 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) |	\
++		 BIT(RT305X_ESW_PORT4))
++
++#define RT305X_ESW_PORTS_NOCPU						\
++		(RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
++
++#define RT305X_ESW_PORTS_CPU	BIT(RT305X_ESW_PORT6)
++
++#define RT305X_ESW_PORTS_ALL						\
++		(RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
++
++#define RT305X_ESW_NUM_VLANS		16
++#define RT305X_ESW_NUM_VIDS		4096
++#define RT305X_ESW_NUM_PORTS		7
++#define RT305X_ESW_NUM_LANWAN		6
++#define RT305X_ESW_NUM_LEDS		5
++
++#define RT5350_ESW_REG_PXTPC(_x)	(0x150 + (4 * _x))
++#define RT5350_EWS_REG_LED_POLARITY	0x168
++#define RT5350_RESET_EPHY		BIT(24)
++#define SYSC_REG_RESET_CTRL		0x34
++
++enum {
++	/* Global attributes. */
++	RT305X_ESW_ATTR_ENABLE_VLAN,
++	RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
++	RT305X_ESW_ATTR_BC_STATUS,
++	RT305X_ESW_ATTR_LED_FREQ,
++	/* Port attributes. */
++	RT305X_ESW_ATTR_PORT_DISABLE,
++	RT305X_ESW_ATTR_PORT_DOUBLETAG,
++	RT305X_ESW_ATTR_PORT_UNTAG,
++	RT305X_ESW_ATTR_PORT_LED,
++	RT305X_ESW_ATTR_PORT_LAN,
++	RT305X_ESW_ATTR_PORT_RECV_BAD,
++	RT305X_ESW_ATTR_PORT_RECV_GOOD,
++	RT5350_ESW_ATTR_PORT_TR_BAD,
++	RT5350_ESW_ATTR_PORT_TR_GOOD,
++};
++
++struct esw_port {
++	bool	disable;
++	bool	doubletag;
++	bool	untag;
++	u8	led;
++	u16	pvid;
++};
++
++struct esw_vlan {
++	u8	ports;
++	u16	vid;
++};
++
++struct rt305x_esw {
++	struct device		*dev;
++	void __iomem		*base;
++	int			irq;
++	const struct rt305x_esw_platform_data *pdata;
++	/* Protects against concurrent register rmw operations. */
++	spinlock_t		reg_rw_lock;
++
++	unsigned char		port_map;
++	unsigned int		reg_initval_fct2;
++	unsigned int		reg_initval_fpa2;
++	unsigned int		reg_led_polarity;
++
++
++	struct switch_dev	swdev;
++	bool			global_vlan_enable;
++	bool			alt_vlan_disable;
++	int			bc_storm_protect;
++	int			led_frequency;
++	struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
++	struct esw_port ports[RT305X_ESW_NUM_PORTS];
++
++};
++
++static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
++{
++	__raw_writel(val, esw->base + reg);
++}
++
++static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
++{
++	return __raw_readl(esw->base + reg);
++}
++
++static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
++		   unsigned long val)
++{
++	unsigned long t;
++
++	t = __raw_readl(esw->base + reg) & ~mask;
++	__raw_writel(t | val, esw->base + reg);
++}
++
++static void esw_rmw(struct rt305x_esw *esw, unsigned reg, unsigned long mask,
++	       unsigned long val)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&esw->reg_rw_lock, flags);
++	esw_rmw_raw(esw, reg, mask, val);
++	spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
++}
++
++static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr, u32 phy_register,
++		 u32 write_data)
++{
++	unsigned long t_start = jiffies;
++	int ret = 0;
++
++	while (1) {
++		if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
++		      RT305X_ESW_PCR1_WT_DONE))
++			break;
++		if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
++			ret = 1;
++			goto out;
++		}
++	}
++
++	write_data &= 0xffff;
++	esw_w32(esw,
++		      (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
++		      (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
++		      (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
++		      RT305X_ESW_REG_PCR0);
++
++	t_start = jiffies;
++	while (1) {
++		if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
++		    RT305X_ESW_PCR1_WT_DONE)
++			break;
++
++		if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
++			ret = 1;
++			break;
++		}
++	}
++out:
++	if (ret)
++		printk(KERN_ERR "ramips_eth: MDIO timeout\n");
++	return ret;
++}
++
++static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
++{
++	unsigned s;
++	unsigned val;
++
++	s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
++	val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
++	val = (val >> s) & RT305X_ESW_VLANI_VID_M;
++
++	return val;
++}
++
++static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
++{
++	unsigned s;
++
++	s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
++	esw_rmw(esw,
++		       RT305X_ESW_REG_VLANI(vlan / 2),
++		       RT305X_ESW_VLANI_VID_M << s,
++		       (vid & RT305X_ESW_VLANI_VID_M) << s);
++}
++
++static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
++{
++	unsigned s, val;
++
++	s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
++	val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
++	return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
++}
++
++static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
++{
++	unsigned s;
++
++	s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
++	esw_rmw(esw,
++		       RT305X_ESW_REG_PVIDC(port / 2),
++		       RT305X_ESW_PVIDC_PVID_M << s,
++		       (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
++}
++
++static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
++{
++	unsigned s, val;
++
++	s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
++	val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
++	val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
++
++	return val;
++}
++
++static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
++{
++	unsigned s;
++
++	s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
++	esw_rmw(esw,
++		       RT305X_ESW_REG_VMSC(vlan / 4),
++		       RT305X_ESW_VMSC_MSC_M << s,
++		       (msc & RT305X_ESW_VMSC_MSC_M) << s);
++}
++
++static unsigned esw_get_port_disable(struct rt305x_esw *esw)
++{
++	unsigned reg;
++	reg = esw_r32(esw, RT305X_ESW_REG_POC0);
++	return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
++	       RT305X_ESW_POC0_DIS_PORT_M;
++}
++
++static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
++{
++	unsigned old_mask;
++	unsigned enable_mask;
++	unsigned changed;
++	int i;
++
++	old_mask = esw_get_port_disable(esw);
++	changed = old_mask ^ disable_mask;
++	enable_mask = old_mask & disable_mask;
++
++	/* enable before writing to MII */
++	esw_rmw(esw, RT305X_ESW_REG_POC0,
++		       (RT305X_ESW_POC0_DIS_PORT_M <<
++			RT305X_ESW_POC0_DIS_PORT_S),
++		       enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
++
++	for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
++		if (!(changed & (1 << i)))
++			continue;
++		if (disable_mask & (1 << i)) {
++			/* disable */
++			rt305x_mii_write(esw, i, MII_BMCR,
++					 BMCR_PDOWN);
++		} else {
++			/* enable */
++			rt305x_mii_write(esw, i, MII_BMCR,
++					 BMCR_FULLDPLX |
++					 BMCR_ANENABLE |
++					 BMCR_ANRESTART |
++					 BMCR_SPEED100);
++		}
++	}
++
++	/* disable after writing to MII */
++	esw_rmw(esw, RT305X_ESW_REG_POC0,
++		       (RT305X_ESW_POC0_DIS_PORT_M <<
++			RT305X_ESW_POC0_DIS_PORT_S),
++		       disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
++}
++
++static void esw_set_gsc(struct rt305x_esw *esw)
++{
++	esw_rmw(esw, RT305X_ESW_REG_SGC,
++		RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
++		esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
++	esw_rmw(esw, RT305X_ESW_REG_SGC,
++		RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
++		esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
++}
++
++static int esw_apply_config(struct switch_dev *dev);
++
++static void esw_hw_init(struct rt305x_esw *esw)
++{
++	int i;
++	u8 port_disable = 0;
++	u8 port_map = RT305X_ESW_PMAP_LLLLLL;
++
++	/* vodoo from original driver */
++	esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
++	esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
++	/* Port priority 1 for all ports, vlan enabled. */
++	esw_w32(esw, 0x00005555 |
++		      (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
++		      RT305X_ESW_REG_PFC1);
++
++	/* Enable Back Pressure, and Flow Control */
++	esw_w32(esw,
++		      ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
++		       (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
++		      RT305X_ESW_REG_POC0);
++
++	/* Enable Aging, and VLAN TAG removal */
++	esw_w32(esw,
++		      ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
++		       (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
++		      RT305X_ESW_REG_POC2);
++
++	if (esw->reg_initval_fct2)
++		esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
++	else
++		esw_w32(esw, esw->pdata->reg_initval_fct2, RT305X_ESW_REG_FCT2);
++
++	/*
++	 * 300s aging timer, max packet len 1536, broadcast storm prevention
++	 * disabled, disable collision abort, mac xor48 hash, 10 packet back
++	 * pressure jam, GMII disable was_transmit, back pressure disabled,
++	 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
++	 * ports.
++	 */
++	esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
++
++	/* Setup SoC Port control register */
++	esw_w32(esw,
++		      (RT305X_ESW_SOCPC_CRC_PADDING |
++		       (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
++		       (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
++		       (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
++		      RT305X_ESW_REG_SOCPC);
++
++	if (esw->reg_initval_fpa2)
++		esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
++	else
++		esw_w32(esw, esw->pdata->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
++	esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
++
++	/* Force Link/Activity on ports */
++	esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
++	esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
++	esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
++	esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
++	esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
++
++	/* Copy disabled port configuration from bootloader setup */
++	port_disable = esw_get_port_disable(esw);
++	for (i = 0; i < 6; i++)
++		esw->ports[i].disable = (port_disable & (1 << i)) != 0;
++
++	if (soc_is_rt3352()) {
++		/* reset EPHY */
++		u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
++		rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
++		rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
++
++		rt305x_mii_write(esw, 0, 31, 0x8000);
++		for (i = 0; i < 5; i++) {
++			if (esw->ports[i].disable) {
++				rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
++			} else {
++				rt305x_mii_write(esw, i, MII_BMCR,
++					 BMCR_FULLDPLX |
++					 BMCR_ANENABLE |
++					 BMCR_SPEED100);
++			}
++			/* TX10 waveform coefficient LSB=0 disable PHY */
++			rt305x_mii_write(esw, i, 26, 0x1601);
++			/* TX100/TX10 AD/DA current bias */
++			rt305x_mii_write(esw, i, 29, 0x7016);
++			/* TX100 slew rate control */
++			rt305x_mii_write(esw, i, 30, 0x0038);
++		}
++
++		/* select global register */
++		rt305x_mii_write(esw, 0, 31, 0x0);
++		/* enlarge agcsel threshold 3 and threshold 2 */
++		rt305x_mii_write(esw, 0, 1, 0x4a40);
++		/* enlarge agcsel threshold 5 and threshold 4 */
++		rt305x_mii_write(esw, 0, 2, 0x6254);
++		/* enlarge agcsel threshold  */
++		rt305x_mii_write(esw, 0, 3, 0xa17f);
++		rt305x_mii_write(esw, 0,12, 0x7eaa);
++		/* longer TP_IDL tail length */
++		rt305x_mii_write(esw, 0, 14, 0x65);
++		/* increased squelch pulse count threshold. */
++		rt305x_mii_write(esw, 0, 16, 0x0684);
++		/* set TX10 signal amplitude threshold to minimum */
++		rt305x_mii_write(esw, 0, 17, 0x0fe0);
++		/* set squelch amplitude to higher threshold */
++		rt305x_mii_write(esw, 0, 18, 0x40ba);
++		/* tune TP_IDL tail and head waveform, enable power down slew rate control */
++		rt305x_mii_write(esw, 0, 22, 0x253f);
++		/* set PLL/Receive bias current are calibrated */
++		rt305x_mii_write(esw, 0, 27, 0x2fda);
++		/* change PLL/Receive bias current to internal(RT3350) */
++		rt305x_mii_write(esw, 0, 28, 0xc410);
++		/* change PLL bias current to internal(RT3052_MP3) */
++		rt305x_mii_write(esw, 0, 29, 0x598b);
++		/* select local register */
++		rt305x_mii_write(esw, 0, 31, 0x8000);
++	} else if (soc_is_rt5350()) {
++		/* reset EPHY */
++		u32 val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
++		rt_sysc_w32(val | RT5350_RESET_EPHY, SYSC_REG_RESET_CTRL);
++		rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
++
++		/* set the led polarity */
++		esw_w32(esw, esw->reg_led_polarity & 0x1F, RT5350_EWS_REG_LED_POLARITY);
++
++		/* local registers */
++		rt305x_mii_write(esw, 0, 31, 0x8000);
++		for (i = 0; i < 5; i++) {
++			if (esw->ports[i].disable) {
++				rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
++			} else {
++				rt305x_mii_write(esw, i, MII_BMCR,
++					 BMCR_FULLDPLX |
++					 BMCR_ANENABLE |
++					 BMCR_SPEED100);
++			}
++			/* TX10 waveform coefficient LSB=0 disable PHY */
++			rt305x_mii_write(esw, i, 26, 0x1601);
++			/* TX100/TX10 AD/DA current bias */
++			rt305x_mii_write(esw, i, 29, 0x7015);
++			/* TX100 slew rate control */
++			rt305x_mii_write(esw, i, 30, 0x0038);
++		}
++
++		/* global registers */
++		rt305x_mii_write(esw, 0, 31, 0x0);
++		/* enlarge agcsel threshold 3 and threshold 2 */
++		rt305x_mii_write(esw, 0, 1, 0x4a40);
++		/* enlarge agcsel threshold 5 and threshold 4 */
++		rt305x_mii_write(esw, 0, 2, 0x6254);
++		/* enlarge agcsel threshold 6 */
++		rt305x_mii_write(esw, 0, 3, 0xa17f);
++		rt305x_mii_write(esw, 0, 12, 0x7eaa);
++		/* longer TP_IDL tail length */
++		rt305x_mii_write(esw, 0, 14, 0x65);
++		/* increased squelch pulse count threshold. */
++		rt305x_mii_write(esw, 0, 16, 0x0684);
++		/* set TX10 signal amplitude threshold to minimum */
++		rt305x_mii_write(esw, 0, 17, 0x0fe0);
++		/* set squelch amplitude to higher threshold */
++		rt305x_mii_write(esw, 0, 18, 0x40ba);
++		/* tune TP_IDL tail and head waveform, enable power down slew rate control */
++		rt305x_mii_write(esw, 0, 22, 0x253f);
++		/* set PLL/Receive bias current are calibrated */
++		rt305x_mii_write(esw, 0, 27, 0x2fda);
++		/* change PLL/Receive bias current to internal(RT3350) */
++		rt305x_mii_write(esw, 0, 28, 0xc410);
++		/* change PLL bias current to internal(RT3052_MP3) */
++		rt305x_mii_write(esw, 0, 29, 0x598b);
++		/* select local register */
++		rt305x_mii_write(esw, 0, 31, 0x8000);
++	} else {
++		rt305x_mii_write(esw, 0, 31, 0x8000);
++		for (i = 0; i < 5; i++) {
++			if (esw->ports[i].disable) {
++				rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
++			} else {
++				rt305x_mii_write(esw, i, MII_BMCR,
++					 BMCR_FULLDPLX |
++					 BMCR_ANENABLE |
++					 BMCR_SPEED100);
++			}
++			/* TX10 waveform coefficient */
++			rt305x_mii_write(esw, i, 26, 0x1601);
++			/* TX100/TX10 AD/DA current bias */
++			rt305x_mii_write(esw, i, 29, 0x7058);
++			/* TX100 slew rate control */
++			rt305x_mii_write(esw, i, 30, 0x0018);
++		}
++
++		/* PHY IOT */
++		/* select global register */
++		rt305x_mii_write(esw, 0, 31, 0x0);
++		/* tune TP_IDL tail and head waveform */
++		rt305x_mii_write(esw, 0, 22, 0x052f);
++		/* set TX10 signal amplitude threshold to minimum */
++		rt305x_mii_write(esw, 0, 17, 0x0fe0);
++		/* set squelch amplitude to higher threshold */
++		rt305x_mii_write(esw, 0, 18, 0x40ba);
++		/* longer TP_IDL tail length */
++		rt305x_mii_write(esw, 0, 14, 0x65);
++		/* select local register */
++		rt305x_mii_write(esw, 0, 31, 0x8000);
++	}
++
++	if (esw->port_map)
++		port_map = esw->port_map;
++	else
++		port_map = RT305X_ESW_PMAP_LLLLLL;
++
++	/*
++	 * Unused HW feature, but still nice to be consistent here...
++	 * This is also exported to userspace ('lan' attribute) so it's
++	 * conveniently usable to decide which ports go into the wan vlan by
++	 * default.
++	 */
++	esw_rmw(esw, RT305X_ESW_REG_SGC2,
++		       RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
++		       port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
++
++	/* make the switch leds blink */
++	for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
++		esw->ports[i].led = 0x05;
++
++	/* Apply the empty config. */
++	esw_apply_config(&esw->swdev);
++
++	/* Only unmask the port change interrupt */
++	esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
++}
++
++static irqreturn_t esw_interrupt(int irq, void *_esw)
++{
++	struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
++	u32 status;
++
++	status = esw_r32(esw, RT305X_ESW_REG_ISR);
++	if (status & RT305X_ESW_PORT_ST_CHG) {
++		u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
++		link >>= RT305X_ESW_POA_LINK_SHIFT;
++		link &= RT305X_ESW_POA_LINK_MASK;
++		dev_info(esw->dev, "link changed 0x%02X\n", link);
++	}
++	esw_w32(esw, status, RT305X_ESW_REG_ISR);
++
++	return IRQ_HANDLED;
++}
++
++static int esw_apply_config(struct switch_dev *dev)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	int i;
++	u8 disable = 0;
++	u8 doubletag = 0;
++	u8 en_vlan = 0;
++	u8 untag = 0;
++
++	for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
++		u32 vid, vmsc;
++		if (esw->global_vlan_enable) {
++			vid = esw->vlans[i].vid;
++			vmsc = esw->vlans[i].ports;
++		} else {
++			vid = RT305X_ESW_VLAN_NONE;
++			vmsc = RT305X_ESW_PORTS_NONE;
++		}
++		esw_set_vlan_id(esw, i, vid);
++		esw_set_vmsc(esw, i, vmsc);
++	}
++
++	for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
++		u32 pvid;
++		disable |= esw->ports[i].disable << i;
++		if (esw->global_vlan_enable) {
++			doubletag |= esw->ports[i].doubletag << i;
++			en_vlan   |= 1                       << i;
++			untag     |= esw->ports[i].untag     << i;
++			pvid       = esw->ports[i].pvid;
++		} else {
++			int x = esw->alt_vlan_disable ? 0 : 1;
++			doubletag |= x << i;
++			en_vlan   |= x << i;
++			untag     |= x << i;
++			pvid       = 0;
++		}
++		esw_set_pvid(esw, i, pvid);
++		if (i < RT305X_ESW_NUM_LEDS)
++			esw_w32(esw, esw->ports[i].led,
++				      RT305X_ESW_REG_P0LED + 4*i);
++	}
++
++	esw_set_gsc(esw);
++	esw_set_port_disable(esw, disable);
++	esw_rmw(esw, RT305X_ESW_REG_SGC2,
++		       (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
++			RT305X_ESW_SGC2_DOUBLE_TAG_S),
++		       doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
++	esw_rmw(esw, RT305X_ESW_REG_PFC1,
++		       RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
++		       en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
++	esw_rmw(esw, RT305X_ESW_REG_POC2,
++		       RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
++		       untag << RT305X_ESW_POC2_UNTAG_EN_S);
++
++	if (!esw->global_vlan_enable) {
++		/*
++		 * Still need to put all ports into vlan 0 or they'll be
++		 * isolated.
++		 * NOTE: vlan 0 is special, no vlan tag is prepended
++		 */
++		esw_set_vlan_id(esw, 0, 0);
++		esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
++	}
++
++	return 0;
++}
++
++static int esw_reset_switch(struct switch_dev *dev)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	esw->global_vlan_enable = 0;
++	memset(esw->ports, 0, sizeof(esw->ports));
++	memset(esw->vlans, 0, sizeof(esw->vlans));
++	esw_hw_init(esw);
++
++	return 0;
++}
++
++static int esw_get_vlan_enable(struct switch_dev *dev,
++			   const struct switch_attr *attr,
++			   struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	val->value.i = esw->global_vlan_enable;
++
++	return 0;
++}
++
++static int esw_set_vlan_enable(struct switch_dev *dev,
++			   const struct switch_attr *attr,
++			   struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	esw->global_vlan_enable = val->value.i != 0;
++
++	return 0;
++}
++
++static int esw_get_alt_vlan_disable(struct switch_dev *dev,
++				const struct switch_attr *attr,
++				struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	val->value.i = esw->alt_vlan_disable;
++
++	return 0;
++}
++
++static int esw_set_alt_vlan_disable(struct switch_dev *dev,
++				const struct switch_attr *attr,
++				struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	esw->alt_vlan_disable = val->value.i != 0;
++
++	return 0;
++}
++
++static int
++rt305x_esw_set_bc_status(struct switch_dev *dev,
++			const struct switch_attr *attr,
++			struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
++
++	return 0;
++}
++
++static int
++rt305x_esw_get_bc_status(struct switch_dev *dev,
++			const struct switch_attr *attr,
++			struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	val->value.i = esw->bc_storm_protect;
++
++	return 0;
++}
++
++static int
++rt305x_esw_set_led_freq(struct switch_dev *dev,
++			const struct switch_attr *attr,
++			struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
++
++	return 0;
++}
++
++static int
++rt305x_esw_get_led_freq(struct switch_dev *dev,
++			const struct switch_attr *attr,
++			struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	val->value.i = esw->led_frequency;
++
++	return 0;
++}
++
++static int esw_get_port_link(struct switch_dev *dev,
++			 int port,
++			 struct switch_port_link *link)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	u32 speed, poa;
++
++	if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
++		return -EINVAL;
++
++	poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
++
++	link->link = (poa >> RT305X_ESW_LINK_S) & 1;
++	link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
++	if (port < RT305X_ESW_NUM_LEDS) {
++		speed = (poa >> RT305X_ESW_SPD_S) & 1;
++	} else {
++		if (port == RT305X_ESW_NUM_PORTS - 1)
++			poa >>= 1;
++		speed = (poa >> RT305X_ESW_SPD_S) & 3;
++	}
++	switch (speed) {
++	case 0:
++		link->speed = SWITCH_PORT_SPEED_10;
++		break;
++	case 1:
++		link->speed = SWITCH_PORT_SPEED_100;
++		break;
++	case 2:
++	case 3: /* forced gige speed can be 2 or 3 */
++		link->speed = SWITCH_PORT_SPEED_1000;
++		break;
++	default:
++		link->speed = SWITCH_PORT_SPEED_UNKNOWN;
++		break;
++	}
++
++	return 0;
++}
++
++static int esw_get_port_bool(struct switch_dev *dev,
++			 const struct switch_attr *attr,
++			 struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	int idx = val->port_vlan;
++	u32 x, reg, shift;
++
++	if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
++		return -EINVAL;
++
++	switch (attr->id) {
++	case RT305X_ESW_ATTR_PORT_DISABLE:
++		reg = RT305X_ESW_REG_POC0;
++		shift = RT305X_ESW_POC0_DIS_PORT_S;
++		break;
++	case RT305X_ESW_ATTR_PORT_DOUBLETAG:
++		reg = RT305X_ESW_REG_SGC2;
++		shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
++		break;
++	case RT305X_ESW_ATTR_PORT_UNTAG:
++		reg = RT305X_ESW_REG_POC2;
++		shift = RT305X_ESW_POC2_UNTAG_EN_S;
++		break;
++	case RT305X_ESW_ATTR_PORT_LAN:
++		reg = RT305X_ESW_REG_SGC2;
++		shift = RT305X_ESW_SGC2_LAN_PMAP_S;
++		if (idx >= RT305X_ESW_NUM_LANWAN)
++			return -EINVAL;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	x = esw_r32(esw, reg);
++	val->value.i = (x >> (idx + shift)) & 1;
++
++	return 0;
++}
++
++static int esw_set_port_bool(struct switch_dev *dev,
++			 const struct switch_attr *attr,
++			 struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	int idx = val->port_vlan;
++
++	if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
++	    val->value.i < 0 || val->value.i > 1)
++		return -EINVAL;
++
++	switch (attr->id) {
++	case RT305X_ESW_ATTR_PORT_DISABLE:
++		esw->ports[idx].disable = val->value.i;
++		break;
++	case RT305X_ESW_ATTR_PORT_DOUBLETAG:
++		esw->ports[idx].doubletag = val->value.i;
++		break;
++	case RT305X_ESW_ATTR_PORT_UNTAG:
++		esw->ports[idx].untag = val->value.i;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int esw_get_port_recv_badgood(struct switch_dev *dev,
++				 const struct switch_attr *attr,
++				 struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	int idx = val->port_vlan;
++	int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
++	u32 reg;
++
++	if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
++		return -EINVAL;
++	reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
++	val->value.i = (reg >> shift) & 0xffff;
++
++	return 0;
++}
++
++static int
++esw_get_port_tr_badgood(struct switch_dev *dev,
++				 const struct switch_attr *attr,
++				 struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	int idx = val->port_vlan;
++	int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
++	u32 reg;
++
++	if (!soc_is_rt5350())
++		return -EINVAL;
++
++	if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
++		return -EINVAL;
++
++	reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
++	val->value.i = (reg >> shift) & 0xffff;
++
++	return 0;
++}
++
++static int esw_get_port_led(struct switch_dev *dev,
++			const struct switch_attr *attr,
++			struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	int idx = val->port_vlan;
++
++	if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
++	    idx >= RT305X_ESW_NUM_LEDS)
++		return -EINVAL;
++
++	val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
++
++	return 0;
++}
++
++static int esw_set_port_led(struct switch_dev *dev,
++			const struct switch_attr *attr,
++			struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	int idx = val->port_vlan;
++
++	if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
++		return -EINVAL;
++
++	esw->ports[idx].led = val->value.i;
++
++	return 0;
++}
++
++static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	if (port >= RT305X_ESW_NUM_PORTS)
++		return -EINVAL;
++
++	*val = esw_get_pvid(esw, port);
++
++	return 0;
++}
++
++static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++
++	if (port >= RT305X_ESW_NUM_PORTS)
++		return -EINVAL;
++
++	esw->ports[port].pvid = val;
++
++	return 0;
++}
++
++static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	u32 vmsc, poc2;
++	int vlan_idx = -1;
++	int i;
++
++	val->len = 0;
++
++	if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
++		return -EINVAL;
++
++	/* valid vlan? */
++	for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
++		if (esw_get_vlan_id(esw, i) == val->port_vlan &&
++		    esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
++			vlan_idx = i;
++			break;
++		}
++	}
++
++	if (vlan_idx == -1)
++		return -EINVAL;
++
++	vmsc = esw_get_vmsc(esw, vlan_idx);
++	poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
++
++	for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
++		struct switch_port *p;
++		int port_mask = 1 << i;
++
++		if (!(vmsc & port_mask))
++			continue;
++
++		p = &val->value.ports[val->len++];
++		p->id = i;
++		if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
++			p->flags = 0;
++		else
++			p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
++	}
++
++	return 0;
++}
++
++static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++{
++	struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
++	int ports;
++	int vlan_idx = -1;
++	int i;
++
++	if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
++	    val->len > RT305X_ESW_NUM_PORTS)
++		return -EINVAL;
++
++	/* one of the already defined vlans? */
++	for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
++		if (esw->vlans[i].vid == val->port_vlan &&
++		    esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
++			vlan_idx = i;
++			break;
++		}
++	}
++
++	/* select a free slot */
++	for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
++		if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
++			vlan_idx = i;
++	}
++
++	/* bail if all slots are in use */
++	if (vlan_idx == -1)
++		return -EINVAL;
++
++	ports = RT305X_ESW_PORTS_NONE;
++	for (i = 0; i < val->len; i++) {
++		struct switch_port *p = &val->value.ports[i];
++		int port_mask = 1 << p->id;
++		bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
++
++		if (p->id >= RT305X_ESW_NUM_PORTS)
++			return -EINVAL;
++
++		ports |= port_mask;
++		esw->ports[p->id].untag = untagged;
++	}
++	esw->vlans[vlan_idx].ports = ports;
++	if (ports == RT305X_ESW_PORTS_NONE)
++		esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
++	else
++		esw->vlans[vlan_idx].vid = val->port_vlan;
++
++	return 0;
++}
++
++static const struct switch_attr esw_global[] = {
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "enable_vlan",
++		.description = "VLAN mode (1:enabled)",
++		.max = 1,
++		.id = RT305X_ESW_ATTR_ENABLE_VLAN,
++		.get = esw_get_vlan_enable,
++		.set = esw_set_vlan_enable,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "alternate_vlan_disable",
++		.description = "Use en_vlan instead of doubletag to disable"
++				" VLAN mode",
++		.max = 1,
++		.id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
++		.get = esw_get_alt_vlan_disable,
++		.set = esw_set_alt_vlan_disable,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "bc_storm_protect",
++		.description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
++		.max = 3,
++		.id = RT305X_ESW_ATTR_BC_STATUS,
++		.get = rt305x_esw_get_bc_status,
++		.set = rt305x_esw_set_bc_status,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "led_frequency",
++		.description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
++		.max = 3,
++		.id = RT305X_ESW_ATTR_LED_FREQ,
++		.get = rt305x_esw_get_led_freq,
++		.set = rt305x_esw_set_led_freq,
++	}
++};
++
++static const struct switch_attr esw_port[] = {
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "disable",
++		.description = "Port state (1:disabled)",
++		.max = 1,
++		.id = RT305X_ESW_ATTR_PORT_DISABLE,
++		.get = esw_get_port_bool,
++		.set = esw_set_port_bool,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "doubletag",
++		.description = "Double tagging for incoming vlan packets "
++				"(1:enabled)",
++		.max = 1,
++		.id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
++		.get = esw_get_port_bool,
++		.set = esw_set_port_bool,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "untag",
++		.description = "Untag (1:strip outgoing vlan tag)",
++		.max = 1,
++		.id = RT305X_ESW_ATTR_PORT_UNTAG,
++		.get = esw_get_port_bool,
++		.set = esw_set_port_bool,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "led",
++		.description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
++				" 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
++				" 8:100mact, 10:blink, 11:off, 12:on)",
++		.max = 15,
++		.id = RT305X_ESW_ATTR_PORT_LED,
++		.get = esw_get_port_led,
++		.set = esw_set_port_led,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "lan",
++		.description = "HW port group (0:wan, 1:lan)",
++		.max = 1,
++		.id = RT305X_ESW_ATTR_PORT_LAN,
++		.get = esw_get_port_bool,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "recv_bad",
++		.description = "Receive bad packet counter",
++		.id = RT305X_ESW_ATTR_PORT_RECV_BAD,
++		.get = esw_get_port_recv_badgood,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "recv_good",
++		.description = "Receive good packet counter",
++		.id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
++		.get = esw_get_port_recv_badgood,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "tr_bad",
++
++		.description = "Transmit bad packet counter. rt5350 only",
++		.id = RT5350_ESW_ATTR_PORT_TR_BAD,
++		.get = esw_get_port_tr_badgood,
++	},
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "tr_good",
++
++		.description = "Transmit good packet counter. rt5350 only",
++		.id = RT5350_ESW_ATTR_PORT_TR_GOOD,
++		.get = esw_get_port_tr_badgood,
++	},
++};
++
++static const struct switch_attr esw_vlan[] = {
++};
++
++static const struct switch_dev_ops esw_ops = {
++	.attr_global = {
++		.attr = esw_global,
++		.n_attr = ARRAY_SIZE(esw_global),
++	},
++	.attr_port = {
++		.attr = esw_port,
++		.n_attr = ARRAY_SIZE(esw_port),
++	},
++	.attr_vlan = {
++		.attr = esw_vlan,
++		.n_attr = ARRAY_SIZE(esw_vlan),
++	},
++	.get_vlan_ports = esw_get_vlan_ports,
++	.set_vlan_ports = esw_set_vlan_ports,
++	.get_port_pvid = esw_get_port_pvid,
++	.set_port_pvid = esw_set_port_pvid,
++	.get_port_link = esw_get_port_link,
++	.apply_config = esw_apply_config,
++	.reset_switch = esw_reset_switch,
++};
++
++static struct rt305x_esw_platform_data rt3050_esw_data = {
++	/* All ports are LAN ports. */
++	.vlan_config            = RT305X_ESW_VLAN_CONFIG_NONE,
++	.reg_initval_fct2       = 0x00d6500c,
++	/*
++	 * ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
++	 * turbo mii off, rgmi 3.3v off
++	 * port5: disabled
++	 * port6: enabled, gige, full-duplex, rx/tx-flow-control
++	 */
++	.reg_initval_fpa2       = 0x3f502b28,
++};
++
++static const struct of_device_id ralink_esw_match[] = {
++	{ .compatible = "ralink,rt3050-esw", .data = &rt3050_esw_data },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ralink_esw_match);
++
++static int esw_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	const struct rt305x_esw_platform_data *pdata;
++	const __be32 *port_map, *reg_init;
++	struct rt305x_esw *esw;
++	struct switch_dev *swdev;
++	struct resource *res, *irq;
++	int err;
++
++	pdata = pdev->dev.platform_data;
++	if (!pdata) {
++		const struct of_device_id *match;
++		match = of_match_device(ralink_esw_match, &pdev->dev);
++		if (match)
++			pdata = (struct rt305x_esw_platform_data *) match->data;
++	}
++	if (!pdata)
++		return -EINVAL;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(&pdev->dev, "no memory resource found\n");
++		return -ENOMEM;
++	}
++
++	irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
++	if (!irq) {
++		dev_err(&pdev->dev, "no irq resource found\n");
++		return -ENOMEM;
++	}
++
++	esw = kzalloc(sizeof(struct rt305x_esw), GFP_KERNEL);
++	if (!esw) {
++		dev_err(&pdev->dev, "no memory for private data\n");
++		return -ENOMEM;
++	}
++
++	esw->dev = &pdev->dev;
++	esw->irq = irq->start;
++	esw->base = ioremap(res->start, resource_size(res));
++	if (!esw->base) {
++		dev_err(&pdev->dev, "ioremap failed\n");
++		err = -ENOMEM;
++		goto free_esw;
++	}
++
++	port_map = of_get_property(np, "ralink,portmap", NULL);
++        if (port_map)
++		esw->port_map = be32_to_cpu(*port_map);
++
++	reg_init = of_get_property(np, "ralink,fct2", NULL);
++        if (reg_init)
++		esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
++
++	reg_init = of_get_property(np, "ralink,fpa2", NULL);
++        if (reg_init)
++		esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
++
++	reg_init = of_get_property(np, "ralink,led_polarity", NULL);
++        if (reg_init)
++		esw->reg_led_polarity = be32_to_cpu(*reg_init);
++
++	swdev = &esw->swdev;
++	swdev->of_node = pdev->dev.of_node;
++	swdev->name = "rt305x-esw";
++	swdev->alias = "rt305x";
++	swdev->cpu_port = RT305X_ESW_PORT6;
++	swdev->ports = RT305X_ESW_NUM_PORTS;
++	swdev->vlans = RT305X_ESW_NUM_VIDS;
++	swdev->ops = &esw_ops;
++
++	err = register_switch(swdev, NULL);
++	if (err < 0) {
++		dev_err(&pdev->dev, "register_switch failed\n");
++		goto unmap_base;
++	}
++
++	platform_set_drvdata(pdev, esw);
++
++	esw->pdata = pdata;
++	spin_lock_init(&esw->reg_rw_lock);
++
++	esw_hw_init(esw);
++
++	esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
++	esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
++	request_irq(esw->irq, esw_interrupt, 0, "esw", esw);
++
++	return 0;
++
++unmap_base:
++	iounmap(esw->base);
++free_esw:
++	kfree(esw);
++	return err;
++}
++
++static int esw_remove(struct platform_device *pdev)
++{
++	struct rt305x_esw *esw;
++
++	esw = platform_get_drvdata(pdev);
++	if (esw) {
++		unregister_switch(&esw->swdev);
++		platform_set_drvdata(pdev, NULL);
++		iounmap(esw->base);
++		kfree(esw);
++	}
++
++	return 0;
++}
++
++static struct platform_driver esw_driver = {
++	.probe = esw_probe,
++	.remove = esw_remove,
++	.driver = {
++		.name = "rt305x-esw",
++		.owner = THIS_MODULE,
++		.of_match_table = ralink_esw_match,
++	},
++};
++
++int __init rtesw_init(void)
++{
++	return platform_driver_register(&esw_driver);
++}
++
++void rtesw_exit(void)
++{
++	platform_driver_unregister(&esw_driver);
++}
+diff --git a/drivers/net/ethernet/ralink/esw_rt3052.h b/drivers/net/ethernet/ralink/esw_rt3052.h
+new file mode 100644
+index 0000000..2ced3dff
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/esw_rt3052.h
+@@ -0,0 +1,32 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _RALINK_ESW_RT3052_H__
++#define _RALINK_ESW_RT3052_H__
++
++#ifdef CONFIG_NET_RALINK_ESW_RT3052
++
++int __init rtesw_init(void);
++void rtesw_exit(void);
++
++#else
++
++static inline int __init rtesw_init(void) { return 0; }
++static inline void rtesw_exit(void) { }
++
++#endif
++#endif
+diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.c b/drivers/net/ethernet/ralink/gsw_mt7620a.c
+new file mode 100644
+index 0000000..9fa6a54
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/gsw_mt7620a.c
+@@ -0,0 +1,1027 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/platform_device.h>
++#include <linux/of_device.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_mdio.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/switch.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "ralink_soc_eth.h"
++
++#include <linux/ioport.h>
++#include <linux/switch.h>
++#include <linux/mii.h>
++
++#include <ralink_regs.h>
++#include <asm/mach-ralink/mt7620.h>
++
++#include "ralink_soc_eth.h"
++#include "gsw_mt7620a.h"
++#include "mdio.h"
++
++#define GSW_REG_PHY_TIMEOUT	(5 * HZ)
++
++#define MT7620A_GSW_REG_PIAC	0x7004
++
++#define GSW_NUM_VLANS		16
++#define GSW_NUM_VIDS		4096
++#define GSW_NUM_PORTS		7
++#define GSW_PORT6		6
++
++#define GSW_MDIO_ACCESS		BIT(31)
++#define GSW_MDIO_READ		BIT(19)
++#define GSW_MDIO_WRITE		BIT(18)
++#define GSW_MDIO_START		BIT(16)
++#define GSW_MDIO_ADDR_SHIFT	20
++#define GSW_MDIO_REG_SHIFT	25
++
++#define GSW_REG_PORT_PMCR(x)	(0x3000 + (x * 0x100))
++#define GSW_REG_PORT_STATUS(x)	(0x3008 + (x * 0x100))
++#define GSW_REG_SMACCR0		0x3fE4
++#define GSW_REG_SMACCR1		0x3fE8
++#define GSW_REG_CKGCR		0x3ff0
++
++#define GSW_REG_IMR		0x7008
++#define GSW_REG_ISR		0x700c
++
++#define SYSC_REG_CFG1		0x14
++
++#define PORT_IRQ_ST_CHG		0x7f
++
++#define GSW_VLAN_VTCR		0x90
++#define GSW_VLAN_VTCR_VID_M	0xfff
++#define GSW_VLAN_ID(_x)		(0x100 + (4 * (_x)))
++#define GSW_VLAN_ID_VID_S	12
++#define GSW_VLAN_ID_VID_M	0xfff
++
++#define GSW_VAWD1		0x94
++#define GSW_VAWD1_VTAG_EN	BIT(28)
++#define GSW_VAWD1_PORTM_S	16
++#define GSW_VAWD1_PORTM_M	0xff
++
++#define GSW_VAWD2		0x98
++#define GSW_VAWD2_PORTT_S	16
++#define GSW_VAWD2_PORTT_M	0xff
++
++#define GSW_VTIM(_x)		(0x100 + (4 * (_x)))
++#define GSW_VTIM_M		0xfff
++#define GSW_VTIM_S		12
++
++#define GSW_REG_PCR(x)		(0x2004 + (x * 0x100))
++#define GSW_REG_PCR_EG_TAG_S	28
++#define GSW_REG_PCR_EG_TAG_M	0x3
++
++#define SYSCFG1			0x14
++
++#define ESW_PHY_POLLING		0x7000
++
++#define	PMCR_IPG		BIT(18)
++#define	PMCR_MAC_MODE		BIT(16)
++#define	PMCR_FORCE		BIT(15)
++#define	PMCR_TX_EN		BIT(14)
++#define	PMCR_RX_EN		BIT(13)
++#define	PMCR_BACKOFF		BIT(9)
++#define	PMCR_BACKPRES		BIT(8)
++#define	PMCR_RX_FC		BIT(5)
++#define	PMCR_TX_FC		BIT(4)
++#define	PMCR_SPEED(_x)		(_x << 2)
++#define	PMCR_DUPLEX		BIT(1)
++#define	PMCR_LINK		BIT(0)
++
++#define PHY_AN_EN		BIT(31)
++#define PHY_PRE_EN		BIT(30)
++#define PMY_MDC_CONF(_x)	((_x & 0x3f) << 24)
++
++enum {
++	/* Global attributes. */
++	GSW_ATTR_ENABLE_VLAN,
++	/* Port attributes. */
++	GSW_ATTR_PORT_UNTAG,
++};
++
++enum {
++	PORT4_EPHY = 0,
++	PORT4_EXT,
++};
++
++struct gsw_port {
++	bool	disable;
++	bool	untag;
++	u16	pvid;
++};
++
++struct gsw_vlan {
++	u8	ports;
++	u16	vid;
++};
++
++struct mt7620_gsw {
++	struct device		*dev;
++	void __iomem		*base;
++	int			irq;
++
++	struct switch_dev	swdev;
++	bool			global_vlan_enable;
++	struct gsw_vlan		vlans[GSW_NUM_VLANS];
++	struct gsw_port		ports[GSW_NUM_PORTS];
++	long unsigned int	autopoll;
++	int			port4;
++};
++
++static inline void gsw_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
++{
++	iowrite32(val, gsw->base + reg);
++}
++
++static inline u32 gsw_r32(struct mt7620_gsw *gsw, unsigned reg)
++{
++	return ioread32(gsw->base + reg);
++}
++
++static int mt7620_mii_busy_wait(struct mt7620_gsw *gsw)
++{
++	unsigned long t_start = jiffies;
++
++	while (1) {
++		if (!(gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & GSW_MDIO_ACCESS))
++			return 0;
++		if (time_after(jiffies, t_start + GSW_REG_PHY_TIMEOUT)) {
++			break;
++		}
++	}
++
++	printk(KERN_ERR "mdio: MDIO timeout\n");
++	return -1;
++}
++
++static u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr, u32 phy_register,
++				u32 write_data)
++{
++	if (mt7620_mii_busy_wait(gsw))
++		return -1;
++
++	write_data &= 0xffff;
++
++	gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_WRITE |
++		(phy_register << GSW_MDIO_REG_SHIFT) |
++		(phy_addr << GSW_MDIO_ADDR_SHIFT) | write_data,
++		MT7620A_GSW_REG_PIAC);
++
++	if (mt7620_mii_busy_wait(gsw))
++		return -1;
++
++	return 0;
++}
++
++int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
++{
++	struct fe_priv *priv = bus->priv;
++	struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
++
++	return _mt7620_mii_write(gsw, phy_addr, phy_reg, val);
++}
++
++int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
++{
++	struct fe_priv *priv = bus->priv;
++	struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
++	u32 d;
++
++	if (mt7620_mii_busy_wait(gsw))
++		return 0xffff;
++
++	gsw_w32(gsw, GSW_MDIO_ACCESS | GSW_MDIO_START | GSW_MDIO_READ |
++		(phy_reg << GSW_MDIO_REG_SHIFT) |
++		(phy_addr << GSW_MDIO_ADDR_SHIFT),
++		MT7620A_GSW_REG_PIAC);
++
++	if (mt7620_mii_busy_wait(gsw))
++		return 0xffff;
++
++	d = gsw_r32(gsw, MT7620A_GSW_REG_PIAC) & 0xffff;
++
++	return d;
++}
++
++static unsigned char *fe_speed_str(int speed)
++{
++	switch (speed) {
++	case 2:
++	case SPEED_1000:
++		return "1000";
++	case 1:
++	case SPEED_100:
++		return "100";
++	case 0:
++	case SPEED_10:
++		return "10";
++	}
++
++	return "? ";
++}
++
++int mt7620a_has_carrier(struct fe_priv *priv)
++{
++        struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
++	int i;
++
++	for (i = 0; i < GSW_PORT6; i++)
++		if (gsw_r32(gsw, GSW_REG_PORT_STATUS(i)) & 0x1)
++			return 1;
++	return 0;
++}
++
++static void mt7620a_handle_carrier(struct fe_priv *priv)
++{
++	if (!priv->phy)
++		return;
++
++	if (mt7620a_has_carrier(priv))
++		netif_carrier_on(priv->netdev);
++	else
++		netif_carrier_off(priv->netdev);
++}
++
++void mt7620_mdio_link_adjust(struct fe_priv *priv, int port)
++{
++	if (priv->link[port])
++		netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
++			port, fe_speed_str(priv->phy->speed[port]),
++			(DUPLEX_FULL == priv->phy->duplex[port]) ? "Full" : "Half");
++	else
++		netdev_info(priv->netdev, "port %d link down\n", port);
++	mt7620a_handle_carrier(priv);
++}
++
++static irqreturn_t gsw_interrupt(int irq, void *_priv)
++{
++	struct fe_priv *priv = (struct fe_priv *) _priv;
++	struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
++	u32 status;
++	int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
++
++	status = gsw_r32(gsw, GSW_REG_ISR);
++	if (status & PORT_IRQ_ST_CHG)
++		for (i = 0; i <= max; i++) {
++			u32 status = gsw_r32(gsw, GSW_REG_PORT_STATUS(i));
++			int link = status & 0x1;
++
++			if (link != priv->link[i]) {
++				if (link)
++					netdev_info(priv->netdev, "port %d link up (%sMbps/%s duplex)\n",
++							i, fe_speed_str((status >> 2) & 3),
++							(status & 0x2) ? "Full" : "Half");
++				else
++					netdev_info(priv->netdev, "port %d link down\n", i);
++			}
++
++			priv->link[i] = link;
++		}
++	mt7620a_handle_carrier(priv);
++
++	gsw_w32(gsw, status, GSW_REG_ISR);
++
++	return IRQ_HANDLED;
++}
++
++static int mt7620_is_bga(void)
++{
++	u32 bga = rt_sysc_r32(0x0c);
++
++	return (bga >> 16) & 1;
++}
++
++static void gsw_auto_poll(struct mt7620_gsw *gsw)
++{
++	int phy;
++	int lsb = -1, msb = 0;
++
++	for_each_set_bit(phy, &gsw->autopoll, 32) {
++		if (lsb < 0)
++			lsb = phy;
++		msb = phy;
++	}
++
++	gsw_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) | (msb << 8) | lsb, ESW_PHY_POLLING);
++}
++
++void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
++{
++	struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
++	const __be32 *_id = of_get_property(np, "reg", NULL);
++	int phy_mode, size, id;
++	int shift = 12;
++	u32 val, mask = 0;
++	int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
++
++	if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
++		if (_id)
++			pr_err("%s: invalid port id %d\n", np->name, be32_to_cpu(*_id));
++		else
++			pr_err("%s: invalid port id\n", np->name);
++		return;
++	}
++
++	id = be32_to_cpu(*_id);
++
++	if (id == 4)
++		shift = 14;
++
++	priv->phy->phy_fixed[id] = of_get_property(np, "ralink,fixed-link", &size);
++	if (priv->phy->phy_fixed[id] && (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
++		pr_err("%s: invalid fixed link property\n", np->name);
++		priv->phy->phy_fixed[id] = NULL;
++		return;
++	}
++
++	phy_mode = of_get_phy_mode(np);
++	switch (phy_mode) {
++	case PHY_INTERFACE_MODE_RGMII:
++		mask = 0;
++		break;
++	case PHY_INTERFACE_MODE_MII:
++		mask = 1;
++		break;
++	case PHY_INTERFACE_MODE_RMII:
++		mask = 2;
++		break;
++	default:
++		dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[id]);
++		return;
++	}
++
++	priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
++	if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
++		return;
++
++	val = rt_sysc_r32(SYSCFG1);
++	val &= ~(3 << shift);
++	val |= mask << shift;
++	rt_sysc_w32(val, SYSCFG1);
++
++	if (priv->phy->phy_fixed[id]) {
++		const __be32 *link = priv->phy->phy_fixed[id];
++		int tx_fc = be32_to_cpup(link++);
++		int rx_fc = be32_to_cpup(link++);
++		u32 val = 0;
++
++		priv->phy->speed[id] = be32_to_cpup(link++);
++		priv->phy->duplex[id] = be32_to_cpup(link++);
++		priv->link[id] = 1;
++
++		switch (priv->phy->speed[id]) {
++		case SPEED_10:
++			val = 0;
++			break;
++		case SPEED_100:
++			val = 1;
++			break;
++		case SPEED_1000:
++			val = 2;
++			break;
++		default:
++			dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[id]);
++			priv->phy->phy_fixed[id] = 0;
++			return;
++		}
++		val = PMCR_SPEED(val);
++		val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
++			PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
++		if (tx_fc)
++			val |= PMCR_TX_FC;
++		if (rx_fc)
++			val |= PMCR_RX_FC;
++		if (priv->phy->duplex[id])
++			val |= PMCR_DUPLEX;
++		gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
++		dev_info(priv->device, "using fixed link parameters\n");
++		return;
++	}
++
++	if (priv->phy->phy_node[id] && priv->mii_bus->phy_map[id]) {
++		u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
++			PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
++
++		gsw_w32(gsw, val, GSW_REG_PORT_PMCR(id));
++		fe_connect_phy_node(priv, priv->phy->phy_node[id]);
++		gsw->autopoll |= BIT(id);
++		gsw_auto_poll(gsw);
++		return;
++	}
++}
++
++static void gsw_hw_init(struct mt7620_gsw *gsw)
++{
++	u32 is_BGA = mt7620_is_bga();
++
++	rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
++	gsw_w32(gsw, gsw_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
++
++	/*correct  PHY  setting L3.0 BGA*/
++	_mt7620_mii_write(gsw, 1, 31, 0x4000); //global, page 4
++
++	_mt7620_mii_write(gsw, 1, 17, 0x7444);
++	if (is_BGA)
++		_mt7620_mii_write(gsw, 1, 19, 0x0114);
++	else
++		_mt7620_mii_write(gsw, 1, 19, 0x0117);
++
++	_mt7620_mii_write(gsw, 1, 22, 0x10cf);
++	_mt7620_mii_write(gsw, 1, 25, 0x6212);
++	_mt7620_mii_write(gsw, 1, 26, 0x0777);
++	_mt7620_mii_write(gsw, 1, 29, 0x4000);
++	_mt7620_mii_write(gsw, 1, 28, 0xc077);
++	_mt7620_mii_write(gsw, 1, 24, 0x0000);
++
++	_mt7620_mii_write(gsw, 1, 31, 0x3000); //global, page 3
++	_mt7620_mii_write(gsw, 1, 17, 0x4838);
++
++	_mt7620_mii_write(gsw, 1, 31, 0x2000); //global, page 2
++	if (is_BGA) {
++		_mt7620_mii_write(gsw, 1, 21, 0x0515);
++		_mt7620_mii_write(gsw, 1, 22, 0x0053);
++		_mt7620_mii_write(gsw, 1, 23, 0x00bf);
++		_mt7620_mii_write(gsw, 1, 24, 0x0aaf);
++		_mt7620_mii_write(gsw, 1, 25, 0x0fad);
++		_mt7620_mii_write(gsw, 1, 26, 0x0fc1);
++	} else {
++		_mt7620_mii_write(gsw, 1, 21, 0x0517);
++		_mt7620_mii_write(gsw, 1, 22, 0x0fd2);
++		_mt7620_mii_write(gsw, 1, 23, 0x00bf);
++		_mt7620_mii_write(gsw, 1, 24, 0x0aab);
++		_mt7620_mii_write(gsw, 1, 25, 0x00ae);
++		_mt7620_mii_write(gsw, 1, 26, 0x0fff);
++	}
++	_mt7620_mii_write(gsw, 1, 31, 0x1000); //global, page 1
++	_mt7620_mii_write(gsw, 1, 17, 0xe7f8);
++
++	_mt7620_mii_write(gsw, 1, 31, 0x8000); //local, page 0
++	_mt7620_mii_write(gsw, 0, 30, 0xa000);
++	_mt7620_mii_write(gsw, 1, 30, 0xa000);
++	_mt7620_mii_write(gsw, 2, 30, 0xa000);
++	_mt7620_mii_write(gsw, 3, 30, 0xa000);
++
++	_mt7620_mii_write(gsw, 0, 4, 0x05e1);
++	_mt7620_mii_write(gsw, 1, 4, 0x05e1);
++	_mt7620_mii_write(gsw, 2, 4, 0x05e1);
++	_mt7620_mii_write(gsw, 3, 4, 0x05e1);
++	_mt7620_mii_write(gsw, 1, 31, 0xa000); //local, page 2
++	_mt7620_mii_write(gsw, 0, 16, 0x1111);
++	_mt7620_mii_write(gsw, 1, 16, 0x1010);
++	_mt7620_mii_write(gsw, 2, 16, 0x1515);
++	_mt7620_mii_write(gsw, 3, 16, 0x0f0f);
++
++	/* CPU Port6 Force Link 1G, FC ON */
++	gsw_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
++	/* Set Port6 CPU Port */
++	gsw_w32(gsw, 0x7f7f7fe0, 0x0010);
++
++//	GSW_VAWD2
++
++	/* setup port 4 */
++	if (gsw->port4 == PORT4_EPHY) {
++		u32 val = rt_sysc_r32(SYSCFG1);
++		val |= 3 << 14;
++		rt_sysc_w32(val, SYSCFG1);
++		_mt7620_mii_write(gsw, 4, 30, 0xa000);
++		_mt7620_mii_write(gsw, 4, 4, 0x05e1);
++		_mt7620_mii_write(gsw, 4, 16, 0x1313);
++		pr_info("gsw: setting port4 to ephy mode\n");
++	}
++}
++
++static int gsw_reset_switch(struct switch_dev *dev)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++
++	gsw->global_vlan_enable = 0;
++	memset(gsw->ports, 0, sizeof(gsw->ports));
++	memset(gsw->vlans, 0, sizeof(gsw->vlans));
++	gsw_hw_init(gsw);
++
++	return 0;
++}
++
++static int gsw_get_vlan_enable(struct switch_dev *dev,
++			   const struct switch_attr *attr,
++			   struct switch_val *val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++
++	val->value.i = gsw->global_vlan_enable;
++
++	return 0;
++}
++
++static int gsw_set_vlan_enable(struct switch_dev *dev,
++			   const struct switch_attr *attr,
++			   struct switch_val *val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++
++	gsw->global_vlan_enable = val->value.i != 0;
++
++	return 0;
++}
++
++static unsigned gsw_get_pvid(struct mt7620_gsw *gsw, unsigned port)
++{
++	unsigned s, val;
++
++	s = GSW_VTIM_S * (port % 2);
++	val = gsw_r32(gsw, GSW_VTIM(port / 2));
++
++	return (val >> s) & GSW_VTIM_M;
++}
++
++static void gsw_set_pvid(struct mt7620_gsw *gsw, unsigned port, unsigned pvid)
++{
++	unsigned s, val;
++
++	s = GSW_VTIM_S * (port % 2);
++	val = gsw_r32(gsw, GSW_VTIM(port / 2));
++	val &= ~(GSW_VTIM_M << s);
++	val |= (pvid && GSW_VTIM_M) << s;
++	gsw_w32(gsw, val, GSW_VTIM(port / 2));
++}
++
++static int gsw_get_port_bool(struct switch_dev *dev,
++			 const struct switch_attr *attr,
++			 struct switch_val *val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	int idx = val->port_vlan;
++
++	if (idx < 0 || idx >= GSW_NUM_PORTS)
++		return -EINVAL;
++
++	switch (attr->id) {
++	case GSW_ATTR_PORT_UNTAG:
++		return gsw->ports[idx].untag;
++	}
++
++	return -EINVAL;
++}
++
++static int gsw_get_port_pvid(struct switch_dev *dev, int port, int *val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++
++	if (port >= GSW_NUM_PORTS)
++		return -EINVAL;
++
++	*val = gsw_get_pvid(gsw, port);
++
++	return 0;
++}
++
++static int gsw_set_port_pvid(struct switch_dev *dev, int port, int val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++
++	if (port >= GSW_NUM_PORTS)
++		return -EINVAL;
++
++	gsw->ports[port].pvid = val;
++
++	return 0;
++}
++
++static void gsw_set_vtcr(struct switch_dev *dev, u32 vid)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	int retry = 1000;
++
++	gsw_w32(gsw, 0x80000000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
++	while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
++		;
++}
++
++static void gsw_apply_vtcr(struct switch_dev *dev, u32 vid)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	int retry = 1000;
++
++	gsw_w32(gsw, 0x80001000 | (BIT(vid) & GSW_VLAN_VTCR_VID_M), GSW_VLAN_VTCR);
++	while (retry-- && (gsw_r32(gsw, GSW_VLAN_VTCR) & 0x80000000))
++		;
++}
++
++static unsigned gsw_get_vlan_id(struct mt7620_gsw *gsw, unsigned vlan)
++{
++	unsigned s;
++	unsigned val;
++
++	s = GSW_VLAN_ID_VID_S * (vlan % 2);
++	val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
++	val = (val >> s) & GSW_VLAN_ID_VID_M;
++
++	return val;
++}
++
++static void gsw_set_vlan_id(struct mt7620_gsw *gsw, unsigned vlan, unsigned vid)
++{
++	unsigned s;
++	unsigned val;
++
++	s = GSW_VLAN_ID_VID_S * (vlan % 2);
++	val = gsw_r32(gsw, GSW_VLAN_ID(vlan / 2));
++	val &= ~(GSW_VLAN_ID_VID_M << s);
++	val |= (vid << s);
++	gsw_w32(gsw, val, GSW_VLAN_ID(vlan / 2));
++}
++
++static void gsw_vlan_tagging_enable(struct mt7620_gsw *gsw, unsigned vlan, unsigned enable)
++{
++	unsigned val;
++
++	val = gsw_r32(gsw, GSW_VAWD1);
++	if (enable)
++		val |= GSW_VAWD1_VTAG_EN;
++	else
++		val &= ~GSW_VAWD1_VTAG_EN;
++	gsw_w32(gsw, val, GSW_VAWD1);
++}
++
++static unsigned gsw_get_port_member(struct mt7620_gsw *gsw, unsigned vlan)
++{
++	unsigned val;
++
++	gsw_set_vtcr(&gsw->swdev, vlan);
++
++	val = gsw_r32(gsw, GSW_VAWD1);
++	val = (val >> GSW_VAWD1_PORTM_S) & GSW_VAWD1_PORTM_M;
++
++	return val;
++}
++
++static void gsw_set_port_member(struct mt7620_gsw *gsw, unsigned vlan, unsigned member)
++{
++	unsigned val;
++
++	val = gsw_r32(gsw, GSW_VAWD1);
++	val = ~(GSW_VAWD1_PORTM_M << GSW_VAWD1_PORTM_S);
++	val |= (member & GSW_VAWD1_PORTM_M) << GSW_VAWD1_PORTM_S;
++        gsw_w32(gsw, val, GSW_VAWD1);
++}
++
++static unsigned gsw_get_port_tag(struct mt7620_gsw *gsw, unsigned port)
++{
++	unsigned val;
++
++	val = gsw_r32(gsw, GSW_REG_PCR(port));
++	val >>= GSW_REG_PCR_EG_TAG_S;
++	val &= GSW_REG_PCR_EG_TAG_M;
++
++	return !!val;
++}
++
++static void gsw_set_port_untag(struct mt7620_gsw *gsw, unsigned port, unsigned untag)
++{
++	unsigned val;
++
++	val = gsw_r32(gsw, GSW_REG_PCR(port));
++	if (!untag)
++		untag = 0x2;
++	else
++		untag = 0;
++	val &= ~(GSW_REG_PCR_EG_TAG_M << GSW_REG_PCR_EG_TAG_S);
++	val |= (untag & GSW_REG_PCR_EG_TAG_M) << GSW_REG_PCR_EG_TAG_S;
++	gsw_w32(gsw, val, GSW_REG_PCR(port));
++}
++
++static int gsw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	int vlan_idx = -1;
++	u32 member;
++	int i;
++
++	val->len = 0;
++
++	if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS)
++		return -EINVAL;
++
++	/* valid vlan? */
++	for (i = 0; i < GSW_NUM_VLANS; i++) {
++		if (gsw_get_vlan_id(gsw, i) != val->port_vlan)
++			continue;
++		member = gsw_get_port_member(gsw, i);
++		vlan_idx = i;
++		break;
++	}
++
++	if (vlan_idx == -1)
++		return -EINVAL;
++
++	for (i = 0; i < GSW_NUM_PORTS; i++) {
++		struct switch_port *p;
++		int port_mask = 1 << i;
++
++		if (!(member & port_mask))
++			continue;
++
++		p = &val->value.ports[val->len++];
++		p->id = i;
++		if (gsw_get_port_tag(gsw, i))
++			p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
++		else
++			p->flags = 0;
++	}
++
++	return 0;
++}
++
++static int gsw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	int ports;
++	int vlan_idx = -1;
++	int i;
++
++	if (val->port_vlan < 0 || val->port_vlan >= GSW_NUM_VIDS ||
++			val->len > GSW_NUM_PORTS)
++		return -EINVAL;
++
++	/* one of the already defined vlans? */
++	for (i = 0; i < GSW_NUM_VLANS; i++) {
++		if (gsw->vlans[i].vid == val->port_vlan &&
++		    gsw->vlans[i].ports) {
++			vlan_idx = i;
++			break;
++		}
++	}
++
++	/* select a free slot */
++	for (i = 0; vlan_idx == -1 && i < GSW_NUM_VLANS; i++) {
++		if (!gsw->vlans[i].ports)
++			vlan_idx = i;
++	}
++
++	/* bail if all slots are in use */
++	if (vlan_idx == -1)
++		return -EINVAL;
++
++	ports = 0;
++	for (i = 0; i < val->len; i++) {
++		struct switch_port *p = &val->value.ports[i];
++		int port_mask = 1 << p->id;
++		bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
++
++		if (p->id >= GSW_NUM_PORTS)
++			return -EINVAL;
++
++		ports |= port_mask;
++		gsw->ports[p->id].untag = untagged;
++	}
++	gsw->vlans[vlan_idx].ports = ports;
++	if (!ports)
++		gsw->vlans[vlan_idx].vid = 0xfff;
++	else
++		gsw->vlans[vlan_idx].vid = val->port_vlan;
++
++	return 0;
++}
++
++static int gsw_apply_config(struct switch_dev *dev)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	int i;
++
++	for (i = 0; i < GSW_NUM_VLANS; i++) {
++		gsw_set_vtcr(&gsw->swdev, i);
++		if (gsw->global_vlan_enable) {
++			gsw_set_vlan_id(gsw, i, gsw->vlans[i].vid);
++			gsw_set_port_member(gsw, i, gsw->vlans[i].ports);
++			gsw_vlan_tagging_enable(gsw, i, 1);
++		} else {
++			gsw_set_vlan_id(gsw, i, 0xfff);
++			gsw_set_port_member(gsw, i, 0);
++			gsw_vlan_tagging_enable(gsw, i, 0);
++		}
++		gsw_apply_vtcr(&gsw->swdev, i);
++	}
++
++	for (i = 0; i < GSW_NUM_PORTS; i++) {
++		if (gsw->global_vlan_enable) {
++			gsw_set_port_untag(gsw, i, !gsw->ports[i].untag);
++			gsw_set_pvid(gsw, i, gsw->ports[i].pvid);
++		} else {
++			gsw_set_port_untag(gsw, i, 0);
++			gsw_set_pvid(gsw, i, 0);
++		}
++	}
++
++	if (!gsw->global_vlan_enable)
++		gsw_set_vlan_id(gsw, 0, 0);
++
++	return 0;
++}
++
++static int gsw_get_port_link(struct switch_dev *dev,
++			 int port,
++			 struct switch_port_link *link)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	u32 status;
++
++	if (port < 0 || port >= GSW_NUM_PORTS)
++		return -EINVAL;
++
++	status = gsw_r32(gsw, GSW_REG_PORT_STATUS(port));
++	link->link = status & 0x1;
++	link->duplex = (status >> 1) & 1;
++
++	switch ((status >> 2) & 0x3) {
++	case 0:
++		link->speed = SWITCH_PORT_SPEED_10;
++		break;
++	case 1:
++		link->speed = SWITCH_PORT_SPEED_100;
++		break;
++	case 2:
++	case 3: // forced gige speed can be 2 or 3
++		link->speed = SWITCH_PORT_SPEED_1000;
++		break;
++	}
++
++	return 0;
++}
++
++static int gsw_set_port_bool(struct switch_dev *dev,
++			 const struct switch_attr *attr,
++			 struct switch_val *val)
++{
++	struct mt7620_gsw *gsw = container_of(dev, struct mt7620_gsw, swdev);
++	int idx = val->port_vlan;
++
++	if (idx < 0 || idx >= GSW_NUM_PORTS ||
++	    val->value.i < 0 || val->value.i > 1)
++		return -EINVAL;
++
++	switch (attr->id) {
++	case GSW_ATTR_PORT_UNTAG:
++		gsw->ports[idx].untag = val->value.i;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct switch_attr gsw_global[] = {
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "enable_vlan",
++		.description = "VLAN mode (1:enabled)",
++		.max = 1,
++		.id = GSW_ATTR_ENABLE_VLAN,
++		.get = gsw_get_vlan_enable,
++		.set = gsw_set_vlan_enable,
++	},
++};
++
++static const struct switch_attr gsw_port[] = {
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "untag",
++		.description = "Untag (1:strip outgoing vlan tag)",
++		.max = 1,
++		.id = GSW_ATTR_PORT_UNTAG,
++		.get = gsw_get_port_bool,
++		.set = gsw_set_port_bool,
++	},
++};
++
++static const struct switch_attr gsw_vlan[] = {
++};
++
++static const struct switch_dev_ops gsw_ops = {
++	.attr_global = {
++		.attr = gsw_global,
++		.n_attr = ARRAY_SIZE(gsw_global),
++	},
++	.attr_port = {
++		.attr = gsw_port,
++		.n_attr = ARRAY_SIZE(gsw_port),
++	},
++	.attr_vlan = {
++		.attr = gsw_vlan,
++		.n_attr = ARRAY_SIZE(gsw_vlan),
++	},
++	.get_vlan_ports = gsw_get_vlan_ports,
++	.set_vlan_ports = gsw_set_vlan_ports,
++	.get_port_pvid = gsw_get_port_pvid,
++	.set_port_pvid = gsw_set_port_pvid,
++	.get_port_link = gsw_get_port_link,
++	.apply_config = gsw_apply_config,
++	.reset_switch = gsw_reset_switch,
++};
++
++void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
++{
++	struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->page_lock, flags);
++	gsw_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
++	gsw_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
++		GSW_REG_SMACCR0);
++	spin_unlock_irqrestore(&priv->page_lock, flags);
++}
++
++static struct of_device_id gsw_match[] = {
++	{ .compatible = "ralink,mt7620a-gsw" },
++	{}
++};
++
++int mt7620_gsw_probe(struct fe_priv *priv)
++{
++	struct mt7620_gsw *gsw;
++	struct device_node *np;
++	struct switch_dev *swdev;
++	const char *port4 = NULL;
++
++	np = of_find_matching_node(NULL, gsw_match);
++	if (!np) {
++		dev_err(priv->device, "no gsw node found\n");
++		return -EINVAL;
++	}
++	np = of_node_get(np);
++
++	gsw = devm_kzalloc(priv->device, sizeof(struct mt7620_gsw), GFP_KERNEL);
++	if (!gsw) {
++		dev_err(priv->device, "no gsw memory for private data\n");
++		return -ENOMEM;
++	}
++
++	gsw->irq = irq_of_parse_and_map(np, 0);
++	if (!gsw->irq) {
++		dev_err(priv->device, "no gsw irq resource found\n");
++		return -ENOMEM;
++	}
++
++	gsw->base = of_iomap(np, 0);
++	if (!gsw->base) {
++		dev_err(priv->device, "gsw ioremap failed\n");
++	}
++
++	gsw->dev = priv->device;
++	priv->soc->swpriv = gsw;
++
++	swdev = &gsw->swdev;
++	swdev->of_node = np;
++	swdev->name = "mt7620a-gsw";
++	swdev->alias = "mt7620x";
++	swdev->cpu_port = GSW_PORT6;
++	swdev->ports = GSW_NUM_PORTS;
++	swdev->vlans = GSW_NUM_VLANS;
++	swdev->ops = &gsw_ops;
++
++	if (register_switch(swdev, NULL))
++		dev_err(priv->device, "register_switch failed\n");
++
++	of_property_read_string(np, "ralink,port4", &port4);
++	if (port4 && !strcmp(port4, "ephy"))
++		gsw->port4 = PORT4_EPHY;
++	else if (port4 && !strcmp(port4, "gmac"))
++		gsw->port4 = PORT4_EXT;
++	else
++		WARN_ON(port4);
++
++	gsw_hw_init(gsw);
++
++	gsw_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
++	request_irq(gsw->irq, gsw_interrupt, 0, "gsw", priv);
++
++	return 0;
++}
+diff --git a/drivers/net/ethernet/ralink/gsw_mt7620a.h b/drivers/net/ethernet/ralink/gsw_mt7620a.h
+new file mode 100644
+index 0000000..fd4add5
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/gsw_mt7620a.h
+@@ -0,0 +1,29 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _RALINK_GSW_MT7620_H__
++#define _RALINK_GSW_MT7620_H__
++
++extern int mt7620_gsw_probe(struct fe_priv *priv);
++extern void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac);
++extern int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
++extern int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
++extern void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
++extern void mt7620_port_init(struct fe_priv *priv, struct device_node *np);
++extern int mt7620a_has_carrier(struct fe_priv *priv);
++
++#endif
+diff --git a/drivers/net/ethernet/ralink/mdio.c b/drivers/net/ethernet/ralink/mdio.c
+new file mode 100644
+index 0000000..b265c75
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/mdio.c
+@@ -0,0 +1,245 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/platform_device.h>
++#include <linux/phy.h>
++#include <linux/of_device.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_mdio.h>
++
++#include "ralink_soc_eth.h"
++#include "mdio.h"
++
++static int fe_mdio_reset(struct mii_bus *bus)
++{
++	/* TODO */
++	return 0;
++}
++
++static void fe_phy_link_adjust(struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++	unsigned long flags;
++	int i;
++
++	spin_lock_irqsave(&priv->phy->lock, flags);
++	for (i = 0; i < 8; i++) {
++		if (priv->phy->phy_node[i]) {
++			struct phy_device *phydev = priv->phy->phy[i];
++			int status_change = 0;
++
++			if (phydev->link)
++				if (priv->phy->duplex[i] != phydev->duplex ||
++						priv->phy->speed[i] != phydev->speed)
++					status_change = 1;
++
++			if (phydev->link != priv->link[i])
++				status_change = 1;
++
++			switch (phydev->speed) {
++			case SPEED_1000:
++			case SPEED_100:
++			case SPEED_10:
++				priv->link[i] = phydev->link;
++				priv->phy->duplex[i] = phydev->duplex;
++				priv->phy->speed[i] = phydev->speed;
++
++				if (status_change && priv->soc->mdio_adjust_link)
++					priv->soc->mdio_adjust_link(priv, i);
++				break;
++			}
++		}
++	}
++	spin_unlock_irqrestore(&priv->phy->lock, flags);
++}
++
++int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node)
++{
++	const __be32 *_port = NULL;
++	struct phy_device *phydev;
++	int phy_mode, port;
++
++	_port = of_get_property(phy_node, "reg", NULL);
++
++	if (!_port || (be32_to_cpu(*_port) >= 8)) {
++		pr_err("%s: invalid port id\n", phy_node->name);
++		return -EINVAL;
++	}
++	port = be32_to_cpu(*_port);
++	phy_mode = of_get_phy_mode(phy_node);
++	if (phy_mode < 0) {
++		dev_err(priv->device, "incorrect phy-mode %d\n", phy_mode);
++		priv->phy->phy_node[port] = NULL;
++		return -EINVAL;
++	}
++
++	phydev = of_phy_connect(priv->netdev, phy_node, fe_phy_link_adjust,
++				0, phy_mode);
++	if (IS_ERR(phydev)) {
++		dev_err(priv->device, "could not connect to PHY\n");
++		priv->phy->phy_node[port] = NULL;
++		return PTR_ERR(phydev);
++	}
++
++	phydev->supported &= PHY_GBIT_FEATURES;
++	phydev->advertising = phydev->supported;
++	phydev->no_auto_carrier_off = 1;
++
++	dev_info(priv->device,
++		 "connected port %d to PHY at %s [uid=%08x, driver=%s]\n",
++		 port, dev_name(&phydev->dev), phydev->phy_id,
++		 phydev->drv->name);
++
++	priv->phy->phy[port] = phydev;
++	priv->link[port] = 0;
++
++	return 0;
++}
++
++static int fe_phy_connect(struct fe_priv *priv)
++{
++	return 0;
++}
++
++static void fe_phy_disconnect(struct fe_priv *priv)
++{
++	unsigned long flags;
++	int i;
++
++	for (i = 0; i < 8; i++)
++		if (priv->phy->phy_fixed[i]) {
++			spin_lock_irqsave(&priv->phy->lock, flags);
++			priv->link[i] = 0;
++			if (priv->soc->mdio_adjust_link)
++				priv->soc->mdio_adjust_link(priv, i);
++			spin_unlock_irqrestore(&priv->phy->lock, flags);
++		} else if (priv->phy->phy[i]) {
++			phy_disconnect(priv->phy->phy[i]);
++		}
++}
++
++static void fe_phy_start(struct fe_priv *priv)
++{
++	unsigned long flags;
++	int i;
++
++	for (i = 0; i < 8; i++) {
++		if (priv->phy->phy_fixed[i]) {
++			spin_lock_irqsave(&priv->phy->lock, flags);
++			priv->link[i] = 1;
++			if (priv->soc->mdio_adjust_link)
++				priv->soc->mdio_adjust_link(priv, i);
++			spin_unlock_irqrestore(&priv->phy->lock, flags);
++		} else if (priv->phy->phy[i]) {
++			phy_start(priv->phy->phy[i]);
++		}
++	}
++}
++
++static void fe_phy_stop(struct fe_priv *priv)
++{
++	unsigned long flags;
++	int i;
++
++	for (i = 0; i < 8; i++)
++		if (priv->phy->phy_fixed[i]) {
++			spin_lock_irqsave(&priv->phy->lock, flags);
++			priv->link[i] = 0;
++			if (priv->soc->mdio_adjust_link)
++				priv->soc->mdio_adjust_link(priv, i);
++			spin_unlock_irqrestore(&priv->phy->lock, flags);
++		} else if (priv->phy->phy[i]) {
++			phy_stop(priv->phy->phy[i]);
++		}
++}
++
++static struct fe_phy phy_ralink = {
++	.connect = fe_phy_connect,
++	.disconnect = fe_phy_disconnect,
++	.start = fe_phy_start,
++	.stop = fe_phy_stop,
++};
++
++int fe_mdio_init(struct fe_priv *priv)
++{
++	struct device_node *mii_np;
++	int err;
++
++	if (!priv->soc->mdio_read || !priv->soc->mdio_write)
++		return 0;
++
++	spin_lock_init(&phy_ralink.lock);
++	priv->phy = &phy_ralink;
++
++	mii_np = of_get_child_by_name(priv->device->of_node, "mdio-bus");
++	if (!mii_np) {
++		dev_err(priv->device, "no %s child node found", "mdio-bus");
++		return -ENODEV;
++	}
++
++	if (!of_device_is_available(mii_np)) {
++		err = 0;
++		goto err_put_node;
++	}
++
++	priv->mii_bus = mdiobus_alloc();
++	if (priv->mii_bus == NULL) {
++		err = -ENOMEM;
++		goto err_put_node;
++	}
++
++	priv->mii_bus->name = "mdio";
++	priv->mii_bus->read = priv->soc->mdio_read;
++	priv->mii_bus->write = priv->soc->mdio_write;
++	priv->mii_bus->reset = fe_mdio_reset;
++	priv->mii_bus->irq = priv->mii_irq;
++	priv->mii_bus->priv = priv;
++	priv->mii_bus->parent = priv->device;
++
++	snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
++	err = of_mdiobus_register(priv->mii_bus, mii_np);
++	if (err)
++		goto err_free_bus;
++
++	return 0;
++
++err_free_bus:
++	kfree(priv->mii_bus);
++err_put_node:
++	of_node_put(mii_np);
++	priv->mii_bus = NULL;
++	return err;
++}
++
++void fe_mdio_cleanup(struct fe_priv *priv)
++{
++	if (!priv->mii_bus)
++		return;
++
++	mdiobus_unregister(priv->mii_bus);
++	of_node_put(priv->mii_bus->dev.of_node);
++	kfree(priv->mii_bus);
++}
+diff --git a/drivers/net/ethernet/ralink/mdio.h b/drivers/net/ethernet/ralink/mdio.h
+new file mode 100644
+index 0000000..c3910a0
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/mdio.h
+@@ -0,0 +1,29 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _RALINK_MDIO_H__
++#define _RALINK_MDIO_H__
++
++#ifdef CONFIG_NET_RALINK_MDIO
++extern int fe_mdio_init(struct fe_priv *priv);
++extern void fe_mdio_cleanup(struct fe_priv *priv);
++extern int fe_connect_phy_node(struct fe_priv *priv, struct device_node *phy_node);
++#else
++static inline int fe_mdio_init(struct fe_priv *priv) { return 0; }
++static inline void fe_mdio_cleanup(struct fe_priv *priv) {}
++#endif
++#endif
+diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.c b/drivers/net/ethernet/ralink/mdio_rt2880.c
+new file mode 100644
+index 0000000..701c7b6
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/mdio_rt2880.c
+@@ -0,0 +1,232 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/platform_device.h>
++#include <linux/phy.h>
++#include <linux/of_device.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_mdio.h>
++
++#include "ralink_soc_eth.h"
++#include "mdio_rt2880.h"
++#include "mdio.h"
++
++#define FE_MDIO_RETRY	1000
++
++static unsigned char *rt2880_speed_str(struct fe_priv *priv)
++{
++	switch (priv->phy->speed[0]) {
++	case SPEED_1000:
++		return "1000";
++	case SPEED_100:
++		return "100";
++	case SPEED_10:
++		return "10";
++	}
++
++	return "?";
++}
++
++void rt2880_mdio_link_adjust(struct fe_priv *priv, int port)
++{
++	u32 mdio_cfg;
++
++	if (!priv->link[0]) {
++		netif_carrier_off(priv->netdev);
++		netdev_info(priv->netdev, "link down\n");
++		return;
++	}
++
++	mdio_cfg = FE_MDIO_CFG_TX_CLK_SKEW_200 |
++		   FE_MDIO_CFG_RX_CLK_SKEW_200 |
++		   FE_MDIO_CFG_GP1_FRC_EN;
++
++	if (priv->phy->duplex[0] == DUPLEX_FULL)
++		mdio_cfg |= FE_MDIO_CFG_GP1_DUPLEX;
++
++	if (priv->phy->tx_fc[0])
++		mdio_cfg |= FE_MDIO_CFG_GP1_FC_TX;
++
++	if (priv->phy->rx_fc[0])
++		mdio_cfg |= FE_MDIO_CFG_GP1_FC_RX;
++
++	switch (priv->phy->speed[0]) {
++	case SPEED_10:
++		mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_10;
++		break;
++	case SPEED_100:
++		mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_100;
++		break;
++	case SPEED_1000:
++		mdio_cfg |= FE_MDIO_CFG_GP1_SPEED_1000;
++		break;
++	default:
++		BUG();
++	}
++
++	fe_w32(mdio_cfg, FE_MDIO_CFG);
++
++	netif_carrier_on(priv->netdev);
++	netdev_info(priv->netdev, "link up (%sMbps/%s duplex)\n",
++		    rt2880_speed_str(priv),
++		    (DUPLEX_FULL == priv->phy->duplex[0]) ? "Full" : "Half");
++}
++
++static int rt2880_mdio_wait_ready(struct fe_priv *priv)
++{
++	int retries;
++
++	retries = FE_MDIO_RETRY;
++	while (1) {
++		u32 t;
++
++		t = fe_r32(FE_MDIO_ACCESS);
++		if ((t & (0x1 << 31)) == 0)
++			return 0;
++
++		if (retries-- == 0)
++			break;
++
++		udelay(1);
++	}
++
++	dev_err(priv->device, "MDIO operation timed out\n");
++	return -ETIMEDOUT;
++}
++
++int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
++{
++	struct fe_priv *priv = bus->priv;
++	int err;
++	u32 t;
++
++	err = rt2880_mdio_wait_ready(priv);
++	if (err)
++		return 0xffff;
++
++	t = (phy_addr << 24) | (phy_reg << 16);
++	fe_w32(t, FE_MDIO_ACCESS);
++	t |= (1 << 31);
++	fe_w32(t, FE_MDIO_ACCESS);
++
++	err = rt2880_mdio_wait_ready(priv);
++	if (err)
++		return 0xffff;
++
++	pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
++		phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
++
++	return fe_r32(FE_MDIO_ACCESS) & 0xffff;
++}
++
++int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val)
++{
++	struct fe_priv *priv = bus->priv;
++	int err;
++	u32 t;
++
++	pr_info("%s: addr=%04x, reg=%04x, value=%04x\n", __func__,
++		phy_addr, phy_reg, fe_r32(FE_MDIO_ACCESS) & 0xffff);
++
++	err = rt2880_mdio_wait_ready(priv);
++	if (err)
++		return err;
++
++	t = (1 << 30) | (phy_addr << 24) | (phy_reg << 16) | val;
++	fe_w32(t, FE_MDIO_ACCESS);
++	t |= (1 << 31);
++	fe_w32(t, FE_MDIO_ACCESS);
++
++	return rt2880_mdio_wait_ready(priv);
++}
++
++void rt2880_port_init(struct fe_priv *priv, struct device_node *np)
++{
++	const __be32 *id = of_get_property(np, "reg", NULL);
++	const __be32 *link;
++	int size;
++	int phy_mode;
++
++	if (!id || (be32_to_cpu(*id) != 0)) {
++		pr_err("%s: invalid port id\n", np->name);
++		return;
++	}
++
++	priv->phy->phy_fixed[0] = of_get_property(np, "ralink,fixed-link", &size);
++	if (priv->phy->phy_fixed[0] && (size != (4 * sizeof(*priv->phy->phy_fixed[0])))) {
++		pr_err("%s: invalid fixed link property\n", np->name);
++		priv->phy->phy_fixed[0] = NULL;
++		return;
++	}
++
++	phy_mode = of_get_phy_mode(np);
++	switch (phy_mode) {
++	case PHY_INTERFACE_MODE_RGMII:
++		break;
++	case PHY_INTERFACE_MODE_MII:
++		break;
++	case PHY_INTERFACE_MODE_RMII:
++		break;
++	default:
++		if (!priv->phy->phy_fixed[0])
++			dev_err(priv->device, "port %d - invalid phy mode\n", priv->phy->speed[0]);
++		break;
++	}
++
++	priv->phy->phy_node[0] = of_parse_phandle(np, "phy-handle", 0);
++	if (!priv->phy->phy_node[0] && !priv->phy->phy_fixed[0])
++		return;
++
++	if (priv->phy->phy_fixed[0]) {
++		link = priv->phy->phy_fixed[0];
++		priv->phy->speed[0] = be32_to_cpup(link++);
++		priv->phy->duplex[0] = be32_to_cpup(link++);
++		priv->phy->tx_fc[0] = be32_to_cpup(link++);
++		priv->phy->rx_fc[0] = be32_to_cpup(link++);
++
++		priv->link[0] = 1;
++		switch (priv->phy->speed[0]) {
++		case SPEED_10:
++			break;
++		case SPEED_100:
++			break;
++		case SPEED_1000:
++			break;
++		default:
++			dev_err(priv->device, "invalid link speed: %d\n", priv->phy->speed[0]);
++			priv->phy->phy_fixed[0] = 0;
++			return;
++		}
++		dev_info(priv->device, "using fixed link parameters\n");
++		rt2880_mdio_link_adjust(priv, 0);
++		return;
++	}
++	if (priv->phy->phy_node[0] && priv->mii_bus->phy_map[0]) {
++		fe_connect_phy_node(priv, priv->phy->phy_node[0]);
++	}
++
++	return;
++}
+diff --git a/drivers/net/ethernet/ralink/mdio_rt2880.h b/drivers/net/ethernet/ralink/mdio_rt2880.h
+new file mode 100644
+index 0000000..51e3633
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/mdio_rt2880.h
+@@ -0,0 +1,26 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef _RALINK_MDIO_RT2880_H__
++#define _RALINK_MDIO_RT2880_H__
++
++void rt2880_mdio_link_adjust(struct fe_priv *priv, int port);
++int rt2880_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
++int rt2880_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
++void rt2880_port_init(struct fe_priv *priv, struct device_node *np);
++
++#endif
+diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.c b/drivers/net/ethernet/ralink/ralink_soc_eth.c
+new file mode 100644
+index 0000000..8c36dba
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/ralink_soc_eth.c
+@@ -0,0 +1,735 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/types.h>
++#include <linux/dma-mapping.h>
++#include <linux/init.h>
++#include <linux/skbuff.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool.h>
++#include <linux/platform_device.h>
++#include <linux/of_device.h>
++#include <linux/clk.h>
++#include <linux/of_net.h>
++#include <linux/of_mdio.h>
++#include <linux/if_vlan.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "ralink_soc_eth.h"
++#include "esw_rt3052.h"
++#include "mdio.h"
++
++#define TX_TIMEOUT		(20 * HZ / 100)
++#define	MAX_RX_LENGTH		1536
++
++static const u32 fe_reg_table_default[FE_REG_COUNT] = {
++	[FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
++	[FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
++	[FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
++	[FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
++	[FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
++	[FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
++	[FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
++	[FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
++	[FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
++	[FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
++	[FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
++};
++
++static const u32 *fe_reg_table = fe_reg_table_default;
++
++static void __iomem *fe_base = 0;
++
++void fe_w32(u32 val, unsigned reg)
++{
++	__raw_writel(val, fe_base + reg);
++}
++
++u32 fe_r32(unsigned reg)
++{
++	return __raw_readl(fe_base + reg);
++}
++
++static inline void fe_reg_w32(u32 val, enum fe_reg reg)
++{
++	fe_w32(val, fe_reg_table[reg]);
++}
++
++static inline u32 fe_reg_r32(enum fe_reg reg)
++{
++	return fe_r32(fe_reg_table[reg]);
++}
++
++static inline void fe_int_disable(u32 mask)
++{
++	fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
++		     FE_REG_FE_INT_ENABLE);
++	/* flush write */
++	fe_reg_r32(FE_REG_FE_INT_ENABLE);
++}
++
++static inline void fe_int_enable(u32 mask)
++{
++	fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
++		     FE_REG_FE_INT_ENABLE);
++	/* flush write */
++	fe_reg_r32(FE_REG_FE_INT_ENABLE);
++}
++
++static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->page_lock, flags);
++	fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
++	fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
++		     FE_GDMA1_MAC_ADRL);
++	spin_unlock_irqrestore(&priv->page_lock, flags);
++}
++
++static int fe_set_mac_address(struct net_device *dev, void *p)
++{
++	int ret = eth_mac_addr(dev, p);
++
++	if (!ret) {
++		struct fe_priv *priv = netdev_priv(dev);
++
++		if (priv->soc->set_mac)
++			priv->soc->set_mac(priv, dev->dev_addr);
++		else
++			fe_hw_set_macaddr(priv, p);
++	}
++
++	return ret;
++}
++
++static struct sk_buff* fe_alloc_skb(struct fe_priv *priv)
++{
++	struct sk_buff *skb;
++
++	skb = netdev_alloc_skb(priv->netdev, MAX_RX_LENGTH + NET_IP_ALIGN);
++	if (!skb)
++		return NULL;
++
++	skb_reserve(skb, NET_IP_ALIGN);
++
++	return skb;
++}
++
++static int fe_alloc_rx(struct fe_priv *priv)
++{
++	int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
++	int i;
++
++	priv->rx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
++					&priv->rx_phys, GFP_ATOMIC);
++	if (!priv->rx_dma)
++		return -ENOMEM;
++
++	memset(priv->rx_dma, 0, size);
++
++	for (i = 0; i < NUM_DMA_DESC; i++) {
++		priv->rx_skb[i] = fe_alloc_skb(priv);
++		if (!priv->rx_skb[i])
++			return -ENOMEM;
++	}
++
++	for (i = 0; i < NUM_DMA_DESC; i++) {
++		dma_addr_t dma_addr = dma_map_single(&priv->netdev->dev,
++						priv->rx_skb[i]->data,
++						MAX_RX_LENGTH,
++						DMA_FROM_DEVICE);
++		priv->rx_dma[i].rxd1 = (unsigned int) dma_addr;
++
++		if (priv->soc->rx_dma)
++			priv->soc->rx_dma(priv, i, MAX_RX_LENGTH);
++		else
++			priv->rx_dma[i].rxd2 = RX_DMA_LSO;
++	}
++	wmb();
++
++	fe_reg_w32(priv->rx_phys, FE_REG_RX_BASE_PTR0);
++	fe_reg_w32(NUM_DMA_DESC, FE_REG_RX_MAX_CNT0);
++	fe_reg_w32((NUM_DMA_DESC - 1), FE_REG_RX_CALC_IDX0);
++	fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
++
++	return 0;
++}
++
++static int fe_alloc_tx(struct fe_priv *priv)
++{
++	int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
++	int i;
++
++	priv->tx_free_idx = 0;
++
++	priv->tx_dma = dma_alloc_coherent(&priv->netdev->dev, size,
++					&priv->tx_phys, GFP_ATOMIC);
++	if (!priv->tx_dma)
++		return -ENOMEM;
++
++	memset(priv->tx_dma, 0, size);
++
++	for (i = 0; i < NUM_DMA_DESC; i++) {
++		if (priv->soc->tx_dma) {
++			priv->soc->tx_dma(priv, i, 0);
++			continue;
++		}
++
++		priv->tx_dma[i].txd2 = TX_DMA_LSO | TX_DMA_DONE;
++		priv->tx_dma[i].txd4 = TX_DMA_QN(3) | TX_DMA_PN(1);
++	}
++
++	fe_reg_w32(priv->tx_phys, FE_REG_TX_BASE_PTR0);
++	fe_reg_w32(NUM_DMA_DESC, FE_REG_TX_MAX_CNT0);
++	fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
++	fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
++
++	return 0;
++}
++
++static void fe_free_dma(struct fe_priv *priv)
++{
++	int i;
++
++	for (i = 0; i < NUM_DMA_DESC; i++) {
++		if (priv->rx_skb[i]) {
++			dma_unmap_single(&priv->netdev->dev, priv->rx_dma[i].rxd1,
++						MAX_RX_LENGTH, DMA_FROM_DEVICE);
++			dev_kfree_skb_any(priv->rx_skb[i]);
++			priv->rx_skb[i] = NULL;
++		}
++
++		if (priv->tx_skb[i]) {
++			dev_kfree_skb_any(priv->tx_skb[i]);
++			priv->tx_skb[i] = NULL;
++		}
++	}
++
++	if (priv->rx_dma) {
++		int size = NUM_DMA_DESC * sizeof(struct fe_rx_dma);
++		dma_free_coherent(&priv->netdev->dev, size, priv->rx_dma,
++					priv->rx_phys);
++	}
++
++	if (priv->tx_dma) {
++		int size = NUM_DMA_DESC * sizeof(struct fe_tx_dma);
++		dma_free_coherent(&priv->netdev->dev, size, priv->tx_dma,
++					priv->tx_phys);
++	}
++
++	netdev_reset_queue(priv->netdev);
++}
++
++static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++	dma_addr_t mapped_addr;
++	u32 tx_next;
++	u32 tx;
++
++	if (priv->soc->min_pkt_len) {
++		if (skb->len < priv->soc->min_pkt_len) {
++			if (skb_padto(skb, priv->soc->min_pkt_len)) {
++				printk(KERN_ERR
++				       "fe_eth: skb_padto failed\n");
++				kfree_skb(skb);
++				return 0;
++			}
++			skb_put(skb, priv->soc->min_pkt_len - skb->len);
++		}
++	}
++
++	dev->trans_start = jiffies;
++	mapped_addr = dma_map_single(&priv->netdev->dev, skb->data,
++				skb->len, DMA_TO_DEVICE);
++
++	spin_lock(&priv->page_lock);
++
++	tx = fe_reg_r32(FE_REG_TX_CTX_IDX0);
++	tx_next = (tx + 1) % NUM_DMA_DESC;
++
++	if ((priv->tx_skb[tx]) || (priv->tx_skb[tx_next]) ||
++			!(priv->tx_dma[tx].txd2 & TX_DMA_DONE) ||
++			!(priv->tx_dma[tx_next].txd2 & TX_DMA_DONE))
++	{
++		spin_unlock(&priv->page_lock);
++		dev->stats.tx_dropped++;
++		kfree_skb(skb);
++
++		return NETDEV_TX_OK;
++	}
++
++	priv->tx_skb[tx] = skb;
++	priv->tx_dma[tx].txd1 = (unsigned int) mapped_addr;
++	wmb();
++	if (priv->soc->tx_dma)
++		priv->soc->tx_dma(priv, tx, skb->len);
++	else
++		priv->tx_dma[tx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(skb->len);
++
++	if (skb->ip_summed == CHECKSUM_PARTIAL)
++		priv->tx_dma[tx].txd4 |= TX_DMA_CHKSUM;
++	else
++		priv->tx_dma[tx].txd4 &= ~TX_DMA_CHKSUM;
++
++	priv->tx_dma[tx].txd4 &= ~0x80;
++
++	dev->stats.tx_packets++;
++	dev->stats.tx_bytes += skb->len;
++
++	fe_reg_w32(tx_next, FE_REG_TX_CTX_IDX0);
++	netdev_sent_queue(dev, skb->len);
++
++	spin_unlock(&priv->page_lock);
++
++	return NETDEV_TX_OK;
++}
++
++static int fe_poll_rx(struct napi_struct *napi, int budget)
++{
++	struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
++	int idx = fe_reg_r32(FE_REG_RX_CALC_IDX0);
++	int complete = 0;
++	int rx = 0;
++
++	while ((rx < budget) && !complete) {
++		idx = (idx + 1) % NUM_DMA_DESC;
++
++		if (priv->rx_dma[idx].rxd2 & RX_DMA_DONE) {
++			struct sk_buff *new_skb = fe_alloc_skb(priv);
++
++			if (new_skb) {
++				int pktlen = RX_DMA_PLEN0(priv->rx_dma[idx].rxd2);
++				dma_addr_t dma_addr;
++
++				dma_unmap_single(&priv->netdev->dev, priv->rx_dma[idx].rxd1,
++						MAX_RX_LENGTH, DMA_FROM_DEVICE);
++
++				skb_put(priv->rx_skb[idx], pktlen);
++				priv->rx_skb[idx]->dev = priv->netdev;
++				priv->rx_skb[idx]->protocol = eth_type_trans(priv->rx_skb[idx], priv->netdev);
++				if (priv->rx_dma[idx].rxd4 & priv->soc->checksum_bit)
++					priv->rx_skb[idx]->ip_summed = CHECKSUM_UNNECESSARY;
++				else
++					priv->rx_skb[idx]->ip_summed = CHECKSUM_NONE;
++				priv->netdev->stats.rx_packets++;
++				priv->netdev->stats.rx_bytes += pktlen;
++				netif_receive_skb(priv->rx_skb[idx]);
++
++				priv->rx_skb[idx] = new_skb;
++
++				dma_addr = dma_map_single(&priv->netdev->dev,
++						  new_skb->data,
++						  MAX_RX_LENGTH,
++						  DMA_FROM_DEVICE);
++				priv->rx_dma[idx].rxd1 = (unsigned int) dma_addr;
++				wmb();
++			} else {
++				priv->netdev->stats.rx_dropped++;
++			}
++
++			if (priv->soc->rx_dma)
++				priv->soc->rx_dma(priv, idx, MAX_RX_LENGTH);
++			else
++				priv->rx_dma[idx].rxd2 = RX_DMA_LSO;
++			fe_reg_w32(idx, FE_REG_RX_CALC_IDX0);
++
++			rx++;
++		} else {
++			complete = 1;
++		}
++	}
++
++	if (complete) {
++		napi_complete(&priv->rx_napi);
++		fe_int_enable(priv->soc->rx_dly_int);
++	}
++
++	return rx;
++}
++
++static void fe_tx_housekeeping(unsigned long ptr)
++{
++	struct net_device *dev = (struct net_device*)ptr;
++	struct fe_priv *priv = netdev_priv(dev);
++	unsigned int bytes_compl = 0;
++	unsigned int pkts_compl = 0;
++
++	spin_lock(&priv->page_lock);
++	while (1) {
++		struct fe_tx_dma *txd;
++
++		txd = &priv->tx_dma[priv->tx_free_idx];
++
++		if (!(txd->txd2 & TX_DMA_DONE) || !(priv->tx_skb[priv->tx_free_idx]))
++			break;
++
++		bytes_compl += priv->tx_skb[priv->tx_free_idx]->len;
++		pkts_compl++;
++
++		dev_kfree_skb_irq(priv->tx_skb[priv->tx_free_idx]);
++		priv->tx_skb[priv->tx_free_idx] = NULL;
++		priv->tx_free_idx++;
++		if (priv->tx_free_idx >= NUM_DMA_DESC)
++			priv->tx_free_idx = 0;
++	}
++
++	netdev_completed_queue(priv->netdev, pkts_compl, bytes_compl);
++        spin_unlock(&priv->page_lock);
++
++	fe_int_enable(priv->soc->tx_dly_int);
++}
++
++static void fe_tx_timeout(struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++
++        tasklet_schedule(&priv->tx_tasklet);
++	priv->netdev->stats.tx_errors++;
++	netdev_err(dev, "transmit timed out, waking up the queue\n");
++	netif_wake_queue(dev);
++}
++
++static irqreturn_t fe_handle_irq(int irq, void *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++	unsigned int status;
++	unsigned int mask;
++
++	status = fe_reg_r32(FE_REG_FE_INT_STATUS);
++	mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
++
++	if (!(status & mask))
++		return IRQ_NONE;
++
++	if (status & priv->soc->rx_dly_int) {
++		fe_int_disable(priv->soc->rx_dly_int);
++		napi_schedule(&priv->rx_napi);
++	}
++
++	if (status & priv->soc->tx_dly_int) {
++		fe_int_disable(priv->soc->tx_dly_int);
++		tasklet_schedule(&priv->tx_tasklet);
++	}
++
++	fe_reg_w32(status, FE_REG_FE_INT_STATUS);
++
++	return IRQ_HANDLED;
++}
++
++static int fe_hw_init(struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++	int err;
++
++	err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
++				dev_name(priv->device), dev);
++	if (err)
++		return err;
++
++	err = fe_alloc_rx(priv);
++	if (!err)
++		err = fe_alloc_tx(priv);
++	if (err)
++		return err;
++
++	if (priv->soc->set_mac)
++		priv->soc->set_mac(priv, dev->dev_addr);
++	else
++		fe_hw_set_macaddr(priv, dev->dev_addr);
++
++	fe_reg_w32(FE_DELAY_INIT, FE_REG_DLY_INT_CFG);
++
++	fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
++
++	tasklet_init(&priv->tx_tasklet, fe_tx_housekeeping, (unsigned long)dev);
++
++	if (priv->soc->fwd_config) {
++		priv->soc->fwd_config(priv);
++	} else {
++		unsigned long sysclk = priv->sysclk;
++
++		if (!sysclk) {
++			netdev_err(dev, "unable to get clock\n");
++			return -EINVAL;
++		}
++
++		sysclk /= FE_US_CYC_CNT_DIVISOR;
++		sysclk <<= FE_US_CYC_CNT_SHIFT;
++
++		fe_w32((fe_r32(FE_FE_GLO_CFG) &
++			~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
++			FE_FE_GLO_CFG);
++
++		fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~0xffff, FE_GDMA1_FWD_CFG);
++		fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN | FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
++			FE_GDMA1_FWD_CFG);
++		fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN | FE_TCS_GEN_EN | FE_UCS_GEN_EN),
++			FE_CDMA_CSG_CFG);
++		fe_w32(FE_PSE_FQFC_CFG_INIT, FE_PSE_FQ_CFG);
++	}
++
++	fe_w32(1, FE_FE_RST_GL);
++	fe_w32(0, FE_FE_RST_GL);
++
++	return 0;
++}
++
++static int fe_open(struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++	unsigned long flags;
++	u32 val;
++
++	spin_lock_irqsave(&priv->page_lock, flags);
++	napi_enable(&priv->rx_napi);
++
++	val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
++	val |= priv->soc->pdma_glo_cfg;
++	fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
++
++	spin_unlock_irqrestore(&priv->page_lock, flags);
++
++	if (priv->phy)
++		priv->phy->start(priv);
++
++	if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
++		netif_carrier_on(dev);
++
++	netif_start_queue(dev);
++	fe_int_enable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
++
++	return 0;
++}
++
++static int fe_stop(struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++	unsigned long flags;
++
++	fe_int_disable(priv->soc->tx_dly_int | priv->soc->rx_dly_int);
++
++	netif_stop_queue(dev);
++
++	if (priv->phy)
++		priv->phy->stop(priv);
++
++	spin_lock_irqsave(&priv->page_lock, flags);
++	napi_disable(&priv->rx_napi);
++
++	fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
++		     ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
++		     FE_REG_PDMA_GLO_CFG);
++	spin_unlock_irqrestore(&priv->page_lock, flags);
++
++	return 0;
++}
++
++static int __init fe_init(struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++	struct device_node *port;
++	int err;
++
++	BUG_ON(!priv->soc->reset_fe);
++	priv->soc->reset_fe();
++
++	if (priv->soc->switch_init)
++		priv->soc->switch_init(priv);
++
++	net_srandom(jiffies);
++	memcpy(dev->dev_addr, priv->soc->mac, ETH_ALEN);
++	of_get_mac_address_mtd(priv->device->of_node, dev->dev_addr);
++
++	err = fe_mdio_init(priv);
++	if (err)
++		return err;
++
++	if (priv->phy) {
++		err = priv->phy->connect(priv);
++		if (err)
++			goto err_mdio_cleanup;
++	}
++
++	if (priv->soc->port_init)
++		for_each_child_of_node(priv->device->of_node, port)
++			if (of_device_is_compatible(port, "ralink,eth-port"))
++				priv->soc->port_init(priv, port);
++
++	err = fe_hw_init(dev);
++	if (err)
++		goto err_phy_disconnect;
++
++	return 0;
++
++err_phy_disconnect:
++	if (priv->phy)
++		priv->phy->disconnect(priv);
++err_mdio_cleanup:
++	fe_mdio_cleanup(priv);
++
++	return err;
++}
++
++static void fe_uninit(struct net_device *dev)
++{
++	struct fe_priv *priv = netdev_priv(dev);
++
++	tasklet_kill(&priv->tx_tasklet);
++
++	if (priv->phy)
++		priv->phy->disconnect(priv);
++	fe_mdio_cleanup(priv);
++
++	fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
++	free_irq(dev->irq, dev);
++
++	fe_free_dma(priv);
++}
++
++static const struct net_device_ops fe_netdev_ops = {
++	.ndo_init		= fe_init,
++	.ndo_uninit		= fe_uninit,
++	.ndo_open		= fe_open,
++	.ndo_stop		= fe_stop,
++	.ndo_start_xmit		= fe_start_xmit,
++	.ndo_tx_timeout		= fe_tx_timeout,
++	.ndo_set_mac_address	= fe_set_mac_address,
++	.ndo_change_mtu		= eth_change_mtu,
++	.ndo_validate_addr	= eth_validate_addr,
++};
++
++static int fe_probe(struct platform_device *pdev)
++{
++	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	const struct of_device_id *match;
++	struct fe_soc_data *soc = NULL;
++	struct net_device *netdev;
++	struct fe_priv *priv;
++	struct clk *sysclk;
++	int err;
++
++	match = of_match_device(of_fe_match, &pdev->dev);
++	soc = (struct fe_soc_data *) match->data;
++	if (soc->reg_table)
++		fe_reg_table = soc->reg_table;
++
++	fe_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (!fe_base)
++		return -ENOMEM;
++
++	netdev = alloc_etherdev(sizeof(struct fe_priv));
++	if (!netdev) {
++		dev_err(&pdev->dev, "alloc_etherdev failed\n");
++		return -ENOMEM;
++	}
++
++	strcpy(netdev->name, "eth%d");
++	netdev->netdev_ops = &fe_netdev_ops;
++	netdev->base_addr = (unsigned long) fe_base;
++	netdev->watchdog_timeo = TX_TIMEOUT;
++	netdev->features |= NETIF_F_IP_CSUM | NETIF_F_RXCSUM;
++
++	netdev->irq = platform_get_irq(pdev, 0);
++	if (netdev->irq < 0) {
++		dev_err(&pdev->dev, "no IRQ resource found\n");
++		kfree(netdev);
++		return -ENXIO;
++	}
++
++	priv = netdev_priv(netdev);
++	memset(priv, 0, sizeof(struct fe_priv));
++	spin_lock_init(&priv->page_lock);
++
++	sysclk = devm_clk_get(&pdev->dev, NULL);
++	if (!IS_ERR(sysclk))
++		priv->sysclk = clk_get_rate(sysclk);
++
++	priv->netdev = netdev;
++	priv->device = &pdev->dev;
++	priv->soc = soc;
++
++	err = register_netdev(netdev);
++	if (err) {
++		dev_err(&pdev->dev, "error bringing up device\n");
++		kfree(netdev);
++		return err;
++	}
++	netif_napi_add(netdev, &priv->rx_napi, fe_poll_rx, 32);
++
++	platform_set_drvdata(pdev, netdev);
++
++	netdev_info(netdev, "done loading\n");
++
++	return 0;
++}
++
++static int fe_remove(struct platform_device *pdev)
++{
++        struct net_device *dev = platform_get_drvdata(pdev);
++	struct fe_priv *priv = netdev_priv(dev);
++
++	netif_stop_queue(dev);
++	netif_napi_del(&priv->rx_napi);
++
++	unregister_netdev(dev);
++	free_netdev(dev);
++
++	return 0;
++}
++
++static struct platform_driver fe_driver = {
++	.probe = fe_probe,
++	.remove = fe_remove,
++	.driver = {
++		.name = "ralink_soc_eth",
++		.owner = THIS_MODULE,
++		.of_match_table = of_fe_match,
++	},
++};
++
++static int __init init_rtfe(void)
++{
++	int ret;
++
++	ret = rtesw_init();
++	if (ret)
++		return ret;
++
++	ret = platform_driver_register(&fe_driver);
++	if (ret)
++		rtesw_exit();
++
++	return ret;
++}
++
++static void __exit exit_rtfe(void)
++{
++	platform_driver_unregister(&fe_driver);
++	rtesw_exit();
++}
++
++module_init(init_rtfe);
++module_exit(exit_rtfe);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
++MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
+diff --git a/drivers/net/ethernet/ralink/ralink_soc_eth.h b/drivers/net/ethernet/ralink/ralink_soc_eth.h
+new file mode 100644
+index 0000000..85bc881
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/ralink_soc_eth.h
+@@ -0,0 +1,374 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   based on Ralink SDK3.3
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#ifndef FE_ETH_H
++#define FE_ETH_H
++
++#include <linux/mii.h>
++#include <linux/interrupt.h>
++#include <linux/netdevice.h>
++#include <linux/dma-mapping.h>
++#include <linux/phy.h>
++
++
++enum fe_reg {
++	FE_REG_PDMA_GLO_CFG = 0,
++	FE_REG_PDMA_RST_CFG,
++	FE_REG_DLY_INT_CFG,
++	FE_REG_TX_BASE_PTR0,
++	FE_REG_TX_MAX_CNT0,
++	FE_REG_TX_CTX_IDX0,
++	FE_REG_RX_BASE_PTR0,
++	FE_REG_RX_MAX_CNT0,
++	FE_REG_RX_CALC_IDX0,
++	FE_REG_FE_INT_ENABLE,
++	FE_REG_FE_INT_STATUS,
++	FE_REG_FE_DMA_VID_BASE,
++	FE_REG_COUNT
++};
++
++#define NUM_DMA_DESC		0x100
++
++#define FE_DELAY_EN_INT		0x80
++#define FE_DELAY_MAX_INT	0x04
++#define FE_DELAY_MAX_TOUT	0x04
++#define FE_DELAY_CHAN		(((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | FE_DELAY_MAX_TOUT)
++#define FE_DELAY_INIT		((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
++#define FE_PSE_FQFC_CFG_INIT	0x80504000
++
++/* interrupt bits */
++#define FE_CNT_PPE_AF		BIT(31)
++#define FE_CNT_GDM_AF		BIT(29)
++#define FE_PSE_P2_FC		BIT(26)
++#define FE_PSE_BUF_DROP		BIT(24)
++#define FE_GDM_OTHER_DROP	BIT(23)
++#define FE_PSE_P1_FC		BIT(22)
++#define FE_PSE_P0_FC		BIT(21)
++#define FE_PSE_FQ_EMPTY		BIT(20)
++#define FE_GE1_STA_CHG		BIT(18)
++#define FE_TX_COHERENT		BIT(17)
++#define FE_RX_COHERENT		BIT(16)
++#define FE_TX_DONE_INT3		BIT(11)
++#define FE_TX_DONE_INT2		BIT(10)
++#define FE_TX_DONE_INT1		BIT(9)
++#define FE_TX_DONE_INT0		BIT(8)
++#define FE_RX_DONE_INT0		BIT(2)
++#define FE_TX_DLY_INT		BIT(1)
++#define FE_RX_DLY_INT		BIT(0)
++
++#define RT5350_RX_DLY_INT	BIT(30)
++#define RT5350_TX_DLY_INT	BIT(28)
++
++/* registers */
++#define FE_FE_OFFSET		0x0000
++#define FE_GDMA_OFFSET		0x0020
++#define FE_PSE_OFFSET		0x0040
++#define FE_GDMA2_OFFSET		0x0060
++#define FE_CDMA_OFFSET		0x0080
++#define FE_DMA_VID0		0x00a8
++#define FE_PDMA_OFFSET		0x0100
++#define FE_PPE_OFFSET		0x0200
++#define FE_CMTABLE_OFFSET	0x0400
++#define FE_POLICYTABLE_OFFSET	0x1000
++
++#define RT5350_PDMA_OFFSET	0x0800
++#define RT5350_SDM_OFFSET	0x0c00
++
++#define FE_MDIO_ACCESS		(FE_FE_OFFSET + 0x00)
++#define FE_MDIO_CFG		(FE_FE_OFFSET + 0x04)
++#define FE_FE_GLO_CFG		(FE_FE_OFFSET + 0x08)
++#define FE_FE_RST_GL		(FE_FE_OFFSET + 0x0C)
++#define FE_FE_INT_STATUS	(FE_FE_OFFSET + 0x10)
++#define FE_FE_INT_ENABLE	(FE_FE_OFFSET + 0x14)
++#define FE_MDIO_CFG2		(FE_FE_OFFSET + 0x18)
++#define FE_FOC_TS_T		(FE_FE_OFFSET + 0x1C)
++
++#define	FE_GDMA1_FWD_CFG	(FE_GDMA_OFFSET + 0x00)
++#define FE_GDMA1_SCH_CFG	(FE_GDMA_OFFSET + 0x04)
++#define FE_GDMA1_SHPR_CFG	(FE_GDMA_OFFSET + 0x08)
++#define FE_GDMA1_MAC_ADRL	(FE_GDMA_OFFSET + 0x0C)
++#define FE_GDMA1_MAC_ADRH	(FE_GDMA_OFFSET + 0x10)
++
++#define	FE_GDMA2_FWD_CFG	(FE_GDMA2_OFFSET + 0x00)
++#define FE_GDMA2_SCH_CFG	(FE_GDMA2_OFFSET + 0x04)
++#define FE_GDMA2_SHPR_CFG	(FE_GDMA2_OFFSET + 0x08)
++#define FE_GDMA2_MAC_ADRL	(FE_GDMA2_OFFSET + 0x0C)
++#define FE_GDMA2_MAC_ADRH	(FE_GDMA2_OFFSET + 0x10)
++
++#define FE_PSE_FQ_CFG		(FE_PSE_OFFSET + 0x00)
++#define FE_CDMA_FC_CFG		(FE_PSE_OFFSET + 0x04)
++#define FE_GDMA1_FC_CFG		(FE_PSE_OFFSET + 0x08)
++#define FE_GDMA2_FC_CFG		(FE_PSE_OFFSET + 0x0C)
++
++#define FE_CDMA_CSG_CFG		(FE_CDMA_OFFSET + 0x00)
++#define FE_CDMA_SCH_CFG		(FE_CDMA_OFFSET + 0x04)
++
++#define MT7620A_GDMA_OFFSET		0x0600
++#define	MT7620A_GDMA1_FWD_CFG		(MT7620A_GDMA_OFFSET + 0x00)
++#define MT7620A_FE_GDMA1_SCH_CFG	(MT7620A_GDMA_OFFSET + 0x04)
++#define MT7620A_FE_GDMA1_SHPR_CFG	(MT7620A_GDMA_OFFSET + 0x08)
++#define MT7620A_FE_GDMA1_MAC_ADRL	(MT7620A_GDMA_OFFSET + 0x0C)
++#define MT7620A_FE_GDMA1_MAC_ADRH	(MT7620A_GDMA_OFFSET + 0x10)
++
++#define RT5350_TX_BASE_PTR0	(RT5350_PDMA_OFFSET + 0x00)
++#define RT5350_TX_MAX_CNT0	(RT5350_PDMA_OFFSET + 0x04)
++#define RT5350_TX_CTX_IDX0	(RT5350_PDMA_OFFSET + 0x08)
++#define RT5350_TX_DTX_IDX0	(RT5350_PDMA_OFFSET + 0x0C)
++#define RT5350_TX_BASE_PTR1	(RT5350_PDMA_OFFSET + 0x10)
++#define RT5350_TX_MAX_CNT1	(RT5350_PDMA_OFFSET + 0x14)
++#define RT5350_TX_CTX_IDX1	(RT5350_PDMA_OFFSET + 0x18)
++#define RT5350_TX_DTX_IDX1	(RT5350_PDMA_OFFSET + 0x1C)
++#define RT5350_TX_BASE_PTR2	(RT5350_PDMA_OFFSET + 0x20)
++#define RT5350_TX_MAX_CNT2	(RT5350_PDMA_OFFSET + 0x24)
++#define RT5350_TX_CTX_IDX2	(RT5350_PDMA_OFFSET + 0x28)
++#define RT5350_TX_DTX_IDX2	(RT5350_PDMA_OFFSET + 0x2C)
++#define RT5350_TX_BASE_PTR3	(RT5350_PDMA_OFFSET + 0x30)
++#define RT5350_TX_MAX_CNT3	(RT5350_PDMA_OFFSET + 0x34)
++#define RT5350_TX_CTX_IDX3	(RT5350_PDMA_OFFSET + 0x38)
++#define RT5350_TX_DTX_IDX3	(RT5350_PDMA_OFFSET + 0x3C)
++#define RT5350_RX_BASE_PTR0	(RT5350_PDMA_OFFSET + 0x100)
++#define RT5350_RX_MAX_CNT0	(RT5350_PDMA_OFFSET + 0x104)
++#define RT5350_RX_CALC_IDX0	(RT5350_PDMA_OFFSET + 0x108)
++#define RT5350_RX_DRX_IDX0	(RT5350_PDMA_OFFSET + 0x10C)
++#define RT5350_RX_BASE_PTR1	(RT5350_PDMA_OFFSET + 0x110)
++#define RT5350_RX_MAX_CNT1	(RT5350_PDMA_OFFSET + 0x114)
++#define RT5350_RX_CALC_IDX1	(RT5350_PDMA_OFFSET + 0x118)
++#define RT5350_RX_DRX_IDX1	(RT5350_PDMA_OFFSET + 0x11C)
++#define RT5350_PDMA_GLO_CFG	(RT5350_PDMA_OFFSET + 0x204)
++#define RT5350_PDMA_RST_CFG	(RT5350_PDMA_OFFSET + 0x208)
++#define RT5350_DLY_INT_CFG	(RT5350_PDMA_OFFSET + 0x20c)
++#define RT5350_FE_INT_STATUS	(RT5350_PDMA_OFFSET + 0x220)
++#define RT5350_FE_INT_ENABLE	(RT5350_PDMA_OFFSET + 0x228)
++#define RT5350_PDMA_SCH_CFG	(RT5350_PDMA_OFFSET + 0x280)
++
++#define FE_PDMA_GLO_CFG		(FE_PDMA_OFFSET + 0x00)
++#define FE_PDMA_RST_CFG		(FE_PDMA_OFFSET + 0x04)
++#define FE_PDMA_SCH_CFG		(FE_PDMA_OFFSET + 0x08)
++#define FE_DLY_INT_CFG		(FE_PDMA_OFFSET + 0x0C)
++#define FE_TX_BASE_PTR0		(FE_PDMA_OFFSET + 0x10)
++#define FE_TX_MAX_CNT0		(FE_PDMA_OFFSET + 0x14)
++#define FE_TX_CTX_IDX0		(FE_PDMA_OFFSET + 0x18)
++#define FE_TX_DTX_IDX0		(FE_PDMA_OFFSET + 0x1C)
++#define FE_TX_BASE_PTR1		(FE_PDMA_OFFSET + 0x20)
++#define FE_TX_MAX_CNT1		(FE_PDMA_OFFSET + 0x24)
++#define FE_TX_CTX_IDX1		(FE_PDMA_OFFSET + 0x28)
++#define FE_TX_DTX_IDX1		(FE_PDMA_OFFSET + 0x2C)
++#define FE_RX_BASE_PTR0		(FE_PDMA_OFFSET + 0x30)
++#define FE_RX_MAX_CNT0		(FE_PDMA_OFFSET + 0x34)
++#define FE_RX_CALC_IDX0		(FE_PDMA_OFFSET + 0x38)
++#define FE_RX_DRX_IDX0		(FE_PDMA_OFFSET + 0x3C)
++#define FE_TX_BASE_PTR2		(FE_PDMA_OFFSET + 0x40)
++#define FE_TX_MAX_CNT2		(FE_PDMA_OFFSET + 0x44)
++#define FE_TX_CTX_IDX2		(FE_PDMA_OFFSET + 0x48)
++#define FE_TX_DTX_IDX2		(FE_PDMA_OFFSET + 0x4C)
++#define FE_TX_BASE_PTR3		(FE_PDMA_OFFSET + 0x50)
++#define FE_TX_MAX_CNT3		(FE_PDMA_OFFSET + 0x54)
++#define FE_TX_CTX_IDX3		(FE_PDMA_OFFSET + 0x58)
++#define FE_TX_DTX_IDX3		(FE_PDMA_OFFSET + 0x5C)
++#define FE_RX_BASE_PTR1		(FE_PDMA_OFFSET + 0x60)
++#define FE_RX_MAX_CNT1		(FE_PDMA_OFFSET + 0x64)
++#define FE_RX_CALC_IDX1		(FE_PDMA_OFFSET + 0x68)
++#define FE_RX_DRX_IDX1		(FE_PDMA_OFFSET + 0x6C)
++
++#define RT5350_SDM_CFG		(RT5350_SDM_OFFSET + 0x00)  //Switch DMA configuration
++#define RT5350_SDM_RRING	(RT5350_SDM_OFFSET + 0x04)  //Switch DMA Rx Ring
++#define RT5350_SDM_TRING	(RT5350_SDM_OFFSET + 0x08)  //Switch DMA Tx Ring
++#define RT5350_SDM_MAC_ADRL	(RT5350_SDM_OFFSET + 0x0C)  //Switch MAC address LSB
++#define RT5350_SDM_MAC_ADRH	(RT5350_SDM_OFFSET + 0x10)  //Switch MAC Address MSB
++#define RT5350_SDM_TPCNT	(RT5350_SDM_OFFSET + 0x100) //Switch DMA Tx packet count
++#define RT5350_SDM_TBCNT	(RT5350_SDM_OFFSET + 0x104) //Switch DMA Tx byte count
++#define RT5350_SDM_RPCNT	(RT5350_SDM_OFFSET + 0x108) //Switch DMA rx packet count
++#define RT5350_SDM_RBCNT	(RT5350_SDM_OFFSET + 0x10C) //Switch DMA rx byte count
++#define RT5350_SDM_CS_ERR	(RT5350_SDM_OFFSET + 0x110) //Switch DMA rx checksum error count
++
++#define RT5350_SDM_ICS_EN	BIT(16)
++#define RT5350_SDM_TCS_EN	BIT(17)
++#define RT5350_SDM_UCS_EN	BIT(18)
++
++
++/* MDIO_CFG register bits */
++#define FE_MDIO_CFG_AUTO_POLL_EN	BIT(29)
++#define FE_MDIO_CFG_GP1_BP_EN		BIT(16)
++#define FE_MDIO_CFG_GP1_FRC_EN		BIT(15)
++#define FE_MDIO_CFG_GP1_SPEED_10	(0 << 13)
++#define FE_MDIO_CFG_GP1_SPEED_100	(1 << 13)
++#define FE_MDIO_CFG_GP1_SPEED_1000	(2 << 13)
++#define FE_MDIO_CFG_GP1_DUPLEX		BIT(12)
++#define FE_MDIO_CFG_GP1_FC_TX		BIT(11)
++#define FE_MDIO_CFG_GP1_FC_RX		BIT(10)
++#define FE_MDIO_CFG_GP1_LNK_DWN		BIT(9)
++#define FE_MDIO_CFG_GP1_AN_FAIL		BIT(8)
++#define FE_MDIO_CFG_MDC_CLK_DIV_1	(0 << 6)
++#define FE_MDIO_CFG_MDC_CLK_DIV_2	(1 << 6)
++#define FE_MDIO_CFG_MDC_CLK_DIV_4	(2 << 6)
++#define FE_MDIO_CFG_MDC_CLK_DIV_8	(3 << 6)
++#define FE_MDIO_CFG_TURBO_MII_FREQ	BIT(5)
++#define FE_MDIO_CFG_TURBO_MII_MODE	BIT(4)
++#define FE_MDIO_CFG_RX_CLK_SKEW_0	(0 << 2)
++#define FE_MDIO_CFG_RX_CLK_SKEW_200	(1 << 2)
++#define FE_MDIO_CFG_RX_CLK_SKEW_400	(2 << 2)
++#define FE_MDIO_CFG_RX_CLK_SKEW_INV	(3 << 2)
++#define FE_MDIO_CFG_TX_CLK_SKEW_0	0
++#define FE_MDIO_CFG_TX_CLK_SKEW_200	1
++#define FE_MDIO_CFG_TX_CLK_SKEW_400	2
++#define FE_MDIO_CFG_TX_CLK_SKEW_INV	3
++
++/* uni-cast port */
++#define FE_GDM1_ICS_EN		BIT(22)
++#define FE_GDM1_TCS_EN		BIT(21)
++#define FE_GDM1_UCS_EN		BIT(20)
++#define FE_GDM1_JMB_EN		BIT(19)
++#define FE_GDM1_STRPCRC		BIT(16)
++#define FE_GDM1_UFRC_P_CPU	(0 << 12)
++#define FE_GDM1_UFRC_P_GDMA1	(1 << 12)
++#define FE_GDM1_UFRC_P_PPE	(6 << 12)
++
++/* checksums */
++#define FE_ICS_GEN_EN		BIT(2)
++#define FE_UCS_GEN_EN		BIT(1)
++#define FE_TCS_GEN_EN		BIT(0)
++
++/* dma ring */
++#define FE_PST_DRX_IDX0		BIT(16)
++#define FE_PST_DTX_IDX3		BIT(3)
++#define FE_PST_DTX_IDX2		BIT(2)
++#define FE_PST_DTX_IDX1		BIT(1)
++#define FE_PST_DTX_IDX0		BIT(0)
++
++#define FE_TX_WB_DDONE		BIT(6)
++#define FE_RX_DMA_BUSY		BIT(3)
++#define FE_TX_DMA_BUSY		BIT(1)
++#define FE_RX_DMA_EN		BIT(2)
++#define FE_TX_DMA_EN		BIT(0)
++
++#define FE_PDMA_SIZE_4DWORDS	(0 << 4)
++#define FE_PDMA_SIZE_8DWORDS	(1 << 4)
++#define FE_PDMA_SIZE_16DWORDS	(2 << 4)
++
++#define FE_US_CYC_CNT_MASK	0xff
++#define FE_US_CYC_CNT_SHIFT	0x8
++#define FE_US_CYC_CNT_DIVISOR	1000000
++
++#define RX_DMA_PLEN0(_x)	(((_x) >> 16) & 0x3fff)
++#define RX_DMA_LSO		BIT(30)
++#define RX_DMA_DONE		BIT(31)
++#define RX_DMA_L4VALID		BIT(30)
++
++struct fe_rx_dma {
++	unsigned int rxd1;
++	unsigned int rxd2;
++	unsigned int rxd3;
++	unsigned int rxd4;
++} __packed __aligned(4);
++
++#define TX_DMA_PLEN0_MASK	((0x3fff) << 16)
++#define TX_DMA_PLEN0(_x)	(((_x) & 0x3fff) << 16)
++#define TX_DMA_LSO		BIT(30)
++#define TX_DMA_DONE		BIT(31)
++#define TX_DMA_QN(_x)		((_x) << 16)
++#define TX_DMA_PN(_x)		((_x) << 24)
++#define TX_DMA_QN_MASK		TX_DMA_QN(0x7)
++#define TX_DMA_PN_MASK		TX_DMA_PN(0x7)
++#define TX_DMA_CHKSUM		(0x7 << 29)
++
++struct fe_tx_dma {
++	unsigned int txd1;
++	unsigned int txd2;
++	unsigned int txd3;
++	unsigned int txd4;
++} __packed __aligned(4);
++
++struct fe_priv;
++
++struct fe_phy {
++	struct phy_device	*phy[8];
++	struct device_node	*phy_node[8];
++	const __be32		*phy_fixed[8];
++	int			duplex[8];
++	int			speed[8];
++	int			tx_fc[8];
++	int			rx_fc[8];
++	spinlock_t		lock;
++
++	int (*connect)(struct fe_priv *priv);
++	void (*disconnect)(struct fe_priv *priv);
++	void (*start)(struct fe_priv *priv);
++	void (*stop)(struct fe_priv *priv);
++};
++
++struct fe_soc_data
++{
++	unsigned char mac[6];
++	const u32 *reg_table;
++
++	void (*reset_fe)(void);
++	void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
++	void (*fwd_config)(struct fe_priv *priv);
++	void (*tx_dma)(struct fe_priv *priv, int idx, int len);
++	void (*rx_dma)(struct fe_priv *priv, int idx, int len);
++	int (*switch_init)(struct fe_priv *priv);
++	void (*port_init)(struct fe_priv *priv, struct device_node *port);
++	int (*has_carrier)(struct fe_priv *priv);
++	int (*mdio_init)(struct fe_priv *priv);
++	void (*mdio_cleanup)(struct fe_priv *priv);
++	int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
++	int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
++	void (*mdio_adjust_link)(struct fe_priv *priv, int port);
++
++	void *swpriv;
++	u32 pdma_glo_cfg;
++	u32 rx_dly_int;
++	u32 tx_dly_int;
++	u32 checksum_bit;
++
++	int min_pkt_len;
++};
++
++struct fe_priv
++{
++	spinlock_t			page_lock;
++
++	struct fe_soc_data		*soc;
++	struct net_device		*netdev;
++	struct device			*device;
++	unsigned long			sysclk;
++
++	struct fe_rx_dma		*rx_dma;
++        struct napi_struct		rx_napi;
++	struct sk_buff			*rx_skb[NUM_DMA_DESC];
++	dma_addr_t			rx_phys;
++
++	struct fe_tx_dma		*tx_dma;
++	struct tasklet_struct		tx_tasklet;
++	struct sk_buff			*tx_skb[NUM_DMA_DESC];
++	dma_addr_t			tx_phys;
++	unsigned int			tx_free_idx;
++
++	struct fe_phy			*phy;
++	struct mii_bus			*mii_bus;
++	int				mii_irq[PHY_MAX_ADDR];
++
++	int				link[8];
++};
++
++extern const struct of_device_id of_fe_match[];
++
++void fe_w32(u32 val, unsigned reg);
++u32 fe_r32(unsigned reg);
++
++#endif /* FE_ETH_H */
+diff --git a/drivers/net/ethernet/ralink/soc_mt7620.c b/drivers/net/ethernet/ralink/soc_mt7620.c
+new file mode 100644
+index 0000000..55e303f
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/soc_mt7620.c
+@@ -0,0 +1,111 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "ralink_soc_eth.h"
++#include "gsw_mt7620a.h"
++
++#define MT7620A_CDMA_CSG_CFG	0x400
++#define MT7620_DMA_VID		(MT7620A_CDMA_CSG_CFG | 0x30)
++#define MT7620A_DMA_2B_OFFSET	BIT(31)
++#define MT7620A_RESET_FE	BIT(21)
++#define MT7620A_RESET_ESW	BIT(23)
++#define MT7620_L4_VALID		BIT(23)
++
++#define SYSC_REG_RESET_CTRL     0x34
++#define MAX_RX_LENGTH           1536
++
++#define CDMA_ICS_EN		BIT(2)
++#define CDMA_UCS_EN		BIT(1)
++#define CDMA_TCS_EN		BIT(0)
++
++#define GDMA_ICS_EN		BIT(22)
++#define GDMA_TCS_EN		BIT(21)
++#define GDMA_UCS_EN		BIT(20)
++
++static const u32 rt5350_reg_table[FE_REG_COUNT] = {
++	[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
++	[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
++	[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
++	[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
++	[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
++	[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
++	[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
++	[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
++	[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
++	[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
++	[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
++	[FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
++};
++
++static void mt7620_fe_reset(void)
++{
++	rt_sysc_w32(MT7620A_RESET_FE | MT7620A_RESET_ESW, SYSC_REG_RESET_CTRL);
++	rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
++}
++
++static void mt7620_fwd_config(struct fe_priv *priv)
++{
++	fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
++	fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN | GDMA_TCS_EN | GDMA_UCS_EN), MT7620A_GDMA1_FWD_CFG);
++	fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN | CDMA_UCS_EN | CDMA_TCS_EN), MT7620A_CDMA_CSG_CFG);
++}
++
++static void mt7620_tx_dma(struct fe_priv *priv, int idx, int len)
++{
++	if (len)
++		priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_PLEN0(len);
++	else
++		priv->tx_dma[idx].txd2 = TX_DMA_LSO | TX_DMA_DONE;
++}
++
++static void mt7620_rx_dma(struct fe_priv *priv, int idx, int len)
++{
++	priv->rx_dma[idx].rxd2 = RX_DMA_PLEN0(len);
++}
++
++static struct fe_soc_data mt7620_data = {
++	.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++	.reset_fe = mt7620_fe_reset,
++	.set_mac = mt7620_set_mac,
++	.fwd_config = mt7620_fwd_config,
++	.tx_dma = mt7620_tx_dma,
++	.rx_dma = mt7620_rx_dma,
++	.switch_init = mt7620_gsw_probe,
++	.port_init = mt7620_port_init,
++	.min_pkt_len = 0,
++	.reg_table = rt5350_reg_table,
++	.pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS | MT7620A_DMA_2B_OFFSET,
++	.rx_dly_int = RT5350_RX_DLY_INT,
++	.tx_dly_int = RT5350_TX_DLY_INT,
++	.checksum_bit = MT7620_L4_VALID,
++	.has_carrier = mt7620a_has_carrier,
++	.mdio_read = mt7620_mdio_read,
++	.mdio_write = mt7620_mdio_write,
++	.mdio_adjust_link = mt7620_mdio_link_adjust,
++};
++
++const struct of_device_id of_fe_match[] = {
++	{ .compatible = "ralink,mt7620a-eth", .data = &mt7620_data },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, of_fe_match);
+diff --git a/drivers/net/ethernet/ralink/soc_rt2880.c b/drivers/net/ethernet/ralink/soc_rt2880.c
+new file mode 100644
+index 0000000..1110947
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/soc_rt2880.c
+@@ -0,0 +1,51 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "ralink_soc_eth.h"
++#include "mdio_rt2880.h"
++
++#define SYSC_REG_RESET_CTRL		0x034
++#define RT2880_RESET_FE			BIT(18)
++
++void rt2880_fe_reset(void)
++{
++	rt_sysc_w32(RT2880_RESET_FE, SYSC_REG_RESET_CTRL);
++}
++
++struct fe_soc_data rt2880_data = {
++	.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++	.reset_fe = rt2880_fe_reset,
++	.min_pkt_len = 64,
++        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++	.checksum_bit = RX_DMA_L4VALID,
++	.rx_dly_int = FE_RX_DLY_INT,
++	.tx_dly_int = FE_TX_DLY_INT,
++	.mdio_read = rt2880_mdio_read,
++	.mdio_write = rt2880_mdio_write,
++	.mdio_adjust_link = rt2880_mdio_link_adjust,
++};
++
++const struct of_device_id of_fe_match[] = {
++	{ .compatible = "ralink,rt2880-eth", .data = &rt2880_data },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, of_fe_match);
+diff --git a/drivers/net/ethernet/ralink/soc_rt305x.c b/drivers/net/ethernet/ralink/soc_rt305x.c
+new file mode 100644
+index 0000000..482ca1f
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/soc_rt305x.c
+@@ -0,0 +1,113 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "ralink_soc_eth.h"
++
++#define RT305X_RESET_FE         BIT(21)
++#define RT305X_RESET_ESW        BIT(23)
++#define SYSC_REG_RESET_CTRL     0x034
++
++static const u32 rt5350_reg_table[FE_REG_COUNT] = {
++	[FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
++	[FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
++	[FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
++	[FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
++	[FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
++	[FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
++	[FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
++	[FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
++	[FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
++	[FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
++	[FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
++	[FE_REG_FE_DMA_VID_BASE] = 0,
++};
++
++static void rt305x_fe_reset(void)
++{
++	rt_sysc_w32(RT305X_RESET_FE, SYSC_REG_RESET_CTRL);
++	rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
++}
++
++static void rt5350_set_mac(struct fe_priv *priv, unsigned char *mac)
++{
++	unsigned long flags;
++
++	spin_lock_irqsave(&priv->page_lock, flags);
++	fe_w32((mac[0] << 8) | mac[1], RT5350_SDM_MAC_ADRH);
++	fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
++		RT5350_SDM_MAC_ADRL);
++	spin_unlock_irqrestore(&priv->page_lock, flags);
++}
++
++static void rt5350_fwd_config(struct fe_priv *priv)
++{
++	unsigned long sysclk = priv->sysclk;
++
++	if (sysclk) {
++		sysclk /= FE_US_CYC_CNT_DIVISOR;
++		sysclk <<= FE_US_CYC_CNT_SHIFT;
++
++		fe_w32((fe_r32(FE_FE_GLO_CFG) &
++			~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) | sysclk,
++			FE_FE_GLO_CFG);
++	}
++
++	fe_w32(fe_r32(RT5350_SDM_CFG) & ~0xffff, RT5350_SDM_CFG);
++	fe_w32(fe_r32(RT5350_SDM_CFG) | RT5350_SDM_ICS_EN | RT5350_SDM_TCS_EN | RT5350_SDM_UCS_EN,
++		RT5350_SDM_CFG);
++}
++
++static void rt5350_fe_reset(void)
++{
++	rt_sysc_w32(RT305X_RESET_FE | RT305X_RESET_ESW, SYSC_REG_RESET_CTRL);
++	rt_sysc_w32(0, SYSC_REG_RESET_CTRL);
++}
++
++static struct fe_soc_data rt3050_data = {
++	.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++	.reset_fe = rt305x_fe_reset,
++	.min_pkt_len = 64,
++        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++	.checksum_bit = RX_DMA_L4VALID,
++	.rx_dly_int = FE_RX_DLY_INT,
++	.tx_dly_int = FE_TX_DLY_INT,
++};
++
++static struct fe_soc_data rt5350_data = {
++	.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++	.reg_table = rt5350_reg_table,
++	.reset_fe = rt5350_fe_reset,
++	.set_mac = rt5350_set_mac,
++	.fwd_config = rt5350_fwd_config,
++	.min_pkt_len = 64,
++        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++	.checksum_bit = RX_DMA_L4VALID,
++	.rx_dly_int = RT5350_RX_DLY_INT,
++	.tx_dly_int = RT5350_TX_DLY_INT,
++};
++
++const struct of_device_id of_fe_match[] = {
++	{ .compatible = "ralink,rt3050-eth", .data = &rt3050_data },
++	{ .compatible = "ralink,rt5350-eth", .data = &rt5350_data },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, of_fe_match);
+diff --git a/drivers/net/ethernet/ralink/soc_rt3883.c b/drivers/net/ethernet/ralink/soc_rt3883.c
+new file mode 100644
+index 0000000..c660529
+--- /dev/null
++++ b/drivers/net/ethernet/ralink/soc_rt3883.c
+@@ -0,0 +1,60 @@
++/*
++ *   This program is free software; you can redistribute it and/or modify
++ *   it under the terms of the GNU General Public License as published by
++ *   the Free Software Foundation; version 2 of the License
++ *
++ *   This program is distributed in the hope that it will be useful,
++ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *   GNU General Public License for more details.
++ *
++ *   You should have received a copy of the GNU General Public License
++ *   along with this program; if not, write to the Free Software
++ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
++ *
++ *   Copyright (C) 2009-2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#include "ralink_soc_eth.h"
++#include "mdio_rt2880.h"
++
++#define RT3883_SYSC_REG_RSTCTRL		0x34
++#define RT3883_RSTCTRL_FE		BIT(21)
++
++static void rt3883_fe_reset(void)
++{
++	u32 t;
++
++	t = rt_sysc_r32(RT3883_SYSC_REG_RSTCTRL);
++	t |= RT3883_RSTCTRL_FE;
++	rt_sysc_w32(t , RT3883_SYSC_REG_RSTCTRL);
++
++	t &= ~RT3883_RSTCTRL_FE;
++	rt_sysc_w32(t, RT3883_SYSC_REG_RSTCTRL);
++}
++
++static struct fe_soc_data rt3883_data = {
++	.mac = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 },
++	.reset_fe = rt3883_fe_reset,
++	.min_pkt_len = 64,
++        .pdma_glo_cfg = FE_PDMA_SIZE_4DWORDS,
++	.rx_dly_int = FE_RX_DLY_INT,
++	.tx_dly_int = FE_TX_DLY_INT,
++	.checksum_bit = RX_DMA_L4VALID,
++	.mdio_read = rt2880_mdio_read,
++	.mdio_write = rt2880_mdio_write,
++	.mdio_adjust_link = rt2880_mdio_link_adjust,
++	.port_init = rt2880_port_init,
++};
++
++const struct of_device_id of_fe_match[] = {
++	{ .compatible = "ralink,rt3883-eth", .data = &rt3883_data },
++	{},
++};
++
++MODULE_DEVICE_TABLE(of, of_fe_match);
++
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0017-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch b/target/linux/ramips/patches-3.10/0017-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch
new file mode 100644
index 0000000..c86a4a3
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0017-USB-MIPS-ralink-fix-usb-issue-on-mt7620.patch
@@ -0,0 +1,48 @@
+From 3f40514a51b44171d274ef6a7d66dce9ae7c349d Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 24 May 2013 21:28:08 +0200
+Subject: [PATCH 17/33] USB: MIPS: ralink: fix usb issue on mt7620
+
+USB fails when frequency scaling is enabled. Increase the idle cpu speed when
+scaled.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/include/asm/mach-ralink/mt7620.h |    1 +
+ arch/mips/ralink/mt7620.c                  |    8 ++++++++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
+index 9809972..d469c69 100644
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -20,6 +20,7 @@
+ #define SYSC_REG_CHIP_REV		0x0c
+ #define SYSC_REG_SYSTEM_CONFIG0		0x10
+ #define SYSC_REG_SYSTEM_CONFIG1		0x14
++#define SYSC_REG_CPU_SYS_CLKCFG		0x3c
+ #define SYSC_REG_CPLL_CONFIG0		0x54
+ #define SYSC_REG_CPLL_CONFIG1		0x58
+ 
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+index 96422e5..6f6b1c8 100644
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -185,6 +185,14 @@ void __init ralink_clk_init(void)
+ 	ralink_clk_add("10000500.uart", 40000000);
+ 	ralink_clk_add("10000b00.spi", 40000000);
+ 	ralink_clk_add("10000c00.uartlite", 40000000);
++
++#ifdef CONFIG_USB
++	/*
++	 * When the CPU goes into sleep mode, the BUS clock will be too low for
++	 * USB to function properly
++	 */
++	rt_sysc_m32(0x1f1f, 0x303, SYSC_REG_CPU_SYS_CLKCFG);
++#endif
+ }
+ 
+ void __init ralink_of_remap(void)
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0018-USB-phy-add-ralink-SoC-driver.patch b/target/linux/ramips/patches-3.10/0018-USB-phy-add-ralink-SoC-driver.patch
new file mode 100644
index 0000000..daa351a
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0018-USB-phy-add-ralink-SoC-driver.patch
@@ -0,0 +1,239 @@
+From c5f51197b13fd312324ac0486a46e530e163eade Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:31:19 +0200
+Subject: [PATCH 18/33] USB: phy: add ralink SoC driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/usb/phy/Kconfig      |    8 ++
+ drivers/usb/phy/Makefile     |    1 +
+ drivers/usb/phy/ralink-phy.c |  191 ++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 200 insertions(+)
+ create mode 100644 drivers/usb/phy/ralink-phy.c
+
+diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
+index 2311b1e..2944b8c 100644
+--- a/drivers/usb/phy/Kconfig
++++ b/drivers/usb/phy/Kconfig
+@@ -210,4 +210,12 @@ config USB_ULPI_VIEWPORT
+ 	  Provides read/write operations to the ULPI phy register set for
+ 	  controllers with a viewport register (e.g. Chipidea/ARC controllers).
+ 
++config RALINK_USBPHY
++	bool "Ralink USB PHY controller Driver"
++	depends on MIPS && RALINK
++	select USB_OTG_UTILS
++	help
++	  Enable this to support ralink USB phy controller for ralink
++	  SoCs.
++
+ endif # USB_PHY
+diff --git a/drivers/usb/phy/Makefile b/drivers/usb/phy/Makefile
+index a9169cb..f7da66b 100644
+--- a/drivers/usb/phy/Makefile
++++ b/drivers/usb/phy/Makefile
+@@ -31,3 +31,4 @@ obj-$(CONFIG_USB_MXS_PHY)		+= phy-mxs-usb.o
+ obj-$(CONFIG_USB_RCAR_PHY)		+= phy-rcar-usb.o
+ obj-$(CONFIG_USB_ULPI)			+= phy-ulpi.o
+ obj-$(CONFIG_USB_ULPI_VIEWPORT)		+= phy-ulpi-viewport.o
++obj-$(CONFIG_RALINK_USBPHY)		+= ralink-phy.o
+diff --git a/drivers/usb/phy/ralink-phy.c b/drivers/usb/phy/ralink-phy.c
+new file mode 100644
+index 0000000..269cff4
+--- /dev/null
++++ b/drivers/usb/phy/ralink-phy.c
+@@ -0,0 +1,191 @@
++/*
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ *
++ * based on: Renesas R-Car USB phy driver
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/usb/otg.h>
++#include <linux/of_platform.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++#include <linux/module.h>
++#include <linux/reset.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define RT_SYSC_REG_SYSCFG1		0x014
++#define RT_SYSC_REG_CLKCFG1		0x030
++#define RT_SYSC_REG_USB_PHY_CFG	0x05c
++
++#define RT_RSTCTRL_UDEV		BIT(25)
++#define RT_RSTCTRL_UHST		BIT(22)
++#define RT_SYSCFG1_USB0_HOST_MODE	BIT(10)
++
++#define MT7620_CLKCFG1_UPHY0_CLK_EN	BIT(25)
++#define RT_CLKCFG1_UPHY1_CLK_EN	BIT(20)
++#define RT_CLKCFG1_UPHY0_CLK_EN	BIT(18)
++
++#define USB_PHY_UTMI_8B60M		BIT(1)
++#define UDEV_WAKEUP			BIT(0)
++
++static atomic_t usb_pwr_ref = ATOMIC_INIT(0);
++static struct reset_control *rstdev;
++static struct reset_control *rsthost;
++static u32 phy_clk;
++
++static void usb_phy_enable(int state)
++{
++	if (state)
++		rt_sysc_m32(0, phy_clk, RT_SYSC_REG_CLKCFG1);
++	else
++		rt_sysc_m32(phy_clk, 0, RT_SYSC_REG_CLKCFG1);
++	mdelay(100);
++}
++
++static int usb_power_on(struct usb_phy *phy)
++{
++	if (atomic_inc_return(&usb_pwr_ref) == 1) {
++		u32 t;
++
++		usb_phy_enable(1);
++
++//		reset_control_assert(rstdev);
++//		reset_control_assert(rsthost);
++
++		if (OTG_STATE_B_HOST) {
++			rt_sysc_m32(0, RT_SYSCFG1_USB0_HOST_MODE, RT_SYSC_REG_SYSCFG1);
++			reset_control_deassert(rsthost);
++		} else {
++			rt_sysc_m32(RT_SYSCFG1_USB0_HOST_MODE, 0, RT_SYSC_REG_SYSCFG1);
++			reset_control_deassert(rstdev);
++		}
++		mdelay(100);
++
++		t = rt_sysc_r32(RT_SYSC_REG_USB_PHY_CFG);
++		dev_info(phy->dev, "remote usb device wakeup %s\n",
++				(t & UDEV_WAKEUP) ? ("enabbled") : ("disabled"));
++		if (t & USB_PHY_UTMI_8B60M)
++			dev_info(phy->dev, "UTMI 8bit 60MHz\n");
++		else
++			dev_info(phy->dev, "UTMI 16bit 30MHz\n");
++	}
++
++	return 0;
++}
++
++static void usb_power_off(struct usb_phy *phy)
++{
++	if (atomic_dec_return(&usb_pwr_ref) == 0) {
++		usb_phy_enable(0);
++		reset_control_assert(rstdev);
++		reset_control_assert(rsthost);
++	}
++}
++
++static int usb_set_host(struct usb_otg *otg, struct usb_bus *host)
++{
++	otg->gadget = NULL;
++	otg->host = host;
++
++	return 0;
++}
++
++static int usb_set_peripheral(struct usb_otg *otg,
++		struct usb_gadget *gadget)
++{
++	otg->host = NULL;
++	otg->gadget = gadget;
++
++	return 0;
++}
++
++static const struct of_device_id ralink_usbphy_dt_match[] = {
++	{ .compatible = "ralink,rt3xxx-usbphy", .data = (void *) (RT_CLKCFG1_UPHY1_CLK_EN | RT_CLKCFG1_UPHY0_CLK_EN) },
++	{ .compatible = "ralink,mt7620a-usbphy", .data = (void *) MT7620_CLKCFG1_UPHY0_CLK_EN },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ralink_usbphy_dt_match);
++
++static int usb_phy_probe(struct platform_device *pdev)
++{
++	const struct of_device_id *match;
++	struct device *dev = &pdev->dev;
++	struct usb_otg *otg;
++	struct usb_phy *phy;
++	int ret;
++
++	match = of_match_device(ralink_usbphy_dt_match, &pdev->dev);
++	phy_clk = (int) match->data;
++
++	rsthost = devm_reset_control_get(&pdev->dev, "host");
++	if (IS_ERR(rsthost))
++		return PTR_ERR(rsthost);
++
++	rstdev = devm_reset_control_get(&pdev->dev, "device");
++	if (IS_ERR(rstdev))
++		return PTR_ERR(rstdev);
++
++	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
++	if (!phy) {
++		dev_err(&pdev->dev, "unable to allocate memory for USB PHY\n");
++		return -ENOMEM;
++	}
++
++	otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL);
++	if (!otg) {
++		dev_err(&pdev->dev, "unable to allocate memory for USB OTG\n");
++		return -ENOMEM;
++	}
++
++	phy->dev = dev;
++	phy->label = dev_name(dev);
++	phy->init = usb_power_on;
++	phy->shutdown = usb_power_off;
++	otg->set_host = usb_set_host;
++	otg->set_peripheral = usb_set_peripheral;
++	otg->phy = phy;
++	phy->otg = otg;
++	ret = usb_add_phy(phy, USB_PHY_TYPE_USB2);
++
++	if (ret < 0) {
++		dev_err(dev, "usb phy addition error\n");
++		return ret;
++	}
++
++	platform_set_drvdata(pdev, phy);
++
++	dev_info(&pdev->dev, "loaded\n");
++
++	return ret;
++}
++
++static int usb_phy_remove(struct platform_device *pdev)
++{
++	struct usb_phy *phy = platform_get_drvdata(pdev);
++
++	usb_remove_phy(phy);
++
++	return 0;
++}
++
++static struct platform_driver usb_phy_driver = {
++	.driver		= {
++		.owner	= THIS_MODULE,
++		.name	= "rt3xxx-usbphy",
++		.of_match_table = of_match_ptr(ralink_usbphy_dt_match),
++	},
++	.probe		= usb_phy_probe,
++	.remove		= usb_phy_remove,
++};
++
++module_platform_driver(usb_phy_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_DESCRIPTION("Ralink USB phy");
++MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0019-USB-add-OHCI-EHCI-OF-binding.patch b/target/linux/ramips/patches-3.10/0019-USB-add-OHCI-EHCI-OF-binding.patch
new file mode 100644
index 0000000..b094bc6
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0019-USB-add-OHCI-EHCI-OF-binding.patch
@@ -0,0 +1,188 @@
+From 40b9d3026ed0b3bcd59f90391195df5b2adabad2 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:34:53 +0200
+Subject: [PATCH 19/33] USB: add OHCI/EHCI OF binding
+
+based on f3bc64d6d1f21c1b92d75f233a37b75d77af6963
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Kconfig         |    2 ++
+ drivers/usb/Makefile             |    3 ++-
+ drivers/usb/host/ehci-platform.c |   19 +++++++++++++++----
+ drivers/usb/host/ohci-platform.c |   37 ++++++++++++++++++++++++++++++++-----
+ 4 files changed, 51 insertions(+), 10 deletions(-)
+
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 992e365..8f49ed7 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -24,6 +24,8 @@ choice
+ 
+ 	config SOC_MT7620
+ 		bool "MT7620"
++		select USB_ARCH_HAS_OHCI
++		select USB_ARCH_HAS_EHCI
+ 		select HW_HAS_PCI
+ 
+ endchoice
+diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
+index c41feba..d155174 100644
+--- a/drivers/usb/Makefile
++++ b/drivers/usb/Makefile
+@@ -10,6 +10,8 @@ obj-$(CONFIG_USB_DWC3)		+= dwc3/
+ 
+ obj-$(CONFIG_USB_MON)		+= mon/
+ 
++obj-$(CONFIG_USB_OTG_UTILS)	+= phy/
++
+ obj-$(CONFIG_PCI)		+= host/
+ obj-$(CONFIG_USB_EHCI_HCD)	+= host/
+ obj-$(CONFIG_USB_ISP116X_HCD)	+= host/
+@@ -44,7 +46,6 @@ obj-$(CONFIG_USB_MICROTEK)	+= image/
+ obj-$(CONFIG_USB_SERIAL)	+= serial/
+ 
+ obj-$(CONFIG_USB)		+= misc/
+-obj-$(CONFIG_USB_PHY)		+= phy/
+ obj-$(CONFIG_EARLY_PRINTK_DBGP)	+= early/
+ 
+ obj-$(CONFIG_USB_ATM)		+= atm/
+diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
+index f47f259..84d22ff 100644
+--- a/drivers/usb/host/ehci-platform.c
++++ b/drivers/usb/host/ehci-platform.c
+@@ -117,6 +117,15 @@ static int ehci_platform_probe(struct platform_device *dev)
+ 	hcd->rsrc_start = res_mem->start;
+ 	hcd->rsrc_len = resource_size(res_mem);
+ 
++#ifdef CONFIG_USB_OTG_UTILS
++	hcd->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB2);
++	if (!IS_ERR_OR_NULL(hcd->phy)) {
++		otg_set_host(hcd->phy->otg,
++				&hcd->self);
++		usb_phy_init(hcd->phy);
++	}
++#endif
++
+ 	hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
+ 	if (IS_ERR(hcd->regs)) {
+ 		err = PTR_ERR(hcd->regs);
+@@ -154,6 +163,9 @@ static int ehci_platform_remove(struct platform_device *dev)
+ 	if (pdata == &ehci_platform_defaults)
+ 		dev->dev.platform_data = NULL;
+ 
++	if (pdata == &ehci_platform_defaults)
++		dev->dev.platform_data = NULL;
++
+ 	return 0;
+ }
+ 
+@@ -198,9 +210,8 @@ static int ehci_platform_resume(struct device *dev)
+ #define ehci_platform_resume	NULL
+ #endif /* CONFIG_PM */
+ 
+-static const struct of_device_id vt8500_ehci_ids[] = {
+-	{ .compatible = "via,vt8500-ehci", },
+-	{ .compatible = "wm,prizm-ehci", },
++static const struct of_device_id ralink_ehci_ids[] = {
++	{ .compatible = "ralink,rt3xxx-ehci", },
+ 	{}
+ };
+ 
+@@ -224,7 +235,7 @@ static struct platform_driver ehci_platform_driver = {
+ 		.owner	= THIS_MODULE,
+ 		.name	= "ehci-platform",
+ 		.pm	= &ehci_platform_pm_ops,
+-		.of_match_table = of_match_ptr(vt8500_ehci_ids),
++		.of_match_table = of_match_ptr(ralink_ehci_ids),
+ 	}
+ };
+ 
+diff --git a/drivers/usb/host/ohci-platform.c b/drivers/usb/host/ohci-platform.c
+index c3e7287..dd9bac6 100644
+--- a/drivers/usb/host/ohci-platform.c
++++ b/drivers/usb/host/ohci-platform.c
+@@ -16,6 +16,10 @@
+ #include <linux/err.h>
+ #include <linux/platform_device.h>
+ #include <linux/usb/ohci_pdriver.h>
++#include <linux/dma-mapping.h>
++#include <linux/of.h>
++
++static struct usb_ohci_pdata ohci_platform_defaults;
+ 
+ static int ohci_platform_reset(struct usb_hcd *hcd)
+ {
+@@ -88,14 +92,22 @@ static int ohci_platform_probe(struct platform_device *dev)
+ {
+ 	struct usb_hcd *hcd;
+ 	struct resource *res_mem;
+-	struct usb_ohci_pdata *pdata = dev->dev.platform_data;
++	struct usb_ohci_pdata *pdata;
+ 	int irq;
+ 	int err = -ENOMEM;
+ 
+-	if (!pdata) {
+-		WARN_ON(1);
+-		return -ENODEV;
+-	}
++	/*
++	 * use reasonable defaults so platforms don't have to provide these.
++	 * with DT probing on ARM, none of these are set.
++	 */
++	if (!dev->dev.platform_data)
++		dev->dev.platform_data = &ohci_platform_defaults;
++	if (!dev->dev.dma_mask)
++		dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
++	if (!dev->dev.coherent_dma_mask)
++		dev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++
++	pdata = dev->dev.platform_data;
+ 
+ 	if (usb_disabled())
+ 		return -ENODEV;
+@@ -128,6 +140,12 @@ static int ohci_platform_probe(struct platform_device *dev)
+ 	hcd->rsrc_start = res_mem->start;
+ 	hcd->rsrc_len = resource_size(res_mem);
+ 
++#ifdef CONFIG_USB_OTG_UTILS
++	hcd->phy = devm_usb_get_phy(&dev->dev, USB_PHY_TYPE_USB2);
++	if (!IS_ERR_OR_NULL(hcd->phy))
++		usb_phy_init(hcd->phy);
++#endif
++
+ 	hcd->regs = devm_ioremap_resource(&dev->dev, res_mem);
+ 	if (IS_ERR(hcd->regs)) {
+ 		err = PTR_ERR(hcd->regs);
+@@ -162,6 +180,9 @@ static int ohci_platform_remove(struct platform_device *dev)
+ 	if (pdata->power_off)
+ 		pdata->power_off(dev);
+ 
++	if (pdata == &ohci_platform_defaults)
++		dev->dev.platform_data = NULL;
++
+ 	return 0;
+ }
+ 
+@@ -201,6 +222,11 @@ static int ohci_platform_resume(struct device *dev)
+ #define ohci_platform_resume	NULL
+ #endif /* CONFIG_PM */
+ 
++static const struct of_device_id ralink_ohci_ids[] = {
++	{ .compatible = "ralink,rt3xxx-ohci", },
++	{}
++};
++
+ static const struct platform_device_id ohci_platform_table[] = {
+ 	{ "ohci-platform", 0 },
+ 	{ }
+@@ -221,5 +247,6 @@ static struct platform_driver ohci_platform_driver = {
+ 		.owner	= THIS_MODULE,
+ 		.name	= "ohci-platform",
+ 		.pm	= &ohci_platform_pm_ops,
++		.of_match_table = of_match_ptr(ralink_ohci_ids),
+ 	}
+ };
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0020-serial-ralink-adds-mt7620-serial.patch b/target/linux/ramips/patches-3.10/0020-serial-ralink-adds-mt7620-serial.patch
new file mode 100644
index 0000000..98516c4
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0020-serial-ralink-adds-mt7620-serial.patch
@@ -0,0 +1,28 @@
+From 629a2ca61e0fbf331f88692038391d22f21b7c70 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Fri, 15 Mar 2013 18:16:01 +0100
+Subject: [PATCH 20/33] serial: ralink: adds mt7620 serial
+
+Add the config symbol for Mediatek7620 SoC to SERIAL_8250_RT288X
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/8250/Kconfig |    2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig
+index 80fe91e..f6d6820 100644
+--- a/drivers/tty/serial/8250/Kconfig
++++ b/drivers/tty/serial/8250/Kconfig
+@@ -296,7 +296,7 @@ config SERIAL_8250_EM
+ 
+ config SERIAL_8250_RT288X
+ 	bool "Ralink RT288x/RT305x/RT3662/RT3883 serial port support"
+-	depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883)
++	depends on SERIAL_8250 && (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
+ 	help
+ 	  If you have a Ralink RT288x/RT305x SoC based board and want to use the
+ 	  serial port, say Y to this option. The driver can handle up to 2 serial
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0021-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch b/target/linux/ramips/patches-3.10/0021-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
new file mode 100644
index 0000000..73fbab9
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0021-serial-of-allow-au1x00-and-rt288x-to-load-from-OF.patch
@@ -0,0 +1,32 @@
+From 53b934f796611b9a27b698429f1aaec0fe678693 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:18:57 +0200
+Subject: [PATCH 21/33] serial: of: allow au1x00 and rt288x to load from OF
+
+In order to make serial_8250 loadable via OF on Au1x00 and Ralink WiSoC we need
+to default the iotype to UPIO_AU.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/tty/serial/of_serial.c |    5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/tty/serial/of_serial.c b/drivers/tty/serial/of_serial.c
+index 39c7ea4..0f333f3 100644
+--- a/drivers/tty/serial/of_serial.c
++++ b/drivers/tty/serial/of_serial.c
+@@ -103,7 +103,10 @@ static int of_platform_serial_setup(struct platform_device *ofdev,
+ 		port->fifosize = prop;
+ 
+ 	port->irq = irq_of_parse_and_map(np, 0);
+-	port->iotype = UPIO_MEM;
++	if (of_device_is_compatible(np, "ralink,rt2880-uart"))
++		port->iotype = UPIO_AU;
++	else
++		port->iotype = UPIO_MEM;
+ 	if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
+ 		switch (prop) {
+ 		case 1:
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0022-clocksource-MIPS-ralink-add-support-for-systick-time.patch b/target/linux/ramips/patches-3.10/0022-clocksource-MIPS-ralink-add-support-for-systick-time.patch
new file mode 100644
index 0000000..c5924ff
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0022-clocksource-MIPS-ralink-add-support-for-systick-time.patch
@@ -0,0 +1,246 @@
+From 10cb446ac01be52c49b5143c8601524bc4f53051 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:11:05 +0200
+Subject: [PATCH 22/33] clocksource: MIPS: ralink: add support for systick
+ timer found on newer ralink SoC
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/Kconfig          |    2 +
+ arch/mips/ralink/clk.c            |    1 +
+ drivers/clocksource/Kconfig       |    6 ++
+ drivers/clocksource/Makefile      |    1 +
+ drivers/clocksource/cevt-rt3352.c |  162 +++++++++++++++++++++++++++++++++++++
+ 5 files changed, 172 insertions(+)
+ create mode 100644 drivers/clocksource/cevt-rt3352.c
+
+diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
+index 8f49ed7..f5d97b8 100644
+--- a/arch/mips/ralink/Kconfig
++++ b/arch/mips/ralink/Kconfig
+@@ -15,6 +15,7 @@ choice
+ 		select USB_ARCH_HAS_HCD
+ 		select USB_ARCH_HAS_OHCI
+ 		select USB_ARCH_HAS_EHCI
++		select CLKEVT_RT3352
+ 
+ 	config SOC_RT3883
+ 		bool "RT3883"
+@@ -27,6 +28,7 @@ choice
+ 		select USB_ARCH_HAS_OHCI
+ 		select USB_ARCH_HAS_EHCI
+ 		select HW_HAS_PCI
++		select CLKEVT_RT3352
+ 
+ endchoice
+ 
+diff --git a/arch/mips/ralink/clk.c b/arch/mips/ralink/clk.c
+index 8dfa22f..bba0cdf 100644
+--- a/arch/mips/ralink/clk.c
++++ b/arch/mips/ralink/clk.c
+@@ -69,4 +69,5 @@ void __init plat_time_init(void)
+ 	pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
+ 	mips_hpt_frequency = clk_get_rate(clk) / 2;
+ 	clk_put(clk);
++	clocksource_of_init();
+ }
+diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
+index f151c6c..0e58a49 100644
+--- a/drivers/clocksource/Kconfig
++++ b/drivers/clocksource/Kconfig
+@@ -7,6 +7,12 @@ config CLKSRC_I8253
+ config CLKEVT_I8253
+ 	bool
+ 
++config CLKEVT_RT3352
++	bool
++	depends on MIPS && RALINK
++	select CLKSRC_OF
++	select CLKSRC_MMIO
++
+ config I8253_LOCK
+ 	bool
+ 
+diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
+index 8d979c7..423a2ef 100644
+--- a/drivers/clocksource/Makefile
++++ b/drivers/clocksource/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_SH_TIMER_TMU)	+= sh_tmu.o
+ obj-$(CONFIG_EM_TIMER_STI)	+= em_sti.o
+ obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
+ obj-$(CONFIG_CLKSRC_MMIO)	+= mmio.o
++obj-$(CONFIG_CLKEVT_RT3352)	+= cevt-rt3352.o
+ obj-$(CONFIG_DW_APB_TIMER)	+= dw_apb_timer.o
+ obj-$(CONFIG_DW_APB_TIMER_OF)	+= dw_apb_timer_of.o
+ obj-$(CONFIG_CLKSRC_NOMADIK_MTU)	+= nomadik-mtu.o
+diff --git a/drivers/clocksource/cevt-rt3352.c b/drivers/clocksource/cevt-rt3352.c
+new file mode 100644
+index 0000000..bd50edd
+--- /dev/null
++++ b/drivers/clocksource/cevt-rt3352.c
+@@ -0,0 +1,162 @@
++/*
++ * This file is subject to the terms and conditions of the GNU General Public
++ * License.  See the file "COPYING" in the main directory of this archive
++ * for more details.
++ *
++ * Copyright (C) 2013 by John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/clockchips.h>
++#include <linux/clocksource.h>
++#include <linux/interrupt.h>
++#include <linux/reset.h>
++#include <linux/init.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/time.h>
++
++#define SYSTICK_FREQ	(50 * 1000)
++
++#define SYSTICK_CONFIG	0x00
++#define SYSTICK_COMPARE	0x04
++#define SYSTICK_COUNT	0x08
++
++/* route systick irq to mips irq 7 instead of the r4k-timer */
++#define CFG_EXT_STK_EN	0x2
++/* enable the counter */
++#define CFG_CNT_EN	0x1
++
++struct systick_device {
++	void __iomem *membase;
++	struct clock_event_device dev;
++	int irq_requested;
++	int freq_scale;
++};
++
++static void systick_set_clock_mode(enum clock_event_mode mode,
++				struct clock_event_device *evt);
++
++static int systick_next_event(unsigned long delta,
++				struct clock_event_device *evt)
++{
++	struct systick_device *sdev = container_of(evt, struct systick_device, dev);
++	u32 count;
++
++	count = ioread32(sdev->membase + SYSTICK_COUNT);
++	count = (count + delta) % SYSTICK_FREQ;
++	iowrite32(count + delta, sdev->membase + SYSTICK_COMPARE);
++
++	return 0;
++}
++
++static void systick_event_handler(struct clock_event_device *dev)
++{
++	/* noting to do here */
++}
++
++static irqreturn_t systick_interrupt(int irq, void *dev_id)
++{
++	struct clock_event_device *dev = (struct clock_event_device *) dev_id;
++
++	dev->event_handler(dev);
++
++	return IRQ_HANDLED;
++}
++
++static struct systick_device systick = {
++	.dev = {
++		/* cevt-r4k uses 300, make sure systick gets used if available */
++		.rating		= 310,
++		.features	= CLOCK_EVT_FEAT_ONESHOT,
++		.set_next_event	= systick_next_event,
++		.set_mode	= systick_set_clock_mode,
++		.event_handler	= systick_event_handler,
++	},
++};
++
++static struct irqaction systick_irqaction = {
++	.handler = systick_interrupt,
++	.flags = IRQF_PERCPU | IRQF_TIMER,
++	.dev_id = &systick.dev,
++};
++
++/* ugly hack */
++#ifdef CONFIG_SOC_MT7620
++
++#define CLK_LUT_CFG	0x40
++#define SLEEP_EN	BIT(31)
++
++static inline void mt7620_freq_scaling(struct systick_device *sdev, int status)
++{
++	if (sdev->freq_scale == status)
++		return;
++
++	sdev->freq_scale = status;
++
++	pr_info("%s: %s autosleep mode\n", systick.dev.name, (status) ? ("enable") : ("disable"));
++	if (status)
++		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) | SLEEP_EN, CLK_LUT_CFG);
++	else
++		rt_sysc_w32(rt_sysc_r32(CLK_LUT_CFG) & ~SLEEP_EN, CLK_LUT_CFG);
++}
++#else
++static inline void mt7620_freq_scaling(struct systick_device *sdev, int status) {}
++#endif
++
++static void systick_set_clock_mode(enum clock_event_mode mode,
++				struct clock_event_device *evt)
++{
++	struct systick_device *sdev = container_of(evt, struct systick_device, dev);
++
++	switch (mode) {
++	case CLOCK_EVT_MODE_ONESHOT:
++		if (!sdev->irq_requested)
++			setup_irq(systick.dev.irq, &systick_irqaction);
++		mt7620_freq_scaling(sdev, 1);
++		sdev->irq_requested = 1;
++		iowrite32(CFG_EXT_STK_EN | CFG_CNT_EN, systick.membase + SYSTICK_CONFIG);
++		break;
++
++	case CLOCK_EVT_MODE_SHUTDOWN:
++		if (sdev->irq_requested)
++			free_irq(systick.dev.irq, &systick_irqaction);
++		mt7620_freq_scaling(sdev, 0);
++		sdev->irq_requested = 0;
++		iowrite32(0, systick.membase + SYSTICK_CONFIG);
++		break;
++
++	default:
++		pr_err("%s: Unhandeled mips clock_mode\n", systick.dev.name);
++		break;
++	}
++}
++
++static void __init ralink_systick_init(struct device_node *np)
++{
++	systick.membase = of_iomap(np, 0);
++	if (!systick.membase) {
++		pr_err("%s: of_iomap failed", np->name);
++		return;
++	}
++
++	clocksource_mmio_init(systick.membase + SYSTICK_COUNT, np->name,
++			SYSTICK_FREQ, 301, 16, clocksource_mmio_readl_up);
++
++	systick_irqaction.name = np->name;
++	systick.dev.name = np->name;
++	clockevent_set_clock(&systick.dev, SYSTICK_FREQ);
++	systick.dev.max_delta_ns = clockevent_delta2ns(0x7fff, &systick.dev);
++	systick.dev.min_delta_ns = clockevent_delta2ns(0x3, &systick.dev);
++	systick.dev.irq = irq_of_parse_and_map(np, 0);
++	if (!systick.dev.irq)
++		panic("%s: request_irq failed", np->name);
++
++	clockevents_register_device(&systick.dev);
++
++	pr_info("%s: runing - mult: %d, shift: %d\n", np->name, systick.dev.mult, systick.dev.shift);
++}
++
++CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0023-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch b/target/linux/ramips/patches-3.10/0023-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch
new file mode 100644
index 0000000..e39443a
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0023-GPIO-MIPS-ralink-adds-ralink-gpio-support.patch
@@ -0,0 +1,425 @@
+From 3af8b2904d2d4758f88bc96c7c9ecff4a708347f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 14 Jul 2013 23:17:27 +0200
+Subject: [PATCH 23/33] GPIO: MIPS: ralink: adds ralink gpio support
+
+Add gpio driver for Ralink SoC. This driver makes the gpio core on
+RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/Kconfig                        |    1 +
+ arch/mips/include/asm/mach-ralink/gpio.h |   24 +++
+ drivers/gpio/Kconfig                     |    6 +
+ drivers/gpio/Makefile                    |    1 +
+ drivers/gpio/gpio-ralink.c               |  326 ++++++++++++++++++++++++++++++
+ 5 files changed, 358 insertions(+)
+ create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
+ create mode 100644 drivers/gpio/gpio-ralink.c
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 7a58ab9..5737c4b 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -443,6 +443,7 @@ config RALINK
+ 	select SYS_HAS_EARLY_PRINTK
+ 	select HAVE_MACH_CLKDEV
+ 	select CLKDEV_LOOKUP
++	select ARCH_REQUIRE_GPIOLIB
+ 
+ config SGI_IP22
+ 	bool "SGI IP22 (Indy/Indigo2)"
+diff --git a/arch/mips/include/asm/mach-ralink/gpio.h b/arch/mips/include/asm/mach-ralink/gpio.h
+new file mode 100644
+index 0000000..f68ee16
+--- /dev/null
++++ b/arch/mips/include/asm/mach-ralink/gpio.h
+@@ -0,0 +1,24 @@
++/*
++ *  Ralink SoC GPIO API support
++ *
++ *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
++ *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
++ *
++ *  This program is free software; you can redistribute it and/or modify it
++ *  under the terms of the GNU General Public License version 2 as published
++ *  by the Free Software Foundation.
++ *
++ */
++
++#ifndef __ASM_MACH_RALINK_GPIO_H
++#define __ASM_MACH_RALINK_GPIO_H
++
++#define ARCH_NR_GPIOS	128
++#include <asm-generic/gpio.h>
++
++#define gpio_get_value	__gpio_get_value
++#define gpio_set_value	__gpio_set_value
++#define gpio_cansleep	__gpio_cansleep
++#define gpio_to_irq	__gpio_to_irq
++
++#endif /* __ASM_MACH_RALINK_GPIO_H */
+diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
+index 573c449..4f2f7c2 100644
+--- a/drivers/gpio/Kconfig
++++ b/drivers/gpio/Kconfig
+@@ -209,6 +209,12 @@ config GPIO_RCAR
+ 	help
+ 	  Say yes here to support GPIO on Renesas R-Car SoCs.
+ 
++config GPIO_RALINK
++	bool "Ralink GPIO Support"
++	depends on RALINK
++	help
++	  Say yes here to support the Ralink SoC GPIO device
++
+ config GPIO_SPEAR_SPICS
+ 	bool "ST SPEAr13xx SPI Chip Select as GPIO support"
+ 	depends on PLAT_SPEAR
+diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
+index 0cb2d65..feb9647 100644
+--- a/drivers/gpio/Makefile
++++ b/drivers/gpio/Makefile
+@@ -56,6 +56,7 @@ obj-$(CONFIG_GPIO_PCF857X)	+= gpio-pcf857x.o
+ obj-$(CONFIG_GPIO_PCH)		+= gpio-pch.o
+ obj-$(CONFIG_GPIO_PL061)	+= gpio-pl061.o
+ obj-$(CONFIG_GPIO_PXA)		+= gpio-pxa.o
++obj-$(CONFIG_GPIO_RALINK)	+= gpio-ralink.o
+ obj-$(CONFIG_GPIO_RC5T583)	+= gpio-rc5t583.o
+ obj-$(CONFIG_GPIO_RDC321X)	+= gpio-rdc321x.o
+ obj-$(CONFIG_GPIO_RCAR)		+= gpio-rcar.o
+diff --git a/drivers/gpio/gpio-ralink.c b/drivers/gpio/gpio-ralink.c
+new file mode 100644
+index 0000000..12984f1
+--- /dev/null
++++ b/drivers/gpio/gpio-ralink.c
+@@ -0,0 +1,326 @@
++/*
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ *
++ * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ */
++
++#include <linux/module.h>
++#include <linux/io.h>
++#include <linux/gpio.h>
++#include <linux/spinlock.h>
++#include <linux/platform_device.h>
++#include <linux/of_irq.h>
++#include <linux/irqdomain.h>
++#include <linux/interrupt.h>
++
++enum ralink_gpio_reg {
++	GPIO_REG_INT = 0,
++	GPIO_REG_EDGE,
++	GPIO_REG_RENA,
++	GPIO_REG_FENA,
++	GPIO_REG_DATA,
++	GPIO_REG_DIR,
++	GPIO_REG_POL,
++	GPIO_REG_SET,
++	GPIO_REG_RESET,
++	GPIO_REG_TOGGLE,
++	GPIO_REG_MAX
++};
++
++struct ralink_gpio_chip {
++	struct gpio_chip chip;
++	u8 regs[GPIO_REG_MAX];
++
++	spinlock_t lock;
++	void __iomem *membase;
++	struct irq_domain *domain;
++	int irq;
++
++	u32 rising;
++	u32 falling;
++};
++
++#define MAP_MAX	4
++static struct irq_domain *irq_map[MAP_MAX];
++static int irq_map_count;
++static atomic_t irq_refcount = ATOMIC_INIT(0);
++
++static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
++{
++	struct ralink_gpio_chip *rg;
++
++	rg = container_of(chip, struct ralink_gpio_chip, chip);
++
++	return rg;
++}
++
++static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
++{
++	iowrite32(val, rg->membase + rg->regs[reg]);
++}
++
++static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
++{
++	return ioread32(rg->membase + rg->regs[reg]);
++}
++
++static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++	rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
++}
++
++static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++	return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
++}
++
++static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++	unsigned long flags;
++	u32 t;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	t = rt_gpio_r32(rg, GPIO_REG_DIR);
++	t &= ~BIT(offset);
++	rt_gpio_w32(rg, GPIO_REG_DIR, t);
++	spin_unlock_irqrestore(&rg->lock, flags);
++
++	return 0;
++}
++
++static int ralink_gpio_direction_output(struct gpio_chip *chip,
++					unsigned offset, int value)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++	unsigned long flags;
++	u32 t;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	ralink_gpio_set(chip, offset, value);
++	t = rt_gpio_r32(rg, GPIO_REG_DIR);
++	t |= BIT(offset);
++	rt_gpio_w32(rg, GPIO_REG_DIR, t);
++	spin_unlock_irqrestore(&rg->lock, flags);
++
++	return 0;
++}
++
++static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
++{
++	struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
++
++	if (rg->irq < 1)
++		return -1;
++
++	ralink_gpio_direction_input(chip, pin);
++
++	return irq_create_mapping(rg->domain, pin);
++}
++
++static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
++{
++	int i;
++
++	for (i = 0; i < irq_map_count; i++) {
++		struct irq_domain *domain = irq_map[i];
++		struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) domain->host_data;
++		unsigned long pending = rt_gpio_r32(rg, GPIO_REG_INT);
++		int bit;
++
++		for_each_set_bit(bit, &pending, rg->chip.ngpio) {
++			u32 map = irq_find_mapping(domain, bit);
++			generic_handle_irq(map);
++			rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
++		}
++	}
++}
++
++static void ralink_gpio_irq_unmask(struct irq_data *d)
++{
++	struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
++	u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
++	unsigned long flags;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
++	rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
++	spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static void ralink_gpio_irq_mask(struct irq_data *d)
++{
++	struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
++	u32 val = rt_gpio_r32(rg, GPIO_REG_RENA);
++	unsigned long flags;
++
++	spin_lock_irqsave(&rg->lock, flags);
++	rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
++	rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
++	spin_unlock_irqrestore(&rg->lock, flags);
++}
++
++static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
++{
++	struct ralink_gpio_chip *rg = (struct ralink_gpio_chip *) d->domain->host_data;
++	u32 mask = BIT(d->hwirq);
++
++	if (type == IRQ_TYPE_PROBE) {
++		if ((rg->rising | rg->falling) & mask)
++			return 0;
++
++		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
++	}
++
++	if (type & IRQ_TYPE_EDGE_RISING)
++		rg->rising |= mask;
++	else
++		rg->rising &= mask;
++
++	if (type & IRQ_TYPE_EDGE_RISING)
++		rg->falling |= mask;
++	else
++		rg->falling &= mask;
++
++	return 0;
++}
++
++static struct irq_chip ralink_gpio_irq_chip = {
++	.name		= "GPIO",
++	.irq_unmask	= ralink_gpio_irq_unmask,
++	.irq_mask	= ralink_gpio_irq_mask,
++	.irq_mask_ack	= ralink_gpio_irq_mask,
++	.irq_set_type	= ralink_gpio_irq_type,
++};
++
++static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
++{
++	irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
++	irq_set_handler_data(irq, d);
++
++	return 0;
++}
++
++static const struct irq_domain_ops irq_domain_ops = {
++	.xlate = irq_domain_xlate_onecell,
++	.map = gpio_map,
++};
++
++static void ralink_gpio_irq_init(struct device_node *np, struct ralink_gpio_chip *rg)
++{
++	if (irq_map_count >= MAP_MAX)
++		return;
++
++	rg->irq = irq_of_parse_and_map(np, 0);
++	if (!rg->irq)
++		return;
++
++	rg->domain = irq_domain_add_linear(np, rg->chip.ngpio, &irq_domain_ops, rg);
++	if (!rg->domain) {
++		dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
++		return;
++	}
++
++	irq_map[irq_map_count++] = rg->domain;
++
++	rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
++	rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
++
++	if (!atomic_read(&irq_refcount))
++		irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
++	atomic_inc(&irq_refcount);
++
++	dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
++}
++
++static int ralink_gpio_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	struct ralink_gpio_chip *rg;
++	const __be32 *ngpio, *gpiobase;
++
++	if (!res) {
++		dev_err(&pdev->dev, "failed to find resource\n");
++		return -ENOMEM;
++	}
++
++	rg = devm_kzalloc(&pdev->dev,
++			sizeof(struct ralink_gpio_chip), GFP_KERNEL);
++	if (!rg)
++		return -ENOMEM;
++
++	rg->membase = devm_request_and_ioremap(&pdev->dev, res);
++	if (!rg->membase) {
++		dev_err(&pdev->dev, "cannot remap I/O memory region\n");
++		return -ENOMEM;
++	}
++
++	if (of_property_read_u8_array(np, "ralink,register-map",
++			rg->regs, GPIO_REG_MAX)) {
++		dev_err(&pdev->dev, "failed to read register definition\n");
++		return -EINVAL;
++	}
++
++	ngpio = of_get_property(np, "ralink,num-gpios", NULL);
++	if (!ngpio) {
++		dev_err(&pdev->dev, "failed to read number of pins\n");
++		return -EINVAL;
++	}
++
++	gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
++	if (gpiobase)
++		rg->chip.base = be32_to_cpu(*gpiobase);
++	else
++		rg->chip.base = -1;
++
++	spin_lock_init(&rg->lock);
++
++	rg->chip.dev = &pdev->dev;
++	rg->chip.label = dev_name(&pdev->dev);
++	rg->chip.of_node = np;
++	rg->chip.ngpio = be32_to_cpu(*ngpio);
++	rg->chip.direction_input = ralink_gpio_direction_input;
++	rg->chip.direction_output = ralink_gpio_direction_output;
++	rg->chip.get = ralink_gpio_get;
++	rg->chip.set = ralink_gpio_set;
++	rg->chip.to_irq = ralink_gpio_to_irq;
++
++	/* set polarity to low for all lines */
++	rt_gpio_w32(rg, GPIO_REG_POL, 0);
++
++	dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
++
++	ralink_gpio_irq_init(np, rg);
++
++	return gpiochip_add(&rg->chip);
++}
++
++static const struct of_device_id ralink_gpio_match[] = {
++	{ .compatible = "ralink,rt2880-gpio" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ralink_gpio_match);
++
++static struct platform_driver ralink_gpio_driver = {
++	.probe = ralink_gpio_probe,
++	.driver = {
++		.name = "rt2880_gpio",
++		.owner = THIS_MODULE,
++		.of_match_table = ralink_gpio_match,
++	},
++};
++
++static int __init ralink_gpio_init(void)
++{
++	return platform_driver_register(&ralink_gpio_driver);
++}
++
++subsys_initcall(ralink_gpio_init);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0024-SPI-ralink-add-Ralink-SoC-spi-driver.patch b/target/linux/ramips/patches-3.10/0024-SPI-ralink-add-Ralink-SoC-spi-driver.patch
new file mode 100644
index 0000000..8170bf4
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0024-SPI-ralink-add-Ralink-SoC-spi-driver.patch
@@ -0,0 +1,528 @@
+From d345c53b941a3d791c26f900af6e85aa1bcaf8b6 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 22 Apr 2013 23:16:18 +0200
+Subject: [PATCH 24/33] SPI: ralink: add Ralink SoC spi driver
+
+Add the driver needed to make SPI work on Ralink SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/spi/Kconfig      |    6 +
+ drivers/spi/Makefile     |    1 +
+ drivers/spi/spi-ralink.c |  475 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 482 insertions(+)
+ create mode 100644 drivers/spi/spi-ralink.c
+
+diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
+index 92a9345..30e73ea 100644
+--- a/drivers/spi/Kconfig
++++ b/drivers/spi/Kconfig
+@@ -345,6 +345,12 @@ config SPI_RSPI
+ 	help
+ 	  SPI driver for Renesas RSPI blocks.
+ 
++config SPI_RALINK
++	tristate "Ralink RT288x/RT305x/RT3662 SPI Controller"
++	depends on (SOC_RT288X || SOC_RT305X || SOC_RT3883 || SOC_MT7620)
++	help
++	  This selects a driver for the Ralink RT288x/RT305x SPI Controller.
++
+ config SPI_S3C24XX
+ 	tristate "Samsung S3C24XX series SPI"
+ 	depends on ARCH_S3C24XX
+diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
+index 33f9c09..724e8de1 100644
+--- a/drivers/spi/Makefile
++++ b/drivers/spi/Makefile
+@@ -55,6 +55,7 @@ spi-pxa2xx-platform-$(CONFIG_SPI_PXA2XX_DMA)	+= spi-pxa2xx-dma.o
+ obj-$(CONFIG_SPI_PXA2XX)		+= spi-pxa2xx-platform.o
+ obj-$(CONFIG_SPI_PXA2XX_PCI)		+= spi-pxa2xx-pci.o
+ obj-$(CONFIG_SPI_RSPI)			+= spi-rspi.o
++obj-$(CONFIG_SPI_RALINK)		+= spi-ralink.o
+ obj-$(CONFIG_SPI_S3C24XX)		+= spi-s3c24xx-hw.o
+ spi-s3c24xx-hw-y			:= spi-s3c24xx.o
+ spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o
+diff --git a/drivers/spi/spi-ralink.c b/drivers/spi/spi-ralink.c
+new file mode 100644
+index 0000000..b07cbaa
+--- /dev/null
++++ b/drivers/spi/spi-ralink.c
+@@ -0,0 +1,475 @@
++/*
++ * spi-ralink.c -- Ralink RT288x/RT305x SPI controller driver
++ *
++ * Copyright (C) 2011 Sergiy <piratfm@gmail.com>
++ * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
++ *
++ * Some parts are based on spi-orion.c:
++ *   Author: Shadi Ammouri <shadi@marvell.com>
++ *   Copyright (C) 2007-2008 Marvell Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ */
++
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/clk.h>
++#include <linux/err.h>
++#include <linux/delay.h>
++#include <linux/io.h>
++#include <linux/reset.h>
++#include <linux/spi/spi.h>
++#include <linux/platform_device.h>
++
++#define DRIVER_NAME			"spi-ralink"
++#define RALINK_NUM_CHIPSELECTS		1 /* only one slave is supported*/
++#define RALINK_SPI_WAIT_RDY_MAX_LOOP	2000 /* in usec */
++
++#define RAMIPS_SPI_STAT			0x00
++#define RAMIPS_SPI_CFG			0x10
++#define RAMIPS_SPI_CTL			0x14
++#define RAMIPS_SPI_DATA			0x20
++
++/* SPISTAT register bit field */
++#define SPISTAT_BUSY			BIT(0)
++
++/* SPICFG register bit field */
++#define SPICFG_LSBFIRST			0
++#define SPICFG_MSBFIRST			BIT(8)
++#define SPICFG_SPICLKPOL		BIT(6)
++#define SPICFG_RXCLKEDGE_FALLING	BIT(5)
++#define SPICFG_TXCLKEDGE_FALLING	BIT(4)
++#define SPICFG_SPICLK_PRESCALE_MASK	0x7
++#define SPICFG_SPICLK_DIV2		0
++#define SPICFG_SPICLK_DIV4		1
++#define SPICFG_SPICLK_DIV8		2
++#define SPICFG_SPICLK_DIV16		3
++#define SPICFG_SPICLK_DIV32		4
++#define SPICFG_SPICLK_DIV64		5
++#define SPICFG_SPICLK_DIV128		6
++#define SPICFG_SPICLK_DISABLE		7
++
++/* SPICTL register bit field */
++#define SPICTL_HIZSDO			BIT(3)
++#define SPICTL_STARTWR			BIT(2)
++#define SPICTL_STARTRD			BIT(1)
++#define SPICTL_SPIENA			BIT(0)
++
++#ifdef DEBUG
++#define spi_debug(args...) printk(args)
++#else
++#define spi_debug(args...)
++#endif
++
++struct ralink_spi {
++	struct spi_master	*master;
++	void __iomem		*base;
++	unsigned int		sys_freq;
++	unsigned int		speed;
++	struct clk		*clk;
++};
++
++static inline struct ralink_spi *spidev_to_ralink_spi(struct spi_device *spi)
++{
++	return spi_master_get_devdata(spi->master);
++}
++
++static inline u32 ralink_spi_read(struct ralink_spi *rs, u32 reg)
++{
++	return ioread32(rs->base + reg);
++}
++
++static inline void ralink_spi_write(struct ralink_spi *rs, u32 reg, u32 val)
++{
++	iowrite32(val, rs->base + reg);
++}
++
++static inline void ralink_spi_setbits(struct ralink_spi *rs, u32 reg, u32 mask)
++{
++	void __iomem *addr = rs->base + reg;
++	u32 val;
++
++	val = ioread32(addr);
++	val |= mask;
++	iowrite32(val, addr);
++}
++
++static inline void ralink_spi_clrbits(struct ralink_spi *rs, u32 reg, u32 mask)
++{
++	void __iomem *addr = rs->base + reg;
++	u32 val;
++
++	val = ioread32(addr);
++	val &= ~mask;
++	iowrite32(val, addr);
++}
++
++static int ralink_spi_baudrate_set(struct spi_device *spi, unsigned int speed)
++{
++	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
++	u32 rate;
++	u32 prescale;
++	u32 reg;
++
++	spi_debug("%s: speed:%u\n", __func__, speed);
++
++	/*
++	 * the supported rates are: 2, 4, 8, ... 128
++	 * round up as we look for equal or less speed
++	 */
++	rate = DIV_ROUND_UP(rs->sys_freq, speed);
++	spi_debug("%s: rate-1:%u\n", __func__, rate);
++	rate = roundup_pow_of_two(rate);
++	spi_debug("%s: rate-2:%u\n", __func__, rate);
++
++	/* check if requested speed is too small */
++	if (rate > 128)
++		return -EINVAL;
++
++	if (rate < 2)
++		rate = 2;
++
++	/* Convert the rate to SPI clock divisor value.	*/
++	prescale = ilog2(rate/2);
++	spi_debug("%s: prescale:%u\n", __func__, prescale);
++
++	reg = ralink_spi_read(rs, RAMIPS_SPI_CFG);
++	reg = ((reg & ~SPICFG_SPICLK_PRESCALE_MASK) | prescale);
++	ralink_spi_write(rs, RAMIPS_SPI_CFG, reg);
++	rs->speed = speed;
++	return 0;
++}
++
++/*
++ * called only when no transfer is active on the bus
++ */
++static int
++ralink_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
++{
++	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
++	unsigned int speed = spi->max_speed_hz;
++	int rc;
++	unsigned int bits_per_word = 8;
++
++	if ((t != NULL) && t->speed_hz)
++		speed = t->speed_hz;
++
++	if ((t != NULL) && t->bits_per_word)
++		bits_per_word = t->bits_per_word;
++
++	if (rs->speed != speed) {
++		spi_debug("%s: speed_hz:%u\n", __func__, speed);
++		rc = ralink_spi_baudrate_set(spi, speed);
++		if (rc)
++			return rc;
++	}
++
++	if (bits_per_word != 8) {
++		spi_debug("%s: bad bits_per_word: %u\n", __func__,
++			  bits_per_word);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static void ralink_spi_set_cs(struct ralink_spi *rs, int enable)
++{
++	if (enable)
++		ralink_spi_clrbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++	else
++		ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_SPIENA);
++}
++
++static inline int ralink_spi_wait_till_ready(struct ralink_spi *rs)
++{
++	int i;
++
++	for (i = 0; i < RALINK_SPI_WAIT_RDY_MAX_LOOP; i++) {
++		u32 status;
++
++		status = ralink_spi_read(rs, RAMIPS_SPI_STAT);
++		if ((status & SPISTAT_BUSY) == 0)
++			return 0;
++
++		udelay(1);
++	}
++
++	return -ETIMEDOUT;
++}
++
++static unsigned int
++ralink_spi_write_read(struct spi_device *spi, struct spi_transfer *xfer)
++{
++	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
++	unsigned count = 0;
++	u8 *rx = xfer->rx_buf;
++	const u8 *tx = xfer->tx_buf;
++	int err;
++
++	spi_debug("%s(%d): %s %s\n", __func__, xfer->len,
++		  (tx != NULL) ? "tx" : "  ",
++		  (rx != NULL) ? "rx" : "  ");
++
++	if (tx) {
++		for (count = 0; count < xfer->len; count++) {
++			ralink_spi_write(rs, RAMIPS_SPI_DATA, tx[count]);
++			ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTWR);
++			err = ralink_spi_wait_till_ready(rs);
++			if (err) {
++				dev_err(&spi->dev, "TX failed, err=%d\n", err);
++				goto out;
++			}
++		}
++	}
++
++	if (rx) {
++		for (count = 0; count < xfer->len; count++) {
++			ralink_spi_setbits(rs, RAMIPS_SPI_CTL, SPICTL_STARTRD);
++			err = ralink_spi_wait_till_ready(rs);
++			if (err) {
++				dev_err(&spi->dev, "RX failed, err=%d\n", err);
++				goto out;
++			}
++			rx[count] = (u8) ralink_spi_read(rs, RAMIPS_SPI_DATA);
++		}
++	}
++
++out:
++	return count;
++}
++
++static int ralink_spi_transfer_one_message(struct spi_master *master,
++					   struct spi_message *m)
++{
++	struct ralink_spi *rs = spi_master_get_devdata(master);
++	struct spi_device *spi = m->spi;
++	struct spi_transfer *t = NULL;
++	int par_override = 0;
++	int status = 0;
++	int cs_active = 0;
++
++	/* Load defaults */
++	status = ralink_spi_setup_transfer(spi, NULL);
++	if (status < 0)
++		goto msg_done;
++
++	list_for_each_entry(t, &m->transfers, transfer_list) {
++		unsigned int bits_per_word = spi->bits_per_word;
++
++		if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
++			dev_err(&spi->dev,
++				"message rejected: invalid transfer data buffers\n");
++			status = -EIO;
++			goto msg_done;
++		}
++
++		if (t->bits_per_word)
++			bits_per_word = t->bits_per_word;
++
++		if (bits_per_word != 8) {
++			dev_err(&spi->dev,
++				"message rejected: invalid transfer bits_per_word (%d bits)\n",
++				bits_per_word);
++			status = -EIO;
++			goto msg_done;
++		}
++
++		if (t->speed_hz && t->speed_hz < (rs->sys_freq / 128)) {
++			dev_err(&spi->dev,
++				"message rejected: device min speed (%d Hz) exceeds required transfer speed (%d Hz)\n",
++				(rs->sys_freq / 128), t->speed_hz);
++			status = -EIO;
++			goto msg_done;
++		}
++
++		if (par_override || t->speed_hz || t->bits_per_word) {
++			par_override = 1;
++			status = ralink_spi_setup_transfer(spi, t);
++			if (status < 0)
++				goto msg_done;
++			if (!t->speed_hz && !t->bits_per_word)
++				par_override = 0;
++		}
++
++		if (!cs_active) {
++			ralink_spi_set_cs(rs, 1);
++			cs_active = 1;
++		}
++
++		if (t->len)
++			m->actual_length += ralink_spi_write_read(spi, t);
++
++		if (t->delay_usecs)
++			udelay(t->delay_usecs);
++
++		if (t->cs_change) {
++			ralink_spi_set_cs(rs, 0);
++			cs_active = 0;
++		}
++	}
++
++msg_done:
++	if (cs_active)
++		ralink_spi_set_cs(rs, 0);
++
++	m->status = status;
++	spi_finalize_current_message(master);
++
++	return 0;
++}
++
++static int ralink_spi_setup(struct spi_device *spi)
++{
++	struct ralink_spi *rs = spidev_to_ralink_spi(spi);
++
++	if ((spi->max_speed_hz == 0) ||
++	    (spi->max_speed_hz > (rs->sys_freq / 2)))
++		spi->max_speed_hz = (rs->sys_freq / 2);
++
++	if (spi->max_speed_hz < (rs->sys_freq / 128)) {
++		dev_err(&spi->dev, "setup: requested speed is too low %d Hz\n",
++			spi->max_speed_hz);
++		return -EINVAL;
++	}
++
++	if (spi->bits_per_word != 0 && spi->bits_per_word != 8) {
++		dev_err(&spi->dev,
++			"setup: requested bits per words - os wrong %d bpw\n",
++			spi->bits_per_word);
++		return -EINVAL;
++	}
++
++	if (spi->bits_per_word == 0)
++		spi->bits_per_word = 8;
++
++	/*
++	 * baudrate & width will be set ralink_spi_setup_transfer
++	 */
++	return 0;
++}
++
++static void ralink_spi_reset(struct ralink_spi *rs)
++{
++	ralink_spi_write(rs, RAMIPS_SPI_CFG,
++			 SPICFG_MSBFIRST | SPICFG_TXCLKEDGE_FALLING |
++			 SPICFG_SPICLK_DIV16 | SPICFG_SPICLKPOL);
++	ralink_spi_write(rs, RAMIPS_SPI_CTL, SPICTL_HIZSDO | SPICTL_SPIENA);
++}
++
++static int ralink_spi_probe(struct platform_device *pdev)
++{
++	struct spi_master *master;
++	struct ralink_spi *rs;
++	struct resource *r;
++	int status = 0;
++
++	master = spi_alloc_master(&pdev->dev, sizeof(*rs));
++	if (master == NULL) {
++		dev_dbg(&pdev->dev, "master allocation failed\n");
++		return -ENOMEM;
++	}
++
++	//if (pdev->id != -1)
++		master->bus_num = 0;
++
++	/* we support only mode 0, and no options */
++	master->mode_bits = 0;
++
++	master->setup = ralink_spi_setup;
++	master->transfer_one_message = ralink_spi_transfer_one_message;
++	master->num_chipselect = RALINK_NUM_CHIPSELECTS;
++	master->dev.of_node = pdev->dev.of_node;
++
++	dev_set_drvdata(&pdev->dev, master);
++
++	rs = spi_master_get_devdata(master);
++	rs->master = master;
++
++	rs->clk = clk_get(&pdev->dev, NULL);
++	if (IS_ERR(rs->clk)) {
++		status = PTR_ERR(rs->clk);
++		dev_err(&pdev->dev, "unable to get SYS clock, err=%d\n",
++			status);
++		goto out_put_master;
++	}
++
++	status = clk_enable(rs->clk);
++	if (status)
++		goto out_put_clk;
++
++	rs->sys_freq = clk_get_rate(rs->clk);
++	spi_debug("%s: sys_freq: %u\n", __func__, rs->sys_freq);
++
++	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (r == NULL) {
++		status = -ENODEV;
++		goto out_disable_clk;
++	}
++
++	rs->base = devm_request_and_ioremap(&pdev->dev, r);
++	if (!rs->base) {
++		status = -EADDRNOTAVAIL;
++		goto out_disable_clk;
++	}
++
++	device_reset(&pdev->dev);
++
++	ralink_spi_reset(rs);
++
++	status = spi_register_master(master);
++	if (status)
++		goto out_disable_clk;
++
++	return 0;
++
++out_disable_clk:
++	clk_disable(rs->clk);
++out_put_clk:
++	clk_put(rs->clk);
++out_put_master:
++	spi_master_put(master);
++	return status;
++}
++
++static int ralink_spi_remove(struct platform_device *pdev)
++{
++	struct spi_master *master;
++	struct ralink_spi *rs;
++
++	master = dev_get_drvdata(&pdev->dev);
++	rs = spi_master_get_devdata(master);
++
++	clk_disable(rs->clk);
++	clk_put(rs->clk);
++	spi_unregister_master(master);
++
++	return 0;
++}
++
++MODULE_ALIAS("platform:" DRIVER_NAME);
++
++static const struct of_device_id ralink_spi_match[] = {
++	{ .compatible = "ralink,rt2880-spi" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ralink_spi_match);
++
++static struct platform_driver ralink_spi_driver = {
++	.driver = {
++		.name = DRIVER_NAME,
++		.owner = THIS_MODULE,
++		.of_match_table = ralink_spi_match,
++	},
++	.probe = ralink_spi_probe,
++	.remove = ralink_spi_remove,
++};
++
++module_platform_driver(ralink_spi_driver);
++
++MODULE_DESCRIPTION("Ralink SPI driver");
++MODULE_AUTHOR("Sergiy <piratfm@gmail.com>");
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
++MODULE_LICENSE("GPL");
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0025-watchdog-adds-ralink-wdt.patch b/target/linux/ramips/patches-3.10/0025-watchdog-adds-ralink-wdt.patch
new file mode 100644
index 0000000..63e54c6
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0025-watchdog-adds-ralink-wdt.patch
@@ -0,0 +1,274 @@
+From f51b3b84af840ea52170ae6444ddee26ec74f7a9 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 22 Apr 2013 23:23:07 +0200
+Subject: [PATCH 25/33] watchdog: adds ralink wdt
+
+Adds the watchdog driver for ralink SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/mt7620.c     |    1 +
+ drivers/watchdog/Kconfig      |    7 ++
+ drivers/watchdog/Makefile     |    1 +
+ drivers/watchdog/rt2880_wdt.c |  207 +++++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 216 insertions(+)
+ create mode 100644 drivers/watchdog/rt2880_wdt.c
+
+diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
+index 6f6b1c8..14c28b0 100644
+--- a/arch/mips/ralink/mt7620.c
++++ b/arch/mips/ralink/mt7620.c
+@@ -182,6 +182,7 @@ void __init ralink_clk_init(void)
+ 
+ 	ralink_clk_add("cpu", cpu_rate);
+ 	ralink_clk_add("10000100.timer", 40000000);
++	ralink_clk_add("10000120.watchdog", 40000000);
+ 	ralink_clk_add("10000500.uart", 40000000);
+ 	ralink_clk_add("10000b00.spi", 40000000);
+ 	ralink_clk_add("10000c00.uartlite", 40000000);
+diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
+index e89fc31..5e34760 100644
+--- a/drivers/watchdog/Kconfig
++++ b/drivers/watchdog/Kconfig
+@@ -1104,6 +1104,13 @@ config LANTIQ_WDT
+ 	help
+ 	  Hardware driver for the Lantiq SoC Watchdog Timer.
+ 
++config RALINK_WDT
++	tristate "Ralink SoC watchdog"
++	select WATCHDOG_CORE
++	depends on RALINK
++	help
++	  Hardware driver for the Ralink SoC Watchdog Timer.
++
+ # PARISC Architecture
+ 
+ # POWERPC Architecture
+diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
+index a300b94..2681e3d 100644
+--- a/drivers/watchdog/Makefile
++++ b/drivers/watchdog/Makefile
+@@ -134,6 +134,7 @@ obj-$(CONFIG_TXX9_WDT) += txx9wdt.o
+ obj-$(CONFIG_OCTEON_WDT) += octeon-wdt.o
+ octeon-wdt-y := octeon-wdt-main.o octeon-wdt-nmi.o
+ obj-$(CONFIG_LANTIQ_WDT) += lantiq_wdt.o
++obj-$(CONFIG_RALINK_WDT) += rt2880_wdt.o
+ 
+ # PARISC Architecture
+ 
+diff --git a/drivers/watchdog/rt2880_wdt.c b/drivers/watchdog/rt2880_wdt.c
+new file mode 100644
+index 0000000..ebba535
+--- /dev/null
++++ b/drivers/watchdog/rt2880_wdt.c
+@@ -0,0 +1,207 @@
++/*
++ * Ralink RT288x/RT3xxx/MT76xx built-in hardware watchdog timer
++ *
++ * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
++ * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ *
++ * This driver was based on: drivers/watchdog/softdog.c
++ *
++ * This program is free software; you can redistribute it and/or modify it
++ * under the terms of the GNU General Public License version 2 as published
++ * by the Free Software Foundation.
++ */
++
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/watchdog.h>
++#include <linux/miscdevice.h>
++#include <linux/moduleparam.h>
++#include <linux/platform_device.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define SYSC_RSTSTAT			0x38
++#define WDT_RST_CAUSE			BIT(1)
++
++#define RALINK_WDT_TIMEOUT		30
++#define RALINK_WDT_PRESCALE		65536
++
++#define TIMER_REG_TMR1LOAD		0x00
++#define TIMER_REG_TMR1CTL		0x08
++
++#define TMRSTAT_TMR1RST			BIT(5)
++
++#define TMR1CTL_ENABLE			BIT(7)
++#define TMR1CTL_MODE_SHIFT		4
++#define TMR1CTL_MODE_MASK		0x3
++#define TMR1CTL_MODE_FREE_RUNNING	0x0
++#define TMR1CTL_MODE_PERIODIC		0x1
++#define TMR1CTL_MODE_TIMEOUT		0x2
++#define TMR1CTL_MODE_WDT		0x3
++#define TMR1CTL_PRESCALE_MASK		0xf
++#define TMR1CTL_PRESCALE_65536		0xf
++
++static struct clk *rt288x_wdt_clk;
++static unsigned long rt288x_wdt_freq;
++static void __iomem *rt288x_wdt_base;
++
++static bool nowayout = WATCHDOG_NOWAYOUT;
++module_param(nowayout, bool, 0);
++MODULE_PARM_DESC(nowayout,
++		"Watchdog cannot be stopped once started (default="
++		__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
++
++static inline void rt_wdt_w32(unsigned reg, u32 val)
++{
++	iowrite32(val, rt288x_wdt_base + reg);
++}
++
++static inline u32 rt_wdt_r32(unsigned reg)
++{
++	return ioread32(rt288x_wdt_base + reg);
++}
++
++static int rt288x_wdt_ping(struct watchdog_device *w)
++{
++        rt_wdt_w32(TIMER_REG_TMR1LOAD, w->timeout * rt288x_wdt_freq);
++
++	return 0;
++}
++
++static int rt288x_wdt_start(struct watchdog_device *w)
++{
++	u32 t;
++
++	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++	t &= ~(TMR1CTL_MODE_MASK << TMR1CTL_MODE_SHIFT |
++		TMR1CTL_PRESCALE_MASK);
++	t |= (TMR1CTL_MODE_WDT << TMR1CTL_MODE_SHIFT |
++		TMR1CTL_PRESCALE_65536);
++	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++	rt288x_wdt_ping(w);
++
++	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++	t |= TMR1CTL_ENABLE;
++	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++	return 0;
++}
++
++static int rt288x_wdt_stop(struct watchdog_device *w)
++{
++	u32 t;
++
++	rt288x_wdt_ping(w);
++
++	t = rt_wdt_r32(TIMER_REG_TMR1CTL);
++	t &= ~TMR1CTL_ENABLE;
++	rt_wdt_w32(TIMER_REG_TMR1CTL, t);
++
++	return 0;
++}
++
++static int rt288x_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
++{
++	w->timeout = t;
++	rt288x_wdt_ping(w);
++
++	return 0;
++}
++
++static int rt288x_wdt_bootcause(void)
++{
++	if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
++		return WDIOF_CARDRESET;
++
++	return 0;
++}
++
++static struct watchdog_info rt288x_wdt_info = {
++	.identity = "Ralink Watchdog",
++	.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
++};
++
++static struct watchdog_ops rt288x_wdt_ops = {
++	.owner = THIS_MODULE,
++	.start = rt288x_wdt_start,
++	.stop = rt288x_wdt_stop,
++	.ping = rt288x_wdt_ping,
++	.set_timeout = rt288x_wdt_set_timeout,
++};
++
++static struct watchdog_device rt288x_wdt_dev = {
++	.info = &rt288x_wdt_info,
++	.ops = &rt288x_wdt_ops,
++	.min_timeout = 1,
++};
++
++static int rt288x_wdt_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	int ret;
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++        rt288x_wdt_base = devm_request_and_ioremap(&pdev->dev, res);
++	if (IS_ERR(rt288x_wdt_base))
++		return PTR_ERR(rt288x_wdt_base);
++
++	rt288x_wdt_clk = devm_clk_get(&pdev->dev, NULL);
++	if (IS_ERR(rt288x_wdt_clk))
++		return PTR_ERR(rt288x_wdt_clk);
++
++	device_reset(&pdev->dev);
++
++	rt288x_wdt_freq = clk_get_rate(rt288x_wdt_clk) / RALINK_WDT_PRESCALE;
++
++	rt288x_wdt_dev.dev = &pdev->dev;
++	rt288x_wdt_dev.bootstatus = rt288x_wdt_bootcause();
++
++	rt288x_wdt_dev.timeout = rt288x_wdt_dev.max_timeout = (0xfffful / rt288x_wdt_freq);
++
++	watchdog_set_nowayout(&rt288x_wdt_dev, nowayout);
++
++	ret = watchdog_register_device(&rt288x_wdt_dev);
++	if (!ret)
++		dev_info(&pdev->dev, "Initialized\n");
++
++	return 0;
++}
++
++static int rt288x_wdt_remove(struct platform_device *pdev)
++{
++	watchdog_unregister_device(&rt288x_wdt_dev);
++
++	return 0;
++}
++
++static void rt288x_wdt_shutdown(struct platform_device *pdev)
++{
++	rt288x_wdt_stop(&rt288x_wdt_dev);
++}
++
++static const struct of_device_id rt288x_wdt_match[] = {
++	{ .compatible = "ralink,rt2880-wdt" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
++
++static struct platform_driver rt288x_wdt_driver = {
++	.probe		= rt288x_wdt_probe,
++	.remove		= rt288x_wdt_remove,
++	.shutdown	= rt288x_wdt_shutdown,
++	.driver		= {
++		.name		= KBUILD_MODNAME,
++		.owner		= THIS_MODULE,
++		.of_match_table	= rt288x_wdt_match,
++	},
++};
++
++module_platform_driver(rt288x_wdt_driver);
++
++MODULE_DESCRIPTION("MediaTek/Ralink RT288x/RT3xxx hardware watchdog driver");
++MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org");
++MODULE_LICENSE("GPL v2");
++MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0026-i2c-MIPS-adds-ralink-I2C-driver.patch b/target/linux/ramips/patches-3.10/0026-i2c-MIPS-adds-ralink-I2C-driver.patch
new file mode 100644
index 0000000..bee64f8
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0026-i2c-MIPS-adds-ralink-I2C-driver.patch
@@ -0,0 +1,358 @@
+From 4596818bca07e0928168970839e08875cf51b4cc Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 29 Apr 2013 14:40:43 +0200
+Subject: [PATCH 26/33] i2c: MIPS: adds ralink I2C driver
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ .../devicetree/bindings/i2c/i2c-ralink.txt         |   27 ++
+ drivers/i2c/busses/Kconfig                         |    4 +
+ drivers/i2c/busses/Makefile                        |    1 +
+ drivers/i2c/busses/i2c-ralink.c                    |  274 ++++++++++++++++++++
+ 4 files changed, 306 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+ create mode 100644 drivers/i2c/busses/i2c-ralink.c
+
+diff --git a/Documentation/devicetree/bindings/i2c/i2c-ralink.txt b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+new file mode 100644
+index 0000000..8fa8ac3
+--- /dev/null
++++ b/Documentation/devicetree/bindings/i2c/i2c-ralink.txt
+@@ -0,0 +1,27 @@
++I2C for Ralink platforms
++
++Required properties :
++- compatible : Must be "link,rt3052-i2c"
++- reg: physical base address of the controller and length of memory mapped
++     region.
++- #address-cells = <1>;
++- #size-cells = <0>;
++
++Optional properties:
++- Child nodes conforming to i2c bus binding
++
++Example :
++
++palmbus@10000000 {
++	i2c@900 {
++		compatible = "link,rt3052-i2c";
++		reg = <0x900 0x100>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		hwmon@4b {
++			compatible = "national,lm92";
++			reg = <0x4b>;
++		};
++	};
++};
+diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
+index 631736e..e2c2381 100644
+--- a/drivers/i2c/busses/Kconfig
++++ b/drivers/i2c/busses/Kconfig
+@@ -628,6 +628,10 @@ config I2C_PXA_SLAVE
+ 	  is necessary for systems where the PXA may be a target on the
+ 	  I2C bus.
+ 
++config I2C_RALINK
++	tristate "Ralink I2C Controller"
++	select OF_I2C
++
+ config HAVE_S3C2410_I2C
+ 	bool
+ 	help
+diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
+index 8f4fc23..7e39a13 100644
+--- a/drivers/i2c/busses/Makefile
++++ b/drivers/i2c/busses/Makefile
+@@ -62,6 +62,7 @@ obj-$(CONFIG_I2C_PNX)		+= i2c-pnx.o
+ obj-$(CONFIG_I2C_PUV3)		+= i2c-puv3.o
+ obj-$(CONFIG_I2C_PXA)		+= i2c-pxa.o
+ obj-$(CONFIG_I2C_PXA_PCI)	+= i2c-pxa-pci.o
++obj-$(CONFIG_I2C_RALINK)	+= i2c-ralink.o
+ obj-$(CONFIG_I2C_S3C2410)	+= i2c-s3c2410.o
+ obj-$(CONFIG_I2C_S6000)		+= i2c-s6000.o
+ obj-$(CONFIG_I2C_SH7760)	+= i2c-sh7760.o
+diff --git a/drivers/i2c/busses/i2c-ralink.c b/drivers/i2c/busses/i2c-ralink.c
+new file mode 100644
+index 0000000..f4dc13d
+--- /dev/null
++++ b/drivers/i2c/busses/i2c-ralink.c
+@@ -0,0 +1,274 @@
++/*
++ * drivers/i2c/busses/i2c-ralink.c
++ *
++ * Copyright (C) 2013 Steven Liu <steven_liu@mediatek.com>
++ *
++ * This software is licensed under the terms of the GNU General Public
++ * License version 2, as published by the Free Software Foundation, and
++ * may be copied, distributed, and modified under those terms.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ */
++
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/reset.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/errno.h>
++#include <linux/platform_device.h>
++#include <linux/i2c.h>
++#include <linux/io.h>
++#include <linux/of_i2c.h>
++#include <linux/err.h>
++
++#include <asm/mach-ralink/ralink_regs.h>
++
++#define REG_CONFIG_REG		0x00
++#define REG_CLKDIV_REG		0x04
++#define REG_DEVADDR_REG		0x08
++#define REG_ADDR_REG		0x0C
++#define REG_DATAOUT_REG		0x10
++#define REG_DATAIN_REG		0x14
++#define REG_STATUS_REG		0x18
++#define REG_STARTXFR_REG	0x1C
++#define REG_BYTECNT_REG		0x20
++
++#define I2C_STARTERR		BIT(4)
++#define I2C_ACKERR		BIT(3)
++#define I2C_DATARDY		BIT(2)
++#define I2C_SDOEMPTY		BIT(1)
++#define I2C_BUSY		BIT(0)
++
++#define I2C_DEVADLEN_7		(6 << 2)
++#define I2C_ADDRDIS		BIT(1)
++
++#define I2C_RETRY		0x400
++
++#define CLKDIV_VALUE		200 // clock rate is 40M, 40M / (200*2) = 100k (standard i2c bus rate).
++//#define CLKDIV_VALUE		50 // clock rate is 40M, 40M / (50*2) = 400k (fast i2c bus rate).
++
++#define READ_CMD		0x01
++#define WRITE_CMD		0x00
++#define READ_BLOCK              64
++
++static void __iomem *membase;
++static struct i2c_adapter *adapter;
++
++static void rt_i2c_w32(u32 val, unsigned reg)
++{
++	iowrite32(val, membase + reg);
++}
++
++static u32 rt_i2c_r32(unsigned reg)
++{
++	return ioread32(membase + reg);
++}
++
++static inline int rt_i2c_wait_rx_done(void)
++{
++	int retries = I2C_RETRY;
++
++	do {
++		if (!retries--)
++			break;
++	} while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_DATARDY));
++
++	return (retries < 0);
++}
++
++static inline int rt_i2c_wait_idle(void)
++{
++	int retries = I2C_RETRY;
++
++	do {
++		if (!retries--)
++			break;
++	} while(rt_i2c_r32(REG_STATUS_REG) & I2C_BUSY);
++
++	return (retries < 0);
++}
++
++static inline int rt_i2c_wait_tx_done(void)
++{
++	int retries = I2C_RETRY;
++
++	do {
++		if (!retries--)
++			break;
++	} while(!(rt_i2c_r32(REG_STATUS_REG) & I2C_SDOEMPTY));
++
++	return (retries < 0);
++}
++
++static int rt_i2c_handle_msg(struct i2c_adapter *a, struct i2c_msg* msg)
++{
++	int i = 0, j = 0, pos = 0;
++	int nblock = msg->len / READ_BLOCK;
++        int rem = msg->len % READ_BLOCK;
++
++	if (msg->flags & I2C_M_TEN) {
++		printk("10 bits addr not supported\n");
++		return -EINVAL;
++	}
++
++	if (msg->flags & I2C_M_RD) {
++		for (i = 0; i < nblock; i++) {
++			rt_i2c_wait_idle();
++			rt_i2c_w32(READ_BLOCK - 1, REG_BYTECNT_REG);
++			rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
++			for (j = 0; j < READ_BLOCK; j++) {
++				if (rt_i2c_wait_rx_done())
++					return -1;
++				msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
++			}
++		}
++
++		rt_i2c_wait_idle();
++		rt_i2c_w32(rem - 1, REG_BYTECNT_REG);
++		rt_i2c_w32(READ_CMD, REG_STARTXFR_REG);
++		for (i = 0; i < rem; i++) {
++			if (rt_i2c_wait_rx_done())
++				return -1;
++			msg->buf[pos++] = rt_i2c_r32(REG_DATAIN_REG);
++		}
++	} else {
++		rt_i2c_wait_idle();
++		rt_i2c_w32(msg->len - 1, REG_BYTECNT_REG);
++		for (i = 0; i < msg->len; i++) {
++			rt_i2c_w32(msg->buf[i], REG_DATAOUT_REG);
++			rt_i2c_w32(WRITE_CMD, REG_STARTXFR_REG);
++			if (rt_i2c_wait_tx_done())
++				return -1;
++		}
++	}
++
++	return 0;
++}
++
++static int rt_i2c_master_xfer(struct i2c_adapter *a, struct i2c_msg *m, int n)
++{
++	int i = 0;
++	int ret = 0;
++
++	if (rt_i2c_wait_idle()) {
++		printk("i2c transfer failed\n");
++		return 0;
++	}
++
++	device_reset(a->dev.parent);
++
++	rt_i2c_w32(m->addr, REG_DEVADDR_REG);
++	rt_i2c_w32(I2C_DEVADLEN_7 | I2C_ADDRDIS, REG_CONFIG_REG);
++	rt_i2c_w32(CLKDIV_VALUE, REG_CLKDIV_REG);
++
++	for (i = 0; i < n && !ret; i++)
++		ret = rt_i2c_handle_msg(a, &m[i]);
++
++	if (ret) {
++		printk("i2c transfer failed\n");
++		return 0;
++	}
++
++	return n;
++}
++
++static u32 rt_i2c_func(struct i2c_adapter *a)
++{
++	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
++}
++
++static const struct i2c_algorithm rt_i2c_algo = {
++	.master_xfer	= rt_i2c_master_xfer,
++	.functionality	= rt_i2c_func,
++};
++
++static int rt_i2c_probe(struct platform_device *pdev)
++{
++	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	int ret;
++
++	if (!res) {
++		dev_err(&pdev->dev, "no memory resource found\n");
++		return -ENODEV;
++	}
++
++	adapter = devm_kzalloc(&pdev->dev, sizeof(struct i2c_adapter), GFP_KERNEL);
++	if (!adapter) {
++		dev_err(&pdev->dev, "failed to allocate i2c_adapter\n");
++		return -ENOMEM;
++	}
++
++	membase = devm_request_and_ioremap(&pdev->dev, res);
++	if (IS_ERR(membase))
++		return PTR_ERR(membase);
++
++	strlcpy(adapter->name, dev_name(&pdev->dev), sizeof(adapter->name));
++	adapter->owner = THIS_MODULE;
++	adapter->nr = pdev->id;
++	adapter->timeout = HZ;
++	adapter->algo = &rt_i2c_algo;
++	adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
++	adapter->dev.parent = &pdev->dev;
++	adapter->dev.of_node = pdev->dev.of_node;
++
++	ret = i2c_add_numbered_adapter(adapter);
++	if (ret)
++		return ret;
++
++	of_i2c_register_devices(adapter);
++
++	platform_set_drvdata(pdev, adapter);
++
++	dev_info(&pdev->dev, "loaded\n");
++
++	return 0;
++}
++
++static int rt_i2c_remove(struct platform_device *pdev)
++{
++	platform_set_drvdata(pdev, NULL);
++
++	return 0;
++}
++
++static const struct of_device_id i2c_rt_dt_ids[] = {
++	{ .compatible = "ralink,rt2880-i2c", },
++	{ /* sentinel */ }
++};
++
++MODULE_DEVICE_TABLE(of, i2c_rt_dt_ids);
++
++static struct platform_driver rt_i2c_driver = {
++	.probe		= rt_i2c_probe,
++	.remove		= rt_i2c_remove,
++	.driver		= {
++		.owner	= THIS_MODULE,
++		.name	= "i2c-ralink",
++		.of_match_table = i2c_rt_dt_ids,
++	},
++};
++
++static int __init i2c_rt_init (void)
++{
++	return platform_driver_register(&rt_i2c_driver);
++}
++subsys_initcall(i2c_rt_init);
++
++static void __exit i2c_rt_exit (void)
++{
++	platform_driver_unregister(&rt_i2c_driver);
++}
++
++module_exit (i2c_rt_exit);
++
++MODULE_AUTHOR("Steven Liu <steven_liu@mediatek.com>");
++MODULE_DESCRIPTION("Ralink I2c host driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:Ralink-I2C");
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0027-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch b/target/linux/ramips/patches-3.10/0027-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
new file mode 100644
index 0000000..50ab088
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0027-mmc-MIPS-ralink-add-sdhci-for-mt7620a-SoC.patch
@@ -0,0 +1,3446 @@
+From de1defdad7554d6ba885a6d3dc55105e01e9a07e Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Thu, 2 May 2013 14:59:01 +0200
+Subject: [PATCH 27/33] mmc: MIPS: ralink: add sdhci for mt7620a SoC
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ drivers/mmc/host/Kconfig        |   11 +
+ drivers/mmc/host/Makefile       |    1 +
+ drivers/mmc/host/mt6575_sd.h    | 1068 ++++++++++++++++++
+ drivers/mmc/host/sdhci-mt7620.c | 2314 +++++++++++++++++++++++++++++++++++++++
+ 4 files changed, 3394 insertions(+)
+ create mode 100644 drivers/mmc/host/mt6575_sd.h
+ create mode 100644 drivers/mmc/host/sdhci-mt7620.c
+
+diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
+index 9ab8f8d..ef6bf59 100644
+--- a/drivers/mmc/host/Kconfig
++++ b/drivers/mmc/host/Kconfig
+@@ -260,6 +260,17 @@ config MMC_SDHCI_BCM2835
+ 
+ 	  If unsure, say N.
+ 
++config MMC_SDHCI_MT7620
++	tristate "SDHCI platform support for the MT7620 SD/MMC Controller"
++	depends on SOC_MT7620
++	depends on MMC_SDHCI_PLTFM
++	select MMC_SDHCI_IO_ACCESSORS
++	help
++	  This selects the BCM2835 SD/MMC controller. If you have a BCM2835
++	  platform with SD or MMC devices, say Y or M here.
++
++	  If unsure, say N.
++
+ config MMC_OMAP
+ 	tristate "TI OMAP Multimedia Card Interface support"
+ 	depends on ARCH_OMAP
+diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
+index cd32280..c800bed 100644
+--- a/drivers/mmc/host/Makefile
++++ b/drivers/mmc/host/Makefile
+@@ -61,6 +61,7 @@ obj-$(CONFIG_MMC_SDHCI_TEGRA)		+= sdhci-tegra.o
+ obj-$(CONFIG_MMC_SDHCI_OF_ESDHC)	+= sdhci-of-esdhc.o
+ obj-$(CONFIG_MMC_SDHCI_OF_HLWD)		+= sdhci-of-hlwd.o
+ obj-$(CONFIG_MMC_SDHCI_BCM2835)		+= sdhci-bcm2835.o
++obj-$(CONFIG_MMC_SDHCI_MT7620)		+= sdhci-mt7620.o
+ 
+ ifeq ($(CONFIG_CB710_DEBUG),y)
+ 	CFLAGS-cb710-mmc	+= -DDEBUG
+diff --git a/drivers/mmc/host/mt6575_sd.h b/drivers/mmc/host/mt6575_sd.h
+new file mode 100644
+index 0000000..406382c
+--- /dev/null
++++ b/drivers/mmc/host/mt6575_sd.h
+@@ -0,0 +1,1068 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ */
++/* MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#ifndef MT6575_SD_H
++#define MT6575_SD_H
++
++#include <linux/bitops.h>
++#include <linux/mmc/host.h>
++
++// #include <mach/mt6575_reg_base.h> /* --- by chhung */
++
++typedef void (*sdio_irq_handler_t)(void*);  /* external irq handler */
++typedef void (*pm_callback_t)(pm_message_t state, void *data);
++
++#define MSDC_CD_PIN_EN      (1 << 0)  /* card detection pin is wired   */
++#define MSDC_WP_PIN_EN      (1 << 1)  /* write protection pin is wired */
++#define MSDC_RST_PIN_EN     (1 << 2)  /* emmc reset pin is wired       */
++#define MSDC_SDIO_IRQ       (1 << 3)  /* use internal sdio irq (bus)   */
++#define MSDC_EXT_SDIO_IRQ   (1 << 4)  /* use external sdio irq         */
++#define MSDC_REMOVABLE      (1 << 5)  /* removable slot                */
++#define MSDC_SYS_SUSPEND    (1 << 6)  /* suspended by system           */
++#define MSDC_HIGHSPEED      (1 << 7)  /* high-speed mode support       */
++#define MSDC_UHS1           (1 << 8)  /* uhs-1 mode support            */
++#define MSDC_DDR            (1 << 9)  /* ddr mode support              */
++#define MSDC_SPE            (1 << 10)  /* special support              */
++#define MSDC_INTERNAL_CLK   (1 << 11)  /* Force Internal clock */
++#define MSDC_TABDRV	(1 << 12)  /* TABLET */
++
++
++#define MSDC_SMPL_RISING    (0)
++#define MSDC_SMPL_FALLING   (1)
++
++#define MSDC_CMD_PIN        (0)
++#define MSDC_DAT_PIN        (1)
++#define MSDC_CD_PIN         (2)
++#define MSDC_WP_PIN         (3)
++#define MSDC_RST_PIN        (4)
++
++enum {
++    MSDC_CLKSRC_26MHZ = 0,
++    MSDC_CLKSRC_197MHZ = 1,
++    MSDC_CLKSRC_208MHZ = 2
++};
++
++struct msdc_hw {
++	unsigned char  clk_src;          /* host clock source */
++	unsigned char  cmd_edge;         /* command latch edge */
++	unsigned char  data_edge;        /* data latch edge */
++	unsigned char  clk_drv;          /* clock pad driving */
++	unsigned char  cmd_drv;          /* command pad driving */
++	unsigned char  dat_drv;          /* data pad driving */
++	unsigned long  flags;            /* hardware capability flags */
++	unsigned long  data_pins;        /* data pins */
++	unsigned long  data_offset;      /* data address offset */
++
++	/* config gpio pull mode */
++	void (*config_gpio_pin)(int type, int pull);
++
++	/* external power control for card */
++	void (*ext_power_on)(void);
++	void (*ext_power_off)(void);
++
++	/* external sdio irq operations */
++	void (*request_sdio_eirq)(sdio_irq_handler_t sdio_irq_handler, void *data);
++	void (*enable_sdio_eirq)(void);
++	void (*disable_sdio_eirq)(void);
++
++	/* external cd irq operations */
++	void (*request_cd_eirq)(sdio_irq_handler_t cd_irq_handler, void *data);
++	void (*enable_cd_eirq)(void);
++	void (*disable_cd_eirq)(void);
++	int  (*get_cd_status)(void);
++
++	/* power management callback for external module */
++	void (*register_pm)(pm_callback_t pm_cb, void *data);
++};
++
++extern struct msdc_hw msdc0_hw;
++extern struct msdc_hw msdc1_hw;
++extern struct msdc_hw msdc2_hw;
++extern struct msdc_hw msdc3_hw;
++
++    
++/*--------------------------------------------------------------------------*/
++/* Common Macro                                                             */
++/*--------------------------------------------------------------------------*/
++#define REG_ADDR(x)                 ((volatile u32*)(base + OFFSET_##x))
++
++/*--------------------------------------------------------------------------*/
++/* Common Definition                                                        */
++/*--------------------------------------------------------------------------*/
++#define MSDC_FIFO_SZ            (128)
++#define MSDC_FIFO_THD           (64)  // (128)
++#define MSDC_NUM                (4)
++
++#define MSDC_MS                 (0)
++#define MSDC_SDMMC              (1)
++
++#define MSDC_MODE_UNKNOWN       (0)
++#define MSDC_MODE_PIO           (1)
++#define MSDC_MODE_DMA_BASIC     (2)
++#define MSDC_MODE_DMA_DESC      (3)
++#define MSDC_MODE_DMA_ENHANCED  (4)
++#define MSDC_MODE_MMC_STREAM    (5)
++
++#define MSDC_BUS_1BITS          (0)
++#define MSDC_BUS_4BITS          (1)
++#define MSDC_BUS_8BITS          (2)
++
++#define MSDC_BRUST_8B           (3)
++#define MSDC_BRUST_16B          (4)
++#define MSDC_BRUST_32B          (5)
++#define MSDC_BRUST_64B          (6)
++
++#define MSDC_PIN_PULL_NONE      (0)
++#define MSDC_PIN_PULL_DOWN      (1)
++#define MSDC_PIN_PULL_UP        (2)
++#define MSDC_PIN_KEEP           (3)
++
++#define MSDC_MAX_SCLK           (48000000) /* +/- by chhung */
++#define MSDC_MIN_SCLK           (260000)
++
++#define MSDC_AUTOCMD12          (0x0001)
++#define MSDC_AUTOCMD23          (0x0002)
++#define MSDC_AUTOCMD19          (0x0003)
++
++#define MSDC_EMMC_BOOTMODE0     (0)     /* Pull low CMD mode */
++#define MSDC_EMMC_BOOTMODE1     (1)     /* Reset CMD mode */
++
++enum {
++    RESP_NONE = 0,
++    RESP_R1,
++    RESP_R2,
++    RESP_R3,
++    RESP_R4,
++    RESP_R5,
++    RESP_R6,
++    RESP_R7,
++    RESP_R1B
++};
++
++/*--------------------------------------------------------------------------*/
++/* Register Offset                                                          */
++/*--------------------------------------------------------------------------*/
++#define OFFSET_MSDC_CFG         (0x0)
++#define OFFSET_MSDC_IOCON       (0x04)
++#define OFFSET_MSDC_PS          (0x08)
++#define OFFSET_MSDC_INT         (0x0c)
++#define OFFSET_MSDC_INTEN       (0x10)
++#define OFFSET_MSDC_FIFOCS      (0x14)
++#define OFFSET_MSDC_TXDATA      (0x18)
++#define OFFSET_MSDC_RXDATA      (0x1c)
++#define OFFSET_SDC_CFG          (0x30)
++#define OFFSET_SDC_CMD          (0x34)
++#define OFFSET_SDC_ARG          (0x38)
++#define OFFSET_SDC_STS          (0x3c)
++#define OFFSET_SDC_RESP0        (0x40)
++#define OFFSET_SDC_RESP1        (0x44)
++#define OFFSET_SDC_RESP2        (0x48)
++#define OFFSET_SDC_RESP3        (0x4c)
++#define OFFSET_SDC_BLK_NUM      (0x50)
++#define OFFSET_SDC_CSTS         (0x58)
++#define OFFSET_SDC_CSTS_EN      (0x5c)
++#define OFFSET_SDC_DCRC_STS     (0x60)
++#define OFFSET_EMMC_CFG0        (0x70)
++#define OFFSET_EMMC_CFG1        (0x74)
++#define OFFSET_EMMC_STS         (0x78)
++#define OFFSET_EMMC_IOCON       (0x7c)
++#define OFFSET_SDC_ACMD_RESP    (0x80)
++#define OFFSET_SDC_ACMD19_TRG   (0x84)
++#define OFFSET_SDC_ACMD19_STS   (0x88)
++#define OFFSET_MSDC_DMA_SA      (0x90)
++#define OFFSET_MSDC_DMA_CA      (0x94)
++#define OFFSET_MSDC_DMA_CTRL    (0x98)
++#define OFFSET_MSDC_DMA_CFG     (0x9c)
++#define OFFSET_MSDC_DBG_SEL     (0xa0)
++#define OFFSET_MSDC_DBG_OUT     (0xa4)
++#define OFFSET_MSDC_PATCH_BIT   (0xb0)
++#define OFFSET_MSDC_PATCH_BIT1  (0xb4)
++#define OFFSET_MSDC_PAD_CTL0    (0xe0)
++#define OFFSET_MSDC_PAD_CTL1    (0xe4)
++#define OFFSET_MSDC_PAD_CTL2    (0xe8)
++#define OFFSET_MSDC_PAD_TUNE    (0xec)
++#define OFFSET_MSDC_DAT_RDDLY0  (0xf0)
++#define OFFSET_MSDC_DAT_RDDLY1  (0xf4)
++#define OFFSET_MSDC_HW_DBG      (0xf8)
++#define OFFSET_MSDC_VERSION     (0x100)
++#define OFFSET_MSDC_ECO_VER     (0x104)
++
++/*--------------------------------------------------------------------------*/
++/* Register Address                                                         */
++/*--------------------------------------------------------------------------*/
++
++/* common register */
++#define MSDC_CFG                REG_ADDR(MSDC_CFG)
++#define MSDC_IOCON              REG_ADDR(MSDC_IOCON)
++#define MSDC_PS                 REG_ADDR(MSDC_PS)
++#define MSDC_INT                REG_ADDR(MSDC_INT)
++#define MSDC_INTEN              REG_ADDR(MSDC_INTEN)
++#define MSDC_FIFOCS             REG_ADDR(MSDC_FIFOCS)
++#define MSDC_TXDATA             REG_ADDR(MSDC_TXDATA)
++#define MSDC_RXDATA             REG_ADDR(MSDC_RXDATA)
++#define MSDC_PATCH_BIT0         REG_ADDR(MSDC_PATCH_BIT)
++
++/* sdmmc register */
++#define SDC_CFG                 REG_ADDR(SDC_CFG)
++#define SDC_CMD                 REG_ADDR(SDC_CMD)
++#define SDC_ARG                 REG_ADDR(SDC_ARG)
++#define SDC_STS                 REG_ADDR(SDC_STS)
++#define SDC_RESP0               REG_ADDR(SDC_RESP0)
++#define SDC_RESP1               REG_ADDR(SDC_RESP1)
++#define SDC_RESP2               REG_ADDR(SDC_RESP2)
++#define SDC_RESP3               REG_ADDR(SDC_RESP3)
++#define SDC_BLK_NUM             REG_ADDR(SDC_BLK_NUM)
++#define SDC_CSTS                REG_ADDR(SDC_CSTS)
++#define SDC_CSTS_EN             REG_ADDR(SDC_CSTS_EN)
++#define SDC_DCRC_STS            REG_ADDR(SDC_DCRC_STS)
++
++/* emmc register*/
++#define EMMC_CFG0               REG_ADDR(EMMC_CFG0)
++#define EMMC_CFG1               REG_ADDR(EMMC_CFG1)
++#define EMMC_STS                REG_ADDR(EMMC_STS)
++#define EMMC_IOCON              REG_ADDR(EMMC_IOCON)
++
++/* auto command register */
++#define SDC_ACMD_RESP           REG_ADDR(SDC_ACMD_RESP)
++#define SDC_ACMD19_TRG          REG_ADDR(SDC_ACMD19_TRG)
++#define SDC_ACMD19_STS          REG_ADDR(SDC_ACMD19_STS)
++
++/* dma register */
++#define MSDC_DMA_SA             REG_ADDR(MSDC_DMA_SA)
++#define MSDC_DMA_CA             REG_ADDR(MSDC_DMA_CA)
++#define MSDC_DMA_CTRL           REG_ADDR(MSDC_DMA_CTRL)
++#define MSDC_DMA_CFG            REG_ADDR(MSDC_DMA_CFG)
++
++/* pad ctrl register */
++#define MSDC_PAD_CTL0           REG_ADDR(MSDC_PAD_CTL0)
++#define MSDC_PAD_CTL1           REG_ADDR(MSDC_PAD_CTL1)
++#define MSDC_PAD_CTL2           REG_ADDR(MSDC_PAD_CTL2)
++
++/* data read delay */
++#define MSDC_DAT_RDDLY0         REG_ADDR(MSDC_DAT_RDDLY0)
++#define MSDC_DAT_RDDLY1         REG_ADDR(MSDC_DAT_RDDLY1)
++
++/* debug register */
++#define MSDC_DBG_SEL            REG_ADDR(MSDC_DBG_SEL)
++#define MSDC_DBG_OUT            REG_ADDR(MSDC_DBG_OUT)
++
++/* misc register */
++#define MSDC_PATCH_BIT          REG_ADDR(MSDC_PATCH_BIT)
++#define MSDC_PATCH_BIT1         REG_ADDR(MSDC_PATCH_BIT1)
++#define MSDC_PAD_TUNE           REG_ADDR(MSDC_PAD_TUNE)
++#define MSDC_HW_DBG             REG_ADDR(MSDC_HW_DBG)
++#define MSDC_VERSION            REG_ADDR(MSDC_VERSION)
++#define MSDC_ECO_VER            REG_ADDR(MSDC_ECO_VER) /* ECO Version */
++
++/*--------------------------------------------------------------------------*/
++/* Register Mask                                                            */
++/*--------------------------------------------------------------------------*/
++
++/* MSDC_CFG mask */
++#define MSDC_CFG_MODE           (0x1  << 0)     /* RW */
++#define MSDC_CFG_CKPDN          (0x1  << 1)     /* RW */
++#define MSDC_CFG_RST            (0x1  << 2)     /* RW */
++#define MSDC_CFG_PIO            (0x1  << 3)     /* RW */
++#define MSDC_CFG_CKDRVEN        (0x1  << 4)     /* RW */
++#define MSDC_CFG_BV18SDT        (0x1  << 5)     /* RW */
++#define MSDC_CFG_BV18PSS        (0x1  << 6)     /* R  */
++#define MSDC_CFG_CKSTB          (0x1  << 7)     /* R  */
++#define MSDC_CFG_CKDIV          (0xff << 8)     /* RW */
++#define MSDC_CFG_CKMOD          (0x3  << 16)    /* RW */
++
++/* MSDC_IOCON mask */
++#define MSDC_IOCON_SDR104CKS    (0x1  << 0)     /* RW */
++#define MSDC_IOCON_RSPL         (0x1  << 1)     /* RW */
++#define MSDC_IOCON_DSPL         (0x1  << 2)     /* RW */
++#define MSDC_IOCON_DDLSEL       (0x1  << 3)     /* RW */
++#define MSDC_IOCON_DDR50CKD     (0x1  << 4)     /* RW */
++#define MSDC_IOCON_DSPLSEL      (0x1  << 5)     /* RW */
++#define MSDC_IOCON_D0SPL        (0x1  << 16)    /* RW */
++#define MSDC_IOCON_D1SPL        (0x1  << 17)    /* RW */
++#define MSDC_IOCON_D2SPL        (0x1  << 18)    /* RW */
++#define MSDC_IOCON_D3SPL        (0x1  << 19)    /* RW */
++#define MSDC_IOCON_D4SPL        (0x1  << 20)    /* RW */
++#define MSDC_IOCON_D5SPL        (0x1  << 21)    /* RW */
++#define MSDC_IOCON_D6SPL        (0x1  << 22)    /* RW */
++#define MSDC_IOCON_D7SPL        (0x1  << 23)    /* RW */
++#define MSDC_IOCON_RISCSZ       (0x3  << 24)    /* RW */
++
++/* MSDC_PS mask */
++#define MSDC_PS_CDEN            (0x1  << 0)     /* RW */
++#define MSDC_PS_CDSTS           (0x1  << 1)     /* R  */
++#define MSDC_PS_CDDEBOUNCE      (0xf  << 12)    /* RW */
++#define MSDC_PS_DAT             (0xff << 16)    /* R  */
++#define MSDC_PS_CMD             (0x1  << 24)    /* R  */
++#define MSDC_PS_WP              (0x1UL<< 31)    /* R  */
++
++/* MSDC_INT mask */
++#define MSDC_INT_MMCIRQ         (0x1  << 0)     /* W1C */
++#define MSDC_INT_CDSC           (0x1  << 1)     /* W1C */
++#define MSDC_INT_ACMDRDY        (0x1  << 3)     /* W1C */
++#define MSDC_INT_ACMDTMO        (0x1  << 4)     /* W1C */
++#define MSDC_INT_ACMDCRCERR     (0x1  << 5)     /* W1C */
++#define MSDC_INT_DMAQ_EMPTY     (0x1  << 6)     /* W1C */
++#define MSDC_INT_SDIOIRQ        (0x1  << 7)     /* W1C */
++#define MSDC_INT_CMDRDY         (0x1  << 8)     /* W1C */
++#define MSDC_INT_CMDTMO         (0x1  << 9)     /* W1C */
++#define MSDC_INT_RSPCRCERR      (0x1  << 10)    /* W1C */
++#define MSDC_INT_CSTA           (0x1  << 11)    /* R */
++#define MSDC_INT_XFER_COMPL     (0x1  << 12)    /* W1C */
++#define MSDC_INT_DXFER_DONE     (0x1  << 13)    /* W1C */
++#define MSDC_INT_DATTMO         (0x1  << 14)    /* W1C */
++#define MSDC_INT_DATCRCERR      (0x1  << 15)    /* W1C */
++#define MSDC_INT_ACMD19_DONE    (0x1  << 16)    /* W1C */
++
++/* MSDC_INTEN mask */
++#define MSDC_INTEN_MMCIRQ       (0x1  << 0)     /* RW */
++#define MSDC_INTEN_CDSC         (0x1  << 1)     /* RW */
++#define MSDC_INTEN_ACMDRDY      (0x1  << 3)     /* RW */
++#define MSDC_INTEN_ACMDTMO      (0x1  << 4)     /* RW */
++#define MSDC_INTEN_ACMDCRCERR   (0x1  << 5)     /* RW */
++#define MSDC_INTEN_DMAQ_EMPTY   (0x1  << 6)     /* RW */
++#define MSDC_INTEN_SDIOIRQ      (0x1  << 7)     /* RW */
++#define MSDC_INTEN_CMDRDY       (0x1  << 8)     /* RW */
++#define MSDC_INTEN_CMDTMO       (0x1  << 9)     /* RW */
++#define MSDC_INTEN_RSPCRCERR    (0x1  << 10)    /* RW */
++#define MSDC_INTEN_CSTA         (0x1  << 11)    /* RW */
++#define MSDC_INTEN_XFER_COMPL   (0x1  << 12)    /* RW */
++#define MSDC_INTEN_DXFER_DONE   (0x1  << 13)    /* RW */
++#define MSDC_INTEN_DATTMO       (0x1  << 14)    /* RW */
++#define MSDC_INTEN_DATCRCERR    (0x1  << 15)    /* RW */
++#define MSDC_INTEN_ACMD19_DONE  (0x1  << 16)    /* RW */
++
++/* MSDC_FIFOCS mask */
++#define MSDC_FIFOCS_RXCNT       (0xff << 0)     /* R */
++#define MSDC_FIFOCS_TXCNT       (0xff << 16)    /* R */
++#define MSDC_FIFOCS_CLR         (0x1UL<< 31)    /* RW */
++
++/* SDC_CFG mask */
++#define SDC_CFG_SDIOINTWKUP     (0x1  << 0)     /* RW */
++#define SDC_CFG_INSWKUP         (0x1  << 1)     /* RW */
++#define SDC_CFG_BUSWIDTH        (0x3  << 16)    /* RW */
++#define SDC_CFG_SDIO            (0x1  << 19)    /* RW */
++#define SDC_CFG_SDIOIDE         (0x1  << 20)    /* RW */      
++#define SDC_CFG_INTATGAP        (0x1  << 21)    /* RW */
++#define SDC_CFG_DTOC            (0xffUL << 24)  /* RW */
++
++/* SDC_CMD mask */
++#define SDC_CMD_OPC             (0x3f << 0)     /* RW */
++#define SDC_CMD_BRK             (0x1  << 6)     /* RW */
++#define SDC_CMD_RSPTYP          (0x7  << 7)     /* RW */
++#define SDC_CMD_DTYP            (0x3  << 11)    /* RW */
++#define SDC_CMD_DTYP            (0x3  << 11)    /* RW */
++#define SDC_CMD_RW              (0x1  << 13)    /* RW */
++#define SDC_CMD_STOP            (0x1  << 14)    /* RW */
++#define SDC_CMD_GOIRQ           (0x1  << 15)    /* RW */
++#define SDC_CMD_BLKLEN          (0xfff<< 16)    /* RW */
++#define SDC_CMD_AUTOCMD         (0x3  << 28)    /* RW */
++#define SDC_CMD_VOLSWTH         (0x1  << 30)    /* RW */
++
++/* SDC_STS mask */
++#define SDC_STS_SDCBUSY         (0x1  << 0)     /* RW */
++#define SDC_STS_CMDBUSY         (0x1  << 1)     /* RW */
++#define SDC_STS_SWR_COMPL       (0x1  << 31)    /* RW */
++
++/* SDC_DCRC_STS mask */
++#define SDC_DCRC_STS_NEG        (0xf  << 8)     /* RO */
++#define SDC_DCRC_STS_POS        (0xff << 0)     /* RO */
++
++/* EMMC_CFG0 mask */
++#define EMMC_CFG0_BOOTSTART     (0x1  << 0)     /* W */
++#define EMMC_CFG0_BOOTSTOP      (0x1  << 1)     /* W */
++#define EMMC_CFG0_BOOTMODE      (0x1  << 2)     /* RW */
++#define EMMC_CFG0_BOOTACKDIS    (0x1  << 3)     /* RW */
++#define EMMC_CFG0_BOOTWDLY      (0x7  << 12)    /* RW */
++#define EMMC_CFG0_BOOTSUPP      (0x1  << 15)    /* RW */
++
++/* EMMC_CFG1 mask */
++#define EMMC_CFG1_BOOTDATTMC    (0xfffff << 0)  /* RW */
++#define EMMC_CFG1_BOOTACKTMC    (0xfffUL << 20) /* RW */
++
++/* EMMC_STS mask */
++#define EMMC_STS_BOOTCRCERR     (0x1  << 0)     /* W1C */
++#define EMMC_STS_BOOTACKERR     (0x1  << 1)     /* W1C */
++#define EMMC_STS_BOOTDATTMO     (0x1  << 2)     /* W1C */
++#define EMMC_STS_BOOTACKTMO     (0x1  << 3)     /* W1C */
++#define EMMC_STS_BOOTUPSTATE    (0x1  << 4)     /* R */
++#define EMMC_STS_BOOTACKRCV     (0x1  << 5)     /* W1C */
++#define EMMC_STS_BOOTDATRCV     (0x1  << 6)     /* R */
++
++/* EMMC_IOCON mask */
++#define EMMC_IOCON_BOOTRST      (0x1  << 0)     /* RW */
++
++/* SDC_ACMD19_TRG mask */
++#define SDC_ACMD19_TRG_TUNESEL  (0xf  << 0)     /* RW */
++
++/* MSDC_DMA_CTRL mask */
++#define MSDC_DMA_CTRL_START     (0x1  << 0)     /* W */
++#define MSDC_DMA_CTRL_STOP      (0x1  << 1)     /* W */
++#define MSDC_DMA_CTRL_RESUME    (0x1  << 2)     /* W */
++#define MSDC_DMA_CTRL_MODE      (0x1  << 8)     /* RW */
++#define MSDC_DMA_CTRL_LASTBUF   (0x1  << 10)    /* RW */
++#define MSDC_DMA_CTRL_BRUSTSZ   (0x7  << 12)    /* RW */
++#define MSDC_DMA_CTRL_XFERSZ    (0xffffUL << 16)/* RW */
++
++/* MSDC_DMA_CFG mask */
++#define MSDC_DMA_CFG_STS        (0x1  << 0)     /* R */
++#define MSDC_DMA_CFG_DECSEN     (0x1  << 1)     /* RW */
++#define MSDC_DMA_CFG_BDCSERR    (0x1  << 4)     /* R */
++#define MSDC_DMA_CFG_GPDCSERR   (0x1  << 5)     /* R */
++
++/* MSDC_PATCH_BIT mask */
++#define MSDC_PATCH_BIT_WFLSMODE (0x1  << 0)     /* RW */
++#define MSDC_PATCH_BIT_ODDSUPP  (0x1  << 1)     /* RW */
++#define MSDC_PATCH_BIT_CKGEN_CK (0x1  << 6)     /* E2: Fixed to 1 */
++#define MSDC_PATCH_BIT_IODSSEL  (0x1  << 16)    /* RW */
++#define MSDC_PATCH_BIT_IOINTSEL (0x1  << 17)    /* RW */
++#define MSDC_PATCH_BIT_BUSYDLY  (0xf  << 18)    /* RW */
++#define MSDC_PATCH_BIT_WDOD     (0xf  << 22)    /* RW */
++#define MSDC_PATCH_BIT_IDRTSEL  (0x1  << 26)    /* RW */
++#define MSDC_PATCH_BIT_CMDFSEL  (0x1  << 27)    /* RW */
++#define MSDC_PATCH_BIT_INTDLSEL (0x1  << 28)    /* RW */
++#define MSDC_PATCH_BIT_SPCPUSH  (0x1  << 29)    /* RW */
++#define MSDC_PATCH_BIT_DECRCTMO (0x1  << 30)    /* RW */
++
++/* MSDC_PATCH_BIT1 mask */
++#define MSDC_PATCH_BIT1_WRDAT_CRCS  (0x7 << 3)
++#define MSDC_PATCH_BIT1_CMD_RSP     (0x7 << 0)
++
++/* MSDC_PAD_CTL0 mask */
++#define MSDC_PAD_CTL0_CLKDRVN   (0x7  << 0)     /* RW */
++#define MSDC_PAD_CTL0_CLKDRVP   (0x7  << 4)     /* RW */
++#define MSDC_PAD_CTL0_CLKSR     (0x1  << 8)     /* RW */
++#define MSDC_PAD_CTL0_CLKPD     (0x1  << 16)    /* RW */
++#define MSDC_PAD_CTL0_CLKPU     (0x1  << 17)    /* RW */
++#define MSDC_PAD_CTL0_CLKSMT    (0x1  << 18)    /* RW */
++#define MSDC_PAD_CTL0_CLKIES    (0x1  << 19)    /* RW */
++#define MSDC_PAD_CTL0_CLKTDSEL  (0xf  << 20)    /* RW */
++#define MSDC_PAD_CTL0_CLKRDSEL  (0xffUL<< 24)   /* RW */
++
++/* MSDC_PAD_CTL1 mask */
++#define MSDC_PAD_CTL1_CMDDRVN   (0x7  << 0)     /* RW */
++#define MSDC_PAD_CTL1_CMDDRVP   (0x7  << 4)     /* RW */
++#define MSDC_PAD_CTL1_CMDSR     (0x1  << 8)     /* RW */
++#define MSDC_PAD_CTL1_CMDPD     (0x1  << 16)    /* RW */
++#define MSDC_PAD_CTL1_CMDPU     (0x1  << 17)    /* RW */
++#define MSDC_PAD_CTL1_CMDSMT    (0x1  << 18)    /* RW */
++#define MSDC_PAD_CTL1_CMDIES    (0x1  << 19)    /* RW */
++#define MSDC_PAD_CTL1_CMDTDSEL  (0xf  << 20)    /* RW */
++#define MSDC_PAD_CTL1_CMDRDSEL  (0xffUL<< 24)   /* RW */
++
++/* MSDC_PAD_CTL2 mask */
++#define MSDC_PAD_CTL2_DATDRVN   (0x7  << 0)     /* RW */
++#define MSDC_PAD_CTL2_DATDRVP   (0x7  << 4)     /* RW */
++#define MSDC_PAD_CTL2_DATSR     (0x1  << 8)     /* RW */
++#define MSDC_PAD_CTL2_DATPD     (0x1  << 16)    /* RW */
++#define MSDC_PAD_CTL2_DATPU     (0x1  << 17)    /* RW */
++#define MSDC_PAD_CTL2_DATIES    (0x1  << 19)    /* RW */
++#define MSDC_PAD_CTL2_DATSMT    (0x1  << 18)    /* RW */
++#define MSDC_PAD_CTL2_DATTDSEL  (0xf  << 20)    /* RW */
++#define MSDC_PAD_CTL2_DATRDSEL  (0xffUL<< 24)   /* RW */
++
++/* MSDC_PAD_TUNE mask */
++#define MSDC_PAD_TUNE_DATWRDLY  (0x1F << 0)     /* RW */
++#define MSDC_PAD_TUNE_DATRRDLY  (0x1F << 8)     /* RW */
++#define MSDC_PAD_TUNE_CMDRDLY   (0x1F << 16)    /* RW */
++#define MSDC_PAD_TUNE_CMDRRDLY  (0x1FUL << 22)  /* RW */
++#define MSDC_PAD_TUNE_CLKTXDLY  (0x1FUL << 27)  /* RW */
++
++/* MSDC_DAT_RDDLY0/1 mask */
++#define MSDC_DAT_RDDLY0_D0      (0x1F << 0)     /* RW */
++#define MSDC_DAT_RDDLY0_D1      (0x1F << 8)     /* RW */
++#define MSDC_DAT_RDDLY0_D2      (0x1F << 16)    /* RW */
++#define MSDC_DAT_RDDLY0_D3      (0x1F << 24)    /* RW */
++
++#define MSDC_DAT_RDDLY1_D4      (0x1F << 0)     /* RW */
++#define MSDC_DAT_RDDLY1_D5      (0x1F << 8)     /* RW */
++#define MSDC_DAT_RDDLY1_D6      (0x1F << 16)    /* RW */
++#define MSDC_DAT_RDDLY1_D7      (0x1F << 24)    /* RW */
++
++#define MSDC_CKGEN_MSDC_DLY_SEL   (0x1F<<10)
++#define MSDC_INT_DAT_LATCH_CK_SEL  (0x7<<7)
++#define MSDC_CKGEN_MSDC_CK_SEL     (0x1<<6)
++#define CARD_READY_FOR_DATA             (1<<8)
++#define CARD_CURRENT_STATE(x)           ((x&0x00001E00)>>9)
++
++/*--------------------------------------------------------------------------*/
++/* Descriptor Structure                                                     */
++/*--------------------------------------------------------------------------*/
++typedef struct {
++    u32  hwo:1; /* could be changed by hw */
++    u32  bdp:1;
++    u32  rsv0:6;
++    u32  chksum:8;
++    u32  intr:1;
++    u32  rsv1:15;
++    void *next;
++    void *ptr;
++    u32  buflen:16;
++    u32  extlen:8;
++    u32  rsv2:8;
++    u32  arg;
++    u32  blknum;
++    u32  cmd;
++} gpd_t;
++
++typedef struct {
++    u32  eol:1;
++    u32  rsv0:7;
++    u32  chksum:8;
++    u32  rsv1:1;
++    u32  blkpad:1;
++    u32  dwpad:1;
++    u32  rsv2:13;
++    void *next;
++    void *ptr;
++    u32  buflen:16;
++    u32  rsv3:16;
++} bd_t;
++
++/*--------------------------------------------------------------------------*/
++/* Register Debugging Structure                                             */
++/*--------------------------------------------------------------------------*/
++
++typedef struct {
++    u32 msdc:1;
++    u32 ckpwn:1;
++    u32 rst:1;
++    u32 pio:1;
++    u32 ckdrven:1;
++    u32 start18v:1;
++    u32 pass18v:1;
++    u32 ckstb:1;
++    u32 ckdiv:8;
++    u32 ckmod:2;
++    u32 pad:14;		
++} msdc_cfg_reg;
++typedef struct {
++    u32 sdr104cksel:1;
++    u32 rsmpl:1;
++    u32 dsmpl:1;
++    u32 ddlysel:1;
++    u32 ddr50ckd:1;
++    u32 dsplsel:1;
++    u32 pad1:10;
++    u32 d0spl:1;
++    u32 d1spl:1;
++    u32 d2spl:1;
++    u32 d3spl:1;
++    u32 d4spl:1;
++    u32 d5spl:1;
++    u32 d6spl:1;
++    u32 d7spl:1;
++    u32 riscsz:1;
++    u32 pad2:7;
++} msdc_iocon_reg;
++typedef struct {
++    u32 cden:1;
++    u32 cdsts:1;
++    u32 pad1:10;
++    u32 cddebounce:4;
++    u32 dat:8;
++    u32 cmd:1;
++    u32 pad2:6;
++    u32 wp:1;
++} msdc_ps_reg;
++typedef struct {
++    u32 mmcirq:1;
++    u32 cdsc:1;
++    u32 pad1:1;
++    u32 atocmdrdy:1;
++    u32 atocmdtmo:1;
++    u32 atocmdcrc:1;
++    u32 dmaqempty:1;
++    u32 sdioirq:1;
++    u32 cmdrdy:1;
++    u32 cmdtmo:1;
++    u32 rspcrc:1;
++    u32 csta:1;
++    u32 xfercomp:1;
++    u32 dxferdone:1;
++    u32 dattmo:1;
++    u32 datcrc:1;
++    u32 atocmd19done:1;
++    u32 pad2:15;
++} msdc_int_reg;
++typedef struct {
++    u32 mmcirq:1;
++    u32 cdsc:1;
++    u32 pad1:1;
++    u32 atocmdrdy:1;
++    u32 atocmdtmo:1;
++    u32 atocmdcrc:1;
++    u32 dmaqempty:1;
++    u32 sdioirq:1;
++    u32 cmdrdy:1;
++    u32 cmdtmo:1;
++    u32 rspcrc:1;
++    u32 csta:1;
++    u32 xfercomp:1;
++    u32 dxferdone:1;
++    u32 dattmo:1;
++    u32 datcrc:1;
++    u32 atocmd19done:1;
++    u32 pad2:15;
++} msdc_inten_reg;
++typedef struct {
++    u32 rxcnt:8;
++    u32 pad1:8;
++    u32 txcnt:8;
++    u32 pad2:7;
++    u32 clr:1;
++} msdc_fifocs_reg;
++typedef struct {
++    u32 val;
++} msdc_txdat_reg;
++typedef struct {
++    u32 val;
++} msdc_rxdat_reg;
++typedef struct {
++    u32 sdiowkup:1;
++    u32 inswkup:1;
++    u32 pad1:14;
++    u32 buswidth:2;
++    u32 pad2:1;
++    u32 sdio:1;
++    u32 sdioide:1;
++    u32 intblkgap:1;
++    u32 pad4:2;
++    u32 dtoc:8;
++} sdc_cfg_reg;
++typedef struct {
++    u32 cmd:6;
++    u32 brk:1;
++    u32 rsptyp:3;
++    u32 pad1:1;
++    u32 dtype:2;
++    u32 rw:1;
++    u32 stop:1;
++    u32 goirq:1;    
++    u32 blklen:12;
++    u32 atocmd:2;
++    u32 volswth:1;
++    u32 pad2:1;
++} sdc_cmd_reg;
++typedef struct {
++    u32 arg;
++} sdc_arg_reg;
++typedef struct {
++    u32 sdcbusy:1;
++    u32 cmdbusy:1;
++    u32 pad:29;
++    u32 swrcmpl:1;
++} sdc_sts_reg;
++typedef struct {
++    u32 val;
++} sdc_resp0_reg;
++typedef struct {
++    u32 val;	
++} sdc_resp1_reg;
++typedef struct {
++    u32 val;	
++} sdc_resp2_reg;
++typedef struct {
++    u32 val;	
++} sdc_resp3_reg;
++typedef struct {
++    u32 num;	
++} sdc_blknum_reg;
++typedef struct {
++    u32 sts;
++} sdc_csts_reg;
++typedef struct {
++    u32 sts;
++} sdc_cstsen_reg;
++typedef struct {
++    u32 datcrcsts:8;
++    u32 ddrcrcsts:4;
++    u32 pad:20;
++} sdc_datcrcsts_reg;
++typedef struct {
++    u32 bootstart:1;
++    u32 bootstop:1;
++    u32 bootmode:1;
++    u32 pad1:9;
++    u32 bootwaidly:3;
++    u32 bootsupp:1;
++    u32 pad2:16;
++} emmc_cfg0_reg;
++typedef struct {
++    u32 bootcrctmc:16;
++    u32 pad:4;
++    u32 bootacktmc:12;
++} emmc_cfg1_reg;
++typedef struct {
++    u32 bootcrcerr:1;
++    u32 bootackerr:1;
++    u32 bootdattmo:1;
++    u32 bootacktmo:1;
++    u32 bootupstate:1;
++    u32 bootackrcv:1;
++    u32 bootdatrcv:1;
++    u32 pad:25;
++} emmc_sts_reg;
++typedef struct {
++    u32 bootrst:1;
++    u32 pad:31;
++} emmc_iocon_reg;
++typedef struct {
++    u32 val;
++} msdc_acmd_resp_reg;
++typedef struct {
++    u32 tunesel:4;
++    u32 pad:28;
++} msdc_acmd19_trg_reg;
++typedef struct {
++    u32 val;
++} msdc_acmd19_sts_reg;
++typedef struct {
++    u32 addr;
++} msdc_dma_sa_reg;
++typedef struct {
++    u32 addr;
++} msdc_dma_ca_reg;
++typedef struct {
++    u32 start:1;
++    u32 stop:1;
++    u32 resume:1;
++    u32 pad1:5;
++    u32 mode:1;
++    u32 pad2:1;
++    u32 lastbuf:1;
++    u32 pad3:1;
++    u32 brustsz:3;
++    u32 pad4:1;
++    u32 xfersz:16;
++} msdc_dma_ctrl_reg;
++typedef struct {
++    u32 status:1;
++    u32 decsen:1;
++    u32 pad1:2;
++    u32 bdcsen:1;
++    u32 gpdcsen:1;
++    u32 pad2:26;
++} msdc_dma_cfg_reg;
++typedef struct {
++    u32 sel:16;
++    u32 pad2:16;
++} msdc_dbg_sel_reg;
++typedef struct {
++    u32 val;
++} msdc_dbg_out_reg;
++typedef struct {
++    u32 clkdrvn:3;
++    u32 rsv0:1;
++    u32 clkdrvp:3;
++    u32 rsv1:1;
++    u32 clksr:1;
++    u32 rsv2:7;
++    u32 clkpd:1;    
++    u32 clkpu:1;
++    u32 clksmt:1;
++    u32 clkies:1;
++    u32 clktdsel:4;
++    u32 clkrdsel:8;
++} msdc_pad_ctl0_reg;
++typedef struct {
++    u32 cmddrvn:3;
++    u32 rsv0:1;    
++    u32 cmddrvp:3;
++    u32 rsv1:1;
++    u32 cmdsr:1;
++    u32 rsv2:7;
++    u32 cmdpd:1;    
++    u32 cmdpu:1;
++    u32 cmdsmt:1;
++    u32 cmdies:1;
++    u32 cmdtdsel:4;
++    u32 cmdrdsel:8;
++} msdc_pad_ctl1_reg;
++typedef struct {
++    u32 datdrvn:3;
++    u32 rsv0:1;
++    u32 datdrvp:3;
++    u32 rsv1:1;
++    u32 datsr:1;
++    u32 rsv2:7;
++    u32 datpd:1;    
++    u32 datpu:1;
++    u32 datsmt:1;
++    u32 daties:1;
++    u32 dattdsel:4;
++    u32 datrdsel:8;
++} msdc_pad_ctl2_reg;
++typedef struct {
++    u32 wrrxdly:3;
++    u32 pad1:5;
++    u32 rdrxdly:8;
++    u32 pad2:16;
++} msdc_pad_tune_reg;
++typedef struct {
++    u32 dat0:5;
++    u32 rsv0:3;
++    u32 dat1:5;
++    u32 rsv1:3;
++    u32 dat2:5;
++    u32 rsv2:3;
++    u32 dat3:5;
++    u32 rsv3:3;    
++} msdc_dat_rddly0;
++typedef struct {
++    u32 dat4:5;
++    u32 rsv4:3;
++    u32 dat5:5;
++    u32 rsv5:3;
++    u32 dat6:5;
++    u32 rsv6:3;
++    u32 dat7:5;
++    u32 rsv7:3;
++} msdc_dat_rddly1;
++typedef struct {
++    u32 dbg0sel:8;
++    u32 dbg1sel:6;
++    u32 pad1:2;
++    u32 dbg2sel:6;
++    u32 pad2:2;
++    u32 dbg3sel:6;
++    u32 pad3:2;
++} msdc_hw_dbg_reg;
++typedef struct {
++    u32 val;
++} msdc_version_reg;
++typedef struct {
++    u32 val;
++} msdc_eco_ver_reg;
++
++struct msdc_regs {
++    msdc_cfg_reg        msdc_cfg;      /* base+0x00h */
++    msdc_iocon_reg      msdc_iocon;    /* base+0x04h */
++    msdc_ps_reg         msdc_ps;       /* base+0x08h */
++    msdc_int_reg        msdc_int;      /* base+0x0ch */
++    msdc_inten_reg      msdc_inten;    /* base+0x10h */
++    msdc_fifocs_reg     msdc_fifocs;   /* base+0x14h */
++    msdc_txdat_reg      msdc_txdat;    /* base+0x18h */
++    msdc_rxdat_reg      msdc_rxdat;    /* base+0x1ch */
++    u32                 rsv1[4];
++    sdc_cfg_reg         sdc_cfg;       /* base+0x30h */
++    sdc_cmd_reg         sdc_cmd;       /* base+0x34h */
++    sdc_arg_reg         sdc_arg;       /* base+0x38h */
++    sdc_sts_reg         sdc_sts;       /* base+0x3ch */
++    sdc_resp0_reg       sdc_resp0;     /* base+0x40h */
++    sdc_resp1_reg       sdc_resp1;     /* base+0x44h */
++    sdc_resp2_reg       sdc_resp2;     /* base+0x48h */
++    sdc_resp3_reg       sdc_resp3;     /* base+0x4ch */
++    sdc_blknum_reg      sdc_blknum;    /* base+0x50h */
++    u32                 rsv2[1];
++    sdc_csts_reg        sdc_csts;      /* base+0x58h */
++    sdc_cstsen_reg      sdc_cstsen;    /* base+0x5ch */
++    sdc_datcrcsts_reg   sdc_dcrcsta;   /* base+0x60h */
++    u32                 rsv3[3];
++    emmc_cfg0_reg       emmc_cfg0;     /* base+0x70h */
++    emmc_cfg1_reg       emmc_cfg1;     /* base+0x74h */
++    emmc_sts_reg        emmc_sts;      /* base+0x78h */
++    emmc_iocon_reg      emmc_iocon;    /* base+0x7ch */
++    msdc_acmd_resp_reg  acmd_resp;     /* base+0x80h */
++    msdc_acmd19_trg_reg acmd19_trg;    /* base+0x84h */
++    msdc_acmd19_sts_reg acmd19_sts;    /* base+0x88h */
++    u32                 rsv4[1];
++    msdc_dma_sa_reg     dma_sa;        /* base+0x90h */
++    msdc_dma_ca_reg     dma_ca;        /* base+0x94h */
++    msdc_dma_ctrl_reg   dma_ctrl;      /* base+0x98h */
++    msdc_dma_cfg_reg    dma_cfg;       /* base+0x9ch */
++    msdc_dbg_sel_reg    dbg_sel;       /* base+0xa0h */
++    msdc_dbg_out_reg    dbg_out;       /* base+0xa4h */
++    u32                 rsv5[2];
++    u32                 patch0;        /* base+0xb0h */
++    u32                 patch1;        /* base+0xb4h */
++    u32                 rsv6[10];
++    msdc_pad_ctl0_reg   pad_ctl0;      /* base+0xe0h */
++    msdc_pad_ctl1_reg   pad_ctl1;      /* base+0xe4h */
++    msdc_pad_ctl2_reg   pad_ctl2;      /* base+0xe8h */
++    msdc_pad_tune_reg   pad_tune;      /* base+0xech */
++    msdc_dat_rddly0     dat_rddly0;    /* base+0xf0h */
++    msdc_dat_rddly1     dat_rddly1;    /* base+0xf4h */
++    msdc_hw_dbg_reg     hw_dbg;        /* base+0xf8h */
++    u32                 rsv7[1];       
++    msdc_version_reg    version;       /* base+0x100h */
++    msdc_eco_ver_reg    eco_ver;       /* base+0x104h */
++};
++
++struct scatterlist_ex {
++    u32 cmd;
++    u32 arg;
++    u32 sglen;
++    struct scatterlist *sg;
++};
++
++#define DMA_FLAG_NONE       (0x00000000)
++#define DMA_FLAG_EN_CHKSUM  (0x00000001)
++#define DMA_FLAG_PAD_BLOCK  (0x00000002)
++#define DMA_FLAG_PAD_DWORD  (0x00000004)
++
++struct msdc_dma {
++    u32 flags;                   /* flags */
++    u32 xfersz;                  /* xfer size in bytes */
++    u32 sglen;                   /* size of scatter list */
++    u32 blklen;                  /* block size */
++    struct scatterlist *sg;      /* I/O scatter list */
++    struct scatterlist_ex *esg;  /* extended I/O scatter list */
++    u8  mode;                    /* dma mode        */
++    u8  burstsz;                 /* burst size      */
++    u8  intr;                    /* dma done interrupt */
++    u8  padding;                 /* padding */
++    u32 cmd;                     /* enhanced mode command */
++    u32 arg;                     /* enhanced mode arg */
++    u32 rsp;                     /* enhanced mode command response */
++    u32 autorsp;                 /* auto command response */
++
++    gpd_t *gpd;                  /* pointer to gpd array */
++    bd_t  *bd;                   /* pointer to bd array */
++    dma_addr_t gpd_addr;         /* the physical address of gpd array */
++    dma_addr_t bd_addr;          /* the physical address of bd array */
++    u32 used_gpd;                /* the number of used gpd elements */
++    u32 used_bd;                 /* the number of used bd elements */
++};
++
++struct msdc_host
++{
++    struct msdc_hw              *hw;
++
++    struct mmc_host             *mmc;           /* mmc structure */
++    struct mmc_command          *cmd;
++    struct mmc_data             *data;
++    struct mmc_request          *mrq; 
++    int                         cmd_rsp;
++    int                         cmd_rsp_done;
++    int                         cmd_r1b_done;
++
++    int                         error; 
++    spinlock_t                  lock;           /* mutex */
++    struct semaphore            sem; 
++
++    u32                         blksz;          /* host block size */
++    u32                         base;           /* host base address */    
++    int                         id;             /* host id */
++    int                         pwr_ref;        /* core power reference count */
++
++    u32                         xfer_size;      /* total transferred size */
++
++    struct msdc_dma             dma;            /* dma channel */
++    u32                         dma_addr;       /* dma transfer address */
++    u32                         dma_left_size;  /* dma transfer left size */
++    u32                         dma_xfer_size;  /* dma transfer size in bytes */
++    int                         dma_xfer;       /* dma transfer mode */
++
++    u32                         timeout_ns;     /* data timeout ns */
++    u32                         timeout_clks;   /* data timeout clks */
++
++    atomic_t                    abort;          /* abort transfer */
++
++    int                         irq;            /* host interrupt */
++
++    struct tasklet_struct       card_tasklet;
++
++    struct completion           cmd_done;
++    struct completion           xfer_done;
++    struct pm_message           pm_state;
++
++    u32                         mclk;           /* mmc subsystem clock */
++    u32                         hclk;           /* host clock speed */		
++    u32                         sclk;           /* SD/MS clock speed */
++    u8                          core_clkon;     /* Host core clock on ? */
++    u8                          card_clkon;     /* Card clock on ? */
++    u8                          core_power;     /* core power */    
++    u8                          power_mode;     /* host power mode */
++    u8                          card_inserted;  /* card inserted ? */
++    u8                          suspend;        /* host suspended ? */    
++    u8                          reserved;
++    u8                          app_cmd;        /* for app command */     
++    u32                         app_cmd_arg;    
++    u64                         starttime;
++};
++
++static inline unsigned int uffs(unsigned int x)
++{
++    unsigned int r = 1;
++
++    if (!x)
++        return 0;
++    if (!(x & 0xffff)) {
++        x >>= 16;
++        r += 16;
++    }
++    if (!(x & 0xff)) {
++        x >>= 8;
++        r += 8;
++    }
++    if (!(x & 0xf)) {
++        x >>= 4;
++        r += 4;
++    }
++    if (!(x & 3)) {
++        x >>= 2;
++        r += 2;
++    }
++    if (!(x & 1)) {
++        x >>= 1;
++        r += 1;
++    }
++    return r;
++}
++#define sdr_read8(reg)           __raw_readb(reg)
++#define sdr_read16(reg)          __raw_readw(reg)
++#define sdr_read32(reg)          __raw_readl(reg)
++#define sdr_write8(reg,val)      __raw_writeb(val,reg)
++#define sdr_write16(reg,val)     __raw_writew(val,reg)
++#define sdr_write32(reg,val)     __raw_writel(val,reg)
++
++#define sdr_set_bits(reg,bs)     ((*(volatile u32*)(reg)) |= (u32)(bs))
++#define sdr_clr_bits(reg,bs)     ((*(volatile u32*)(reg)) &= ~((u32)(bs)))
++
++#define sdr_set_field(reg,field,val) \
++    do {	\
++        volatile unsigned int tv = sdr_read32(reg);	\
++        tv &= ~(field); \
++        tv |= ((val) << (uffs((unsigned int)field) - 1)); \
++        sdr_write32(reg,tv); \
++    } while(0)
++#define sdr_get_field(reg,field,val) \
++    do {	\
++        volatile unsigned int tv = sdr_read32(reg);	\
++        val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
++    } while(0)
++
++#endif
++
+diff --git a/drivers/mmc/host/sdhci-mt7620.c b/drivers/mmc/host/sdhci-mt7620.c
+new file mode 100644
+index 0000000..a3cb5e4
+--- /dev/null
++++ b/drivers/mmc/host/sdhci-mt7620.c
+@@ -0,0 +1,2314 @@
++/* Copyright Statement:
++ *
++ * This software/firmware and related documentation ("MediaTek Software") are
++ * protected under relevant copyright laws. The information contained herein
++ * is confidential and proprietary to MediaTek Inc. and/or its licensors.
++ * Without the prior written permission of MediaTek inc. and/or its licensors,
++ * any reproduction, modification, use or disclosure of MediaTek Software,
++ * and information contained herein, in whole or in part, shall be strictly prohibited.
++ *
++ * MediaTek Inc. (C) 2010. All rights reserved.
++ *
++ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
++ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
++ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER ON
++ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
++ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
++ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
++ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
++ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES TO LOOK ONLY TO SUCH
++ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. RECEIVER EXPRESSLY ACKNOWLEDGES
++ * THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES
++ * CONTAINED IN MEDIATEK SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK
++ * SOFTWARE RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
++ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND
++ * CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
++ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
++ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY RECEIVER TO
++ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
++ *
++ * The following software/firmware and/or related documentation ("MediaTek Software")
++ * have been modified by MediaTek Inc. All revisions are subject to any receiver's
++ * applicable license agreements with MediaTek Inc.
++ */
++
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/init.h>
++#include <linux/spinlock.h>
++#include <linux/timer.h>
++#include <linux/ioport.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/of_platform.h>
++#include <linux/interrupt.h>
++#include <linux/delay.h>
++#include <linux/blkdev.h>
++#include <linux/slab.h>
++#include <linux/mmc/host.h>
++#include <linux/mmc/card.h>
++#include <linux/mmc/core.h>
++#include <linux/mmc/mmc.h>
++#include <linux/mmc/sd.h>
++#include <linux/mmc/sdio.h>
++#include <linux/dma-mapping.h>
++
++#include <linux/types.h>
++#include <linux/kernel.h>
++#include <linux/version.h>
++#include <linux/pm.h>
++
++#define MSDC_SMPL_FALLING   (1)
++#define MSDC_CD_PIN_EN      (1 << 0)  /* card detection pin is wired   */
++#define MSDC_WP_PIN_EN      (1 << 1)  /* write protection pin is wired */
++#define MSDC_REMOVABLE      (1 << 5)  /* removable slot                */
++#define MSDC_SYS_SUSPEND    (1 << 6)  /* suspended by system           */
++#define MSDC_HIGHSPEED      (1 << 7)
++
++#define IRQ_SDC 22
++
++#include <asm/dma.h>
++
++#include "mt6575_sd.h"
++
++#define DRV_NAME            "mtk-sd"
++
++#define HOST_MAX_NUM        (1) /* +/- by chhung */
++
++#define HOST_MAX_MCLK       (48000000) /* +/- by chhung */
++#define HOST_MIN_MCLK       (260000)
++
++#define HOST_MAX_BLKSZ      (2048)
++
++#define MSDC_OCR_AVAIL      (MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33)
++
++#define GPIO_PULL_DOWN      (0)
++#define GPIO_PULL_UP        (1)
++
++#define DEFAULT_DEBOUNCE    (8)       /* 8 cycles */
++#define DEFAULT_DTOC        (40)      /* data timeout counter. 65536x40 sclk. */
++
++#define CMD_TIMEOUT         (HZ/10)     /* 100ms */
++#define DAT_TIMEOUT         (HZ/2 * 5)  /* 500ms x5 */
++
++#define MAX_DMA_CNT         (64 * 1024 - 512)   /* a single transaction for WIFI may be 50K*/
++
++#define MAX_GPD_NUM         (1 + 1)  /* one null gpd */
++#define MAX_BD_NUM          (1024)
++#define MAX_BD_PER_GPD      (MAX_BD_NUM)
++
++#define MAX_HW_SGMTS        (MAX_BD_NUM)
++#define MAX_PHY_SGMTS       (MAX_BD_NUM)
++#define MAX_SGMT_SZ         (MAX_DMA_CNT)
++#define MAX_REQ_SZ          (MAX_SGMT_SZ * 8)  
++
++#ifdef MT6575_SD_DEBUG
++static struct msdc_regs *msdc_reg[HOST_MAX_NUM];
++#endif 
++
++//=================================
++#define PERI_MSDC0_PDN      (15)
++//#define PERI_MSDC1_PDN    (16)
++//#define PERI_MSDC2_PDN    (17)
++//#define PERI_MSDC3_PDN    (18)
++
++struct msdc_host *msdc_6575_host[] = {NULL,NULL,NULL,NULL};
++
++struct msdc_hw msdc0_hw = {
++	.clk_src        = 0,
++	.cmd_edge       = MSDC_SMPL_FALLING,
++	.data_edge      = MSDC_SMPL_FALLING,
++	.clk_drv        = 4,
++	.cmd_drv        = 4,
++	.dat_drv        = 4,
++	.data_pins      = 4,
++	.data_offset    = 0,
++	.flags          = MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED,
++};
++
++static struct resource mtk_sd_resources[] = {
++	[0] = {
++		.start  = 0xb0130000,
++		.end    = 0xb0133fff,
++		.flags  = IORESOURCE_MEM,
++	},
++	[1] = {
++		.start  = IRQ_SDC,	/*FIXME*/
++		.end    = IRQ_SDC,	/*FIXME*/
++		.flags  = IORESOURCE_IRQ,
++	},
++};
++
++static struct platform_device mtk_sd_device = {
++	.name           = "mtk-sd",
++	.id             = 0,
++	.num_resources  = ARRAY_SIZE(mtk_sd_resources),
++	.resource       = mtk_sd_resources,
++};
++/* end of +++ */
++
++static int msdc_rsp[] = {
++    0,  /* RESP_NONE */
++    1,  /* RESP_R1 */
++    2,  /* RESP_R2 */
++    3,  /* RESP_R3 */
++    4,  /* RESP_R4 */
++    1,  /* RESP_R5 */
++    1,  /* RESP_R6 */
++    1,  /* RESP_R7 */
++    7,  /* RESP_R1b */
++};
++
++/* For Inhanced DMA */
++#define msdc_init_gpd_ex(gpd,extlen,cmd,arg,blknum) \
++    do { \
++        ((gpd_t*)gpd)->extlen = extlen; \
++        ((gpd_t*)gpd)->cmd    = cmd; \
++        ((gpd_t*)gpd)->arg    = arg; \
++        ((gpd_t*)gpd)->blknum = blknum; \
++    }while(0)
++    
++#define msdc_init_bd(bd, blkpad, dwpad, dptr, dlen) \
++    do { \
++        BUG_ON(dlen > 0xFFFFUL); \
++        ((bd_t*)bd)->blkpad = blkpad; \
++        ((bd_t*)bd)->dwpad  = dwpad; \
++        ((bd_t*)bd)->ptr    = (void*)dptr; \
++        ((bd_t*)bd)->buflen = dlen; \
++    }while(0)
++
++#define msdc_txfifocnt()   ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16)
++#define msdc_rxfifocnt()   ((sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) >> 0)
++#define msdc_fifo_write32(v)   sdr_write32(MSDC_TXDATA, (v))
++#define msdc_fifo_write8(v)    sdr_write8(MSDC_TXDATA, (v))
++#define msdc_fifo_read32()   sdr_read32(MSDC_RXDATA)
++#define msdc_fifo_read8()    sdr_read8(MSDC_RXDATA)	
++
++
++#define msdc_dma_on()        sdr_clr_bits(MSDC_CFG, MSDC_CFG_PIO)
++#define msdc_dma_off()       sdr_set_bits(MSDC_CFG, MSDC_CFG_PIO)
++
++#define msdc_retry(expr,retry,cnt) \
++    do { \
++        int backup = cnt; \
++        while (retry) { \
++            if (!(expr)) break; \
++            if (cnt-- == 0) { \
++                retry--; mdelay(1); cnt = backup; \
++            } \
++        } \
++        WARN_ON(retry == 0); \
++    } while(0)
++
++#if 0 /* +/- chhung */
++#define msdc_reset() \
++    do { \
++        int retry = 3, cnt = 1000; \
++        sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
++        dsb(); \
++        msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
++    } while(0)
++#else
++#define msdc_reset() \
++    do { \
++        int retry = 3, cnt = 1000; \
++        sdr_set_bits(MSDC_CFG, MSDC_CFG_RST); \
++        msdc_retry(sdr_read32(MSDC_CFG) & MSDC_CFG_RST, retry, cnt); \
++    } while(0)
++#endif /* end of +/- */
++
++#define msdc_clr_int() \
++    do { \
++        volatile u32 val = sdr_read32(MSDC_INT); \
++        sdr_write32(MSDC_INT, val); \
++    } while(0)
++
++#define msdc_clr_fifo() \
++    do { \
++        int retry = 3, cnt = 1000; \
++        sdr_set_bits(MSDC_FIFOCS, MSDC_FIFOCS_CLR); \
++        msdc_retry(sdr_read32(MSDC_FIFOCS) & MSDC_FIFOCS_CLR, retry, cnt); \
++    } while(0)
++
++#define msdc_irq_save(val) \
++    do { \
++        val = sdr_read32(MSDC_INTEN); \
++        sdr_clr_bits(MSDC_INTEN, val); \
++    } while(0)
++	
++#define msdc_irq_restore(val) \
++    do { \
++        sdr_set_bits(MSDC_INTEN, val); \
++    } while(0)
++
++/* clock source for host: global */
++static u32 hclks[] = {48000000}; /* +/- by chhung */
++
++//============================================
++// the power for msdc host controller: global
++//    always keep the VMC on. 
++//============================================
++#define msdc_vcore_on(host) \
++    do { \
++        printk("[+]VMC ref. count<%d>\n", ++host->pwr_ref); \
++        (void)hwPowerOn(MT65XX_POWER_LDO_VMC, VOL_3300, "SD"); \
++    } while (0)
++#define msdc_vcore_off(host) \
++    do { \
++        printk("[-]VMC ref. count<%d>\n", --host->pwr_ref); \
++        (void)hwPowerDown(MT65XX_POWER_LDO_VMC, "SD"); \
++    } while (0)
++
++//====================================
++// the vdd output for card: global 
++//   always keep the VMCH on. 
++//==================================== 
++#define msdc_vdd_on(host) \
++    do { \
++        (void)hwPowerOn(MT65XX_POWER_LDO_VMCH, VOL_3300, "SD"); \
++    } while (0)   
++#define msdc_vdd_off(host) \
++    do { \
++        (void)hwPowerDown(MT65XX_POWER_LDO_VMCH, "SD"); \
++    } while (0)      
++
++#define sdc_is_busy()          (sdr_read32(SDC_STS) & SDC_STS_SDCBUSY)
++#define sdc_is_cmd_busy()      (sdr_read32(SDC_STS) & SDC_STS_CMDBUSY)
++
++#define sdc_send_cmd(cmd,arg) \
++    do { \
++        sdr_write32(SDC_ARG, (arg)); \
++        sdr_write32(SDC_CMD, (cmd)); \
++    } while(0)
++
++// can modify to read h/w register.
++//#define is_card_present(h)   ((sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1);
++#define is_card_present(h)     (((struct msdc_host*)(h))->card_inserted)
++
++/* +++ chhung */
++#ifndef __ASSEMBLY__
++#define PHYSADDR(a)             (((unsigned long)(a)) & 0x1fffffff)
++#else
++#define PHYSADDR(a)             ((a) & 0x1fffffff)
++#endif
++/* end of +++ */
++static unsigned int msdc_do_command(struct msdc_host   *host, 
++                                      struct mmc_command *cmd,
++                                      int                 tune,
++                                      unsigned long       timeout);  
++                                     
++static int msdc_tune_cmdrsp(struct msdc_host*host,struct mmc_command *cmd);
++
++#ifdef MT6575_SD_DEBUG
++static void msdc_dump_card_status(struct msdc_host *host, u32 status)
++{
++    static char *state[] = {
++        "Idle",			/* 0 */
++        "Ready",		/* 1 */
++        "Ident",		/* 2 */
++        "Stby",			/* 3 */
++        "Tran",			/* 4 */
++        "Data",			/* 5 */
++        "Rcv",			/* 6 */
++        "Prg",			/* 7 */
++        "Dis",			/* 8 */
++        "Reserved",		/* 9 */
++        "Reserved",		/* 10 */
++        "Reserved",		/* 11 */
++        "Reserved",		/* 12 */
++        "Reserved",		/* 13 */
++        "Reserved",		/* 14 */
++        "I/O mode",		/* 15 */
++    };
++    if (status & R1_OUT_OF_RANGE)
++        printk("[CARD_STATUS] Out of Range\n");
++    if (status & R1_ADDRESS_ERROR)
++        printk("[CARD_STATUS] Address Error\n");
++    if (status & R1_BLOCK_LEN_ERROR)
++        printk("[CARD_STATUS] Block Len Error\n");
++    if (status & R1_ERASE_SEQ_ERROR)
++        printk("[CARD_STATUS] Erase Seq Error\n");
++    if (status & R1_ERASE_PARAM)
++        printk("[CARD_STATUS] Erase Param\n");
++    if (status & R1_WP_VIOLATION)
++        printk("[CARD_STATUS] WP Violation\n");
++    if (status & R1_CARD_IS_LOCKED)
++        printk("[CARD_STATUS] Card is Locked\n");
++    if (status & R1_LOCK_UNLOCK_FAILED)
++        printk("[CARD_STATUS] Lock/Unlock Failed\n");
++    if (status & R1_COM_CRC_ERROR)
++        printk("[CARD_STATUS] Command CRC Error\n");
++    if (status & R1_ILLEGAL_COMMAND)
++        printk("[CARD_STATUS] Illegal Command\n");
++    if (status & R1_CARD_ECC_FAILED)
++        printk("[CARD_STATUS] Card ECC Failed\n");
++    if (status & R1_CC_ERROR)
++        printk("[CARD_STATUS] CC Error\n");
++    if (status & R1_ERROR)
++        printk("[CARD_STATUS] Error\n");
++    if (status & R1_UNDERRUN)
++        printk("[CARD_STATUS] Underrun\n");
++    if (status & R1_OVERRUN)
++        printk("[CARD_STATUS] Overrun\n");
++    if (status & R1_CID_CSD_OVERWRITE)
++        printk("[CARD_STATUS] CID/CSD Overwrite\n");
++    if (status & R1_WP_ERASE_SKIP)
++        printk("[CARD_STATUS] WP Eraser Skip\n");
++    if (status & R1_CARD_ECC_DISABLED)
++        printk("[CARD_STATUS] Card ECC Disabled\n");
++    if (status & R1_ERASE_RESET)
++        printk("[CARD_STATUS] Erase Reset\n");
++    if (status & R1_READY_FOR_DATA)
++        printk("[CARD_STATUS] Ready for Data\n");
++    if (status & R1_SWITCH_ERROR)
++        printk("[CARD_STATUS] Switch error\n");
++    if (status & R1_APP_CMD)
++        printk("[CARD_STATUS] App Command\n");
++    
++    printk("[CARD_STATUS] '%s' State\n", state[R1_CURRENT_STATE(status)]);
++}
++
++static void msdc_dump_ocr_reg(struct msdc_host *host, u32 resp)
++{
++    if (resp & (1 << 7))
++        printk("[OCR] Low Voltage Range\n");
++    if (resp & (1 << 15))
++        printk("[OCR] 2.7-2.8 volt\n");
++    if (resp & (1 << 16))
++        printk("[OCR] 2.8-2.9 volt\n");
++    if (resp & (1 << 17))
++        printk("[OCR] 2.9-3.0 volt\n");
++    if (resp & (1 << 18))
++        printk("[OCR] 3.0-3.1 volt\n");
++    if (resp & (1 << 19))
++        printk("[OCR] 3.1-3.2 volt\n");
++    if (resp & (1 << 20))
++        printk("[OCR] 3.2-3.3 volt\n");
++    if (resp & (1 << 21))
++        printk("[OCR] 3.3-3.4 volt\n");
++    if (resp & (1 << 22))
++        printk("[OCR] 3.4-3.5 volt\n");
++    if (resp & (1 << 23))
++        printk("[OCR] 3.5-3.6 volt\n");
++    if (resp & (1 << 24))
++        printk("[OCR] Switching to 1.8V Accepted (S18A)\n");
++    if (resp & (1 << 30))
++        printk("[OCR] Card Capacity Status (CCS)\n");
++    if (resp & (1 << 31))
++        printk("[OCR] Card Power Up Status (Idle)\n");
++    else
++        printk("[OCR] Card Power Up Status (Busy)\n");
++}
++
++static void msdc_dump_rca_resp(struct msdc_host *host, u32 resp)
++{
++    u32 status = (((resp >> 15) & 0x1) << 23) |
++                 (((resp >> 14) & 0x1) << 22) |
++                 (((resp >> 13) & 0x1) << 19) |
++                   (resp & 0x1fff);
++
++    printk("[RCA] 0x%.4x\n", resp >> 16);
++    
++    msdc_dump_card_status(host, status);
++}
++
++static void msdc_dump_io_resp(struct msdc_host *host, u32 resp)
++{
++    u32 flags = (resp >> 8) & 0xFF;
++    char *state[] = {"DIS", "CMD", "TRN", "RFU"};
++
++    if (flags & (1 << 7))
++        printk("[IO] COM_CRC_ERR\n");
++    if (flags & (1 << 6))
++        printk("[IO] Illgal command\n");
++    if (flags & (1 << 3))
++        printk("[IO] Error\n");
++    if (flags & (1 << 2))
++        printk("[IO] RFU\n");
++    if (flags & (1 << 1))
++        printk("[IO] Function number error\n");
++    if (flags & (1 << 0))
++        printk("[IO] Out of range\n");
++
++    printk("[IO] State: %s, Data:0x%x\n", state[(resp >> 12) & 0x3], resp & 0xFF);
++}
++#endif
++
++static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks)
++{
++	u32 base = host->base;
++	u32 timeout, clk_ns;
++
++	host->timeout_ns = ns;
++	host->timeout_clks = clks;
++
++	clk_ns = 1000000000UL / host->sclk;
++	timeout = ns / clk_ns + clks;
++	timeout = timeout >> 16; /* in 65536 sclk cycle unit */
++	timeout = timeout > 1 ? timeout - 1 : 0;
++	timeout = timeout > 255 ? 255 : timeout;
++
++	sdr_set_field(SDC_CFG, SDC_CFG_DTOC, timeout);
++
++/*	printk("Set read data timeout: %dns %dclks -> %d x 65536 cycles\n",
++		ns, clks, timeout + 1);*/
++}
++
++static void msdc_eirq_sdio(void *data)
++{
++	struct msdc_host *host = (struct msdc_host *)data;
++
++//	printk("SDIO EINT\n");
++
++	mmc_signal_sdio_irq(host->mmc);
++}
++
++static void msdc_eirq_cd(void *data)
++{
++	struct msdc_host *host = (struct msdc_host *)data;
++
++//	printk("CD EINT\n");
++
++	tasklet_hi_schedule(&host->card_tasklet);
++}
++
++static void msdc_tasklet_card(unsigned long arg)
++{
++	struct msdc_host *host = (struct msdc_host *)arg;
++	struct msdc_hw *hw = host->hw;
++	u32 base = host->base;
++	u32 inserted;
++	u32 status = 0;
++
++	spin_lock(&host->lock);
++
++	if (hw->get_cd_status) {
++		inserted = hw->get_cd_status();
++	} else {
++		status = sdr_read32(MSDC_PS);
++		inserted = (status & MSDC_PS_CDSTS) ? 0 : 1;
++	}
++
++	host->card_inserted = inserted;
++
++	if (!host->suspend) {
++		host->mmc->f_max = HOST_MAX_MCLK;
++		mmc_detect_change(host->mmc, msecs_to_jiffies(20));
++	}
++
++//	printk("card found<%s>\n", inserted ? "inserted" : "removed");
++
++	spin_unlock(&host->lock);
++}
++
++static void msdc_set_mclk(struct msdc_host *host, int ddr, unsigned int hz)
++{
++	u32 base = host->base;
++	u32 hclk = host->hclk;
++	u32 mode, flags, div, sclk;
++
++	if (!hz) {
++//		printk("set mclk to 0!!!\n");
++		msdc_reset();
++		return;
++	}
++
++	msdc_irq_save(flags);
++
++	if (ddr) {
++		mode = 0x2;
++		if (hz >= (hclk >> 2)) {
++			div = 1;
++			sclk = hclk >> 2;
++		} else {
++			div  = (hclk + ((hz << 2) - 1)) / (hz << 2);
++			sclk = (hclk >> 2) / div;
++		}
++	} else if (hz >= hclk) {
++		mode = 0x1;
++		div = 0;
++		sclk = hclk;
++	} else {
++		mode = 0x0;
++		if (hz >= (hclk >> 1)) {
++			div = 0;
++			sclk = hclk >> 1;
++		} else {
++			div = (hclk + ((hz << 2) - 1)) / (hz << 2);
++			sclk = (hclk >> 2) / div;
++		}
++	}
++
++	sdr_set_field(MSDC_CFG, MSDC_CFG_CKMOD, mode);
++	sdr_set_field(MSDC_CFG, MSDC_CFG_CKDIV, div);
++
++	while (!(sdr_read32(MSDC_CFG) & MSDC_CFG_CKSTB));
++
++	host->sclk = sclk;
++	host->mclk = hz;
++	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
++
++/*	printk("!!! Set<%dKHz> Source<%dKHz> -> sclk<%dKHz>\n",
++		hz / 1000, hclk / 1000, sclk / 1000);
++*/
++	msdc_irq_restore(flags);
++}
++
++static void msdc_abort_data(struct msdc_host *host)
++{
++	u32 base = host->base;
++	struct mmc_command *stop = host->mrq->stop;
++
++//	printk("Need to Abort. dma<%d>\n", host->dma_xfer);
++
++	msdc_reset();
++	msdc_clr_fifo();
++	msdc_clr_int();
++
++	if (stop) {
++//		printk("stop when abort CMD<%d>\n", stop->opcode);
++		msdc_do_command(host, stop, 0, CMD_TIMEOUT);
++	}
++}
++
++static unsigned int msdc_command_start(struct msdc_host *host,
++		struct mmc_command *cmd, int tune, unsigned long timeout)
++{
++	u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
++		MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
++		MSDC_INT_ACMD19_DONE;
++	u32 base = host->base;
++	u32 opcode = cmd->opcode;
++	u32 rawcmd;
++	u32 resp;
++	unsigned long tmo;
++
++	if (opcode == MMC_SEND_OP_COND || opcode == SD_APP_OP_COND)
++		resp = RESP_R3;
++	else if (opcode == MMC_SET_RELATIVE_ADDR || opcode == SD_SEND_RELATIVE_ADDR)
++		resp = (mmc_cmd_type(cmd) == MMC_CMD_BCR) ? RESP_R6 : RESP_R1;
++	else if (opcode == MMC_FAST_IO)
++		resp = RESP_R4;
++	else if (opcode == MMC_GO_IRQ_STATE)
++		resp = RESP_R5;
++	else if (opcode == MMC_SELECT_CARD)
++		resp = (cmd->arg != 0) ? RESP_R1B : RESP_NONE;
++	else if (opcode == SD_IO_RW_DIRECT || opcode == SD_IO_RW_EXTENDED)
++		resp = RESP_R1;
++	else if (opcode == SD_SEND_IF_COND && (mmc_cmd_type(cmd) == MMC_CMD_BCR))
++		resp = RESP_R1;
++	else {
++		switch (mmc_resp_type(cmd)) {
++		case MMC_RSP_R1:
++			resp = RESP_R1;
++			break;
++		case MMC_RSP_R1B:
++			resp = RESP_R1B;
++			break;
++		case MMC_RSP_R2:
++			resp = RESP_R2;
++			break;
++		case MMC_RSP_R3:
++			resp = RESP_R3;
++			break;
++		case MMC_RSP_NONE:
++		default:
++			resp = RESP_NONE;
++			break;
++		}
++	}
++
++	cmd->error = 0;
++	rawcmd = opcode | msdc_rsp[resp] << 7 | host->blksz << 16;
++
++	if (opcode == MMC_READ_MULTIPLE_BLOCK) {
++		rawcmd |= (2 << 11);
++	} else if (opcode == MMC_READ_SINGLE_BLOCK) {
++		rawcmd |= (1 << 11);
++	} else if (opcode == MMC_WRITE_MULTIPLE_BLOCK) {
++		rawcmd |= ((2 << 11) | (1 << 13));
++	} else if (opcode == MMC_WRITE_BLOCK) {
++		rawcmd |= ((1 << 11) | (1 << 13));
++	} else if (opcode == SD_IO_RW_EXTENDED) {
++		if (cmd->data->flags & MMC_DATA_WRITE)
++			rawcmd |= (1 << 13);
++		if (cmd->data->blocks > 1)
++			rawcmd |= (2 << 11);
++		else
++			rawcmd |= (1 << 11);
++	} else if (opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int)-1) {
++		rawcmd |= (1 << 14);
++	} else if ((opcode == SD_APP_SEND_SCR) ||
++			(opcode == SD_APP_SEND_NUM_WR_BLKS) ||
++			(opcode == SD_SWITCH && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
++			(opcode == SD_APP_SD_STATUS && (mmc_cmd_type(cmd) == MMC_CMD_ADTC)) ||
++			(opcode == MMC_SEND_EXT_CSD && (mmc_cmd_type(cmd) == MMC_CMD_ADTC))) {
++		rawcmd |= (1 << 11);
++	} else if (opcode == MMC_STOP_TRANSMISSION) {
++		rawcmd |= (1 << 14);
++		rawcmd &= ~(0x0FFF << 16);
++	}
++
++//	printk("CMD<%d><0x%.8x> Arg<0x%.8x>\n", opcode , rawcmd, cmd->arg);
++
++	tmo = jiffies + timeout;
++
++	if (opcode == MMC_SEND_STATUS) {
++		for (;;) {
++			if (!sdc_is_cmd_busy())
++				break;
++
++			if (time_after(jiffies, tmo)) {
++				//printk("XXX cmd_busy timeout: before CMD<%d>\n", opcode);
++				cmd->error = (unsigned int)-ETIMEDOUT;
++				msdc_reset();
++				goto end;
++			}
++		}
++	} else {
++		for (;;) {
++			if (!sdc_is_busy())
++				break;
++			if (time_after(jiffies, tmo)) {
++				//printk("XXX sdc_busy timeout: before CMD<%d>\n", opcode);
++				cmd->error = (unsigned int)-ETIMEDOUT;
++				msdc_reset();
++				goto end;
++			}
++		}
++	}
++
++	//BUG_ON(in_interrupt());
++	host->cmd = cmd;
++	host->cmd_rsp = resp;
++	init_completion(&host->cmd_done);
++	sdr_set_bits(MSDC_INTEN, wints);
++	sdc_send_cmd(rawcmd, cmd->arg);
++
++end:
++	return cmd->error;
++}
++
++static unsigned int msdc_command_resp(struct msdc_host *host, struct mmc_command *cmd,
++				int tune, unsigned long timeout)
++{
++	u32 base = host->base;
++	//u32 opcode = cmd->opcode;
++	u32 resp;
++	u32 wints = MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO |
++		MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO |
++		MSDC_INT_ACMD19_DONE;
++
++	resp = host->cmd_rsp;
++
++	BUG_ON(in_interrupt());
++	spin_unlock(&host->lock);
++	if (!wait_for_completion_timeout(&host->cmd_done, 10*timeout)) {
++		//printk("XXX CMD<%d> wait_for_completion timeout ARG<0x%.8x>\n", opcode, cmd->arg);
++		cmd->error = (unsigned int)-ETIMEDOUT;
++		msdc_reset();
++	}
++	spin_lock(&host->lock);
++
++	sdr_clr_bits(MSDC_INTEN, wints);
++	host->cmd = NULL;
++
++	if (!tune)
++		return cmd->error;
++
++	/* memory card CRC */
++	if (host->hw->flags & MSDC_REMOVABLE && cmd->error == (unsigned int)(-EIO) ) {
++		if (sdr_read32(SDC_CMD) & 0x1800) {
++			msdc_abort_data(host);
++		} else {
++			msdc_reset();
++			msdc_clr_fifo();
++			msdc_clr_int();
++		}
++		cmd->error = msdc_tune_cmdrsp(host,cmd);
++	}
++
++	return cmd->error;
++}
++
++static unsigned int msdc_do_command(struct msdc_host *host, struct mmc_command *cmd,
++			int tune, unsigned long timeout)
++{
++	if (!msdc_command_start(host, cmd, tune, timeout))
++		msdc_command_resp(host, cmd, tune, timeout);
++
++	//printk("        return<%d> resp<0x%.8x>\n", cmd->error, cmd->resp[0]);
++	return cmd->error;
++}
++
++static int msdc_pio_abort(struct msdc_host *host, struct mmc_data *data, unsigned long tmo)
++{
++	u32  base = host->base;
++	int  ret = 0;
++
++	if (atomic_read(&host->abort))
++		ret = 1;
++
++	if (time_after(jiffies, tmo)) {
++		data->error = (unsigned int)-ETIMEDOUT;
++		//printk("XXX PIO Data Timeout: CMD<%d>\n", host->mrq->cmd->opcode);
++		ret = 1;
++	}
++
++	if (ret) {
++		msdc_reset();
++		msdc_clr_fifo();
++		msdc_clr_int();
++		//printk("msdc pio find abort\n");
++	}
++
++	return ret;
++}
++
++static int msdc_pio_read(struct msdc_host *host, struct mmc_data *data)
++{
++	struct scatterlist *sg = data->sg;
++	u32  base = host->base;
++	u32  num = data->sg_len;
++	u32 *ptr;
++	u8  *u8ptr;
++	u32  left;
++	u32  count, size = 0;
++	u32  wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
++	unsigned long tmo = jiffies + DAT_TIMEOUT;
++
++	sdr_set_bits(MSDC_INTEN, wints);
++	while (num) {
++		left = sg_dma_len(sg);
++		ptr = sg_virt(sg);
++		while (left) {
++			if ((left >=  MSDC_FIFO_THD) && (msdc_rxfifocnt() >= MSDC_FIFO_THD)) {
++				count = MSDC_FIFO_THD >> 2;
++				do {
++					*ptr++ = msdc_fifo_read32();
++				} while (--count);
++				left -= MSDC_FIFO_THD;
++			} else if ((left < MSDC_FIFO_THD) && msdc_rxfifocnt() >= left) {
++				while (left > 3) {
++					*ptr++ = msdc_fifo_read32();
++					left -= 4;
++				}
++
++				u8ptr = (u8 *)ptr;
++				while(left) {
++					* u8ptr++ = msdc_fifo_read8();
++					left--;
++				}
++			}
++
++			if (msdc_pio_abort(host, data, tmo))
++				goto end;
++		}
++		size += sg_dma_len(sg);
++		sg = sg_next(sg); num--;
++	}
++end:
++	data->bytes_xfered += size;
++	//printk("        PIO Read<%d>bytes\n", size);
++
++	sdr_clr_bits(MSDC_INTEN, wints);
++	if(data->error)
++		printk("read pio data->error<%d> left<%d> size<%d>\n", data->error, left, size);
++
++	return data->error;
++}
++
++static int msdc_pio_write(struct msdc_host* host, struct mmc_data *data)
++{
++	u32  base = host->base;
++	struct scatterlist *sg = data->sg;
++	u32  num = data->sg_len;
++	u32 *ptr;
++	u8  *u8ptr;
++	u32  left;
++	u32  count, size = 0;
++	u32  wints = MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
++	unsigned long tmo = jiffies + DAT_TIMEOUT;
++
++	sdr_set_bits(MSDC_INTEN, wints);
++	while (num) {
++		left = sg_dma_len(sg);
++		ptr = sg_virt(sg);
++
++		while (left) {
++			if (left >= MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
++				count = MSDC_FIFO_SZ >> 2;
++				do {
++					msdc_fifo_write32(*ptr); ptr++;
++				} while (--count);
++				left -= MSDC_FIFO_SZ;
++			} else if (left < MSDC_FIFO_SZ && msdc_txfifocnt() == 0) {
++				while (left > 3) {
++					msdc_fifo_write32(*ptr); ptr++;
++					left -= 4;
++				}
++
++				u8ptr = (u8*)ptr;
++				while( left) {
++					msdc_fifo_write8(*u8ptr);
++					u8ptr++;
++					left--;
++				}
++			}
++
++			if (msdc_pio_abort(host, data, tmo))
++				goto end;
++		}
++		size += sg_dma_len(sg);
++		sg = sg_next(sg); num--;
++	}
++end:
++	data->bytes_xfered += size;
++	//printk("        PIO Write<%d>bytes\n", size);
++	if(data->error)
++		printk("write pio data->error<%d>\n", data->error);
++
++	sdr_clr_bits(MSDC_INTEN, wints);
++
++	return data->error;
++}
++
++static void msdc_dma_start(struct msdc_host *host)
++{
++	u32 base = host->base;
++	u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
++
++	sdr_set_bits(MSDC_INTEN, wints);
++	sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
++
++	//printk("DMA start\n");
++}
++
++static void msdc_dma_stop(struct msdc_host *host)
++{
++	u32 base = host->base;
++	u32 wints = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | MSDC_INTEN_DATCRCERR;
++
++	//printk("DMA status: 0x%.8x\n",sdr_read32(MSDC_DMA_CFG));
++
++	sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1);
++	while (sdr_read32(MSDC_DMA_CFG) & MSDC_DMA_CFG_STS);
++	sdr_clr_bits(MSDC_INTEN, wints); /* Not just xfer_comp */
++
++	//printk("DMA stop\n");
++}
++
++static u8 msdc_dma_calcs(u8 *buf, u32 len)
++{
++	u32 i, sum = 0;
++
++	for (i = 0; i < len; i++)
++		sum += buf[i];
++
++	return 0xFF - (u8)sum;
++}
++
++static int msdc_dma_config(struct msdc_host *host, struct msdc_dma *dma)
++{
++	u32 base = host->base;
++	u32 sglen = dma->sglen;
++	u32 j, num, bdlen;
++	u8  blkpad, dwpad, chksum;
++	struct scatterlist *sg = dma->sg;
++	gpd_t *gpd;
++	bd_t *bd;
++
++	switch (dma->mode) {
++	case MSDC_MODE_DMA_BASIC:
++		BUG_ON(dma->xfersz > 65535);
++		BUG_ON(dma->sglen != 1);
++		sdr_write32(MSDC_DMA_SA, PHYSADDR(sg_dma_address(sg)));
++		sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_LASTBUF, 1);
++		sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_XFERSZ, sg_dma_len(sg));
++		sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
++		sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 0);
++		break;
++
++	case MSDC_MODE_DMA_DESC:
++		blkpad = (dma->flags & DMA_FLAG_PAD_BLOCK) ? 1 : 0;
++		dwpad  = (dma->flags & DMA_FLAG_PAD_DWORD) ? 1 : 0;
++		chksum = (dma->flags & DMA_FLAG_EN_CHKSUM) ? 1 : 0;
++
++		num = (sglen + MAX_BD_PER_GPD - 1) / MAX_BD_PER_GPD;
++		BUG_ON(num !=1 );
++
++		gpd = dma->gpd;
++		bd = dma->bd;
++		bdlen = sglen;
++
++		gpd->hwo = 1;  /* hw will clear it */
++		gpd->bdp = 1;
++		gpd->chksum = 0;  /* need to clear first. */
++		gpd->chksum = (chksum ? msdc_dma_calcs((u8 *)gpd, 16) : 0);
++
++		for (j = 0; j < bdlen; j++) {
++			msdc_init_bd(&bd[j], blkpad, dwpad, sg_dma_address(sg), sg_dma_len(sg));
++			if( j == bdlen - 1)
++				bd[j].eol = 1;
++			else
++				bd[j].eol = 0;
++			bd[j].chksum = 0; /* checksume need to clear first */
++			bd[j].chksum = (chksum ? msdc_dma_calcs((u8 *)(&bd[j]), 16) : 0);
++			sg++;
++		}
++
++		dma->used_gpd += 2;
++		dma->used_bd += bdlen;
++
++		sdr_set_field(MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, chksum);
++		sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_BRUSTSZ, dma->burstsz);
++		sdr_set_field(MSDC_DMA_CTRL, MSDC_DMA_CTRL_MODE, 1);
++		sdr_write32(MSDC_DMA_SA, PHYSADDR((u32)dma->gpd_addr));
++		break;
++	}
++
++//	printk("DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
++//	printk("DMA_CFG  = 0x%x\n", sdr_read32(MSDC_DMA_CFG));
++//	printk("DMA_SA   = 0x%x\n", sdr_read32(MSDC_DMA_SA));
++
++	return 0;
++}
++
++static void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
++			struct scatterlist *sg, unsigned int sglen)
++{
++	BUG_ON(sglen > MAX_BD_NUM);
++
++	dma->sg = sg;
++	dma->flags = DMA_FLAG_EN_CHKSUM;
++	dma->sglen = sglen;
++	dma->xfersz = host->xfer_size;
++	dma->burstsz = MSDC_BRUST_64B;
++
++	if (sglen == 1 && sg_dma_len(sg) <= MAX_DMA_CNT)
++		dma->mode = MSDC_MODE_DMA_BASIC;
++	else
++		dma->mode = MSDC_MODE_DMA_DESC;
++
++//	printk("DMA mode<%d> sglen<%d> xfersz<%d>\n", dma->mode, dma->sglen, dma->xfersz);
++
++	msdc_dma_config(host, dma);
++}
++
++static void msdc_set_blknum(struct msdc_host *host, u32 blknum)
++{
++	u32 base = host->base;
++
++	sdr_write32(SDC_BLK_NUM, blknum);
++}
++
++static int msdc_do_request(struct mmc_host*mmc, struct mmc_request*mrq)
++{
++	struct msdc_host *host = mmc_priv(mmc);
++	struct mmc_command *cmd;
++	struct mmc_data *data;
++	u32 base = host->base;
++	unsigned int left=0;
++	int dma = 0, read = 1, dir = DMA_FROM_DEVICE, send_type=0;
++
++#define SND_DAT 0
++#define SND_CMD 1
++
++	BUG_ON(mmc == NULL);
++	BUG_ON(mrq == NULL);
++
++	host->error = 0;
++	atomic_set(&host->abort, 0);
++
++	cmd  = mrq->cmd;
++	data = mrq->cmd->data;
++
++	if (!data) {
++		send_type = SND_CMD;
++		if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
++			goto done;
++	} else {
++		BUG_ON(data->blksz > HOST_MAX_BLKSZ);
++		send_type=SND_DAT;
++
++		data->error = 0;
++		read = data->flags & MMC_DATA_READ ? 1 : 0;
++		host->data = data;
++		host->xfer_size = data->blocks * data->blksz;
++		host->blksz = data->blksz;
++
++		host->dma_xfer = dma = ((host->xfer_size >= 512) ? 1 : 0);
++
++		if (read)
++			if ((host->timeout_ns != data->timeout_ns) ||
++					(host->timeout_clks != data->timeout_clks))
++				msdc_set_timeout(host, data->timeout_ns, data->timeout_clks);
++
++			msdc_set_blknum(host, data->blocks);
++
++			if (dma) {
++				msdc_dma_on();
++				init_completion(&host->xfer_done);
++
++				if (msdc_command_start(host, cmd, 1, CMD_TIMEOUT) != 0)
++					goto done;
++
++				dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
++				dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
++				msdc_dma_setup(host, &host->dma, data->sg, data->sg_len);
++
++				if (msdc_command_resp(host, cmd, 1, CMD_TIMEOUT) != 0)
++					goto done;
++
++				msdc_dma_start(host);
++
++				spin_unlock(&host->lock);
++				if (!wait_for_completion_timeout(&host->xfer_done, DAT_TIMEOUT)) {
++					/*printk("XXX CMD<%d> wait xfer_done<%d> timeout!!\n", cmd->opcode, data->blocks * data->blksz);
++					printk("    DMA_SA   = 0x%x\n", sdr_read32(MSDC_DMA_SA));
++					printk("    DMA_CA   = 0x%x\n", sdr_read32(MSDC_DMA_CA));
++					printk("    DMA_CTRL = 0x%x\n", sdr_read32(MSDC_DMA_CTRL));
++					printk("    DMA_CFG  = 0x%x\n", sdr_read32(MSDC_DMA_CFG));*/
++					data->error = (unsigned int)-ETIMEDOUT;
++
++					msdc_reset();
++					msdc_clr_fifo();
++					msdc_clr_int();
++				}
++				spin_lock(&host->lock);
++				msdc_dma_stop(host);
++			} else {
++				if (msdc_do_command(host, cmd, 1, CMD_TIMEOUT) != 0)
++					goto done;
++
++				if (read) {
++					if (msdc_pio_read(host, data))
++						goto done;
++				} else {
++					if (msdc_pio_write(host, data))
++						goto done;
++				}
++
++			if (!read) {
++				while (1) {
++					left = msdc_txfifocnt();
++					if (left == 0) {
++						break;
++					}
++					if (msdc_pio_abort(host, data, jiffies + DAT_TIMEOUT)) {
++						break;
++					/* Fix me: what about if data error, when stop ? how to? */
++					}
++				}
++			} else {
++				/* Fix me: read case: need to check CRC error */	
++			}
++
++			/* For write case: SDCBUSY and Xfer_Comp will assert when DAT0 not busy. 
++			   For read case : SDCBUSY and Xfer_Comp will assert when last byte read out from FIFO.
++			*/
++
++			/* try not to wait xfer_comp interrupt. 
++			the next command will check SDC_BUSY. 
++			SDC_BUSY means xfer_comp assert 
++			*/ 
++
++		} // PIO mode 
++
++		/* Last: stop transfer */
++		if (data->stop){ 
++			if (msdc_do_command(host, data->stop, 0, CMD_TIMEOUT) != 0) {
++				goto done; 
++			}
++		} 
++	}
++
++done:
++	if (data != NULL) {
++		host->data = NULL;
++		host->dma_xfer = 0;    
++		if (dma != 0) {
++			msdc_dma_off();     
++			host->dma.used_bd  = 0;
++			host->dma.used_gpd = 0;
++			dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, dir);
++		}
++		host->blksz = 0;  
++
++	//	printk("CMD<%d> data<%s %s> blksz<%d> block<%d> error<%d>",cmd->opcode, (dma? "dma":"pio\n"), 
++	//		(read ? "read ":"write") ,data->blksz, data->blocks, data->error);                
++	}
++
++	if (mrq->cmd->error) host->error = 0x001;
++	if (mrq->data && mrq->data->error) host->error |= 0x010;     
++	if (mrq->stop && mrq->stop->error) host->error |= 0x100; 
++
++	//if (host->error) printk("host->error<%d>\n", host->error);     
++
++	return host->error;
++}
++
++static int msdc_app_cmd(struct mmc_host *mmc, struct msdc_host *host)
++{
++    struct mmc_command cmd;    
++    struct mmc_request mrq;
++    u32 err; 
++
++    memset(&cmd, 0, sizeof(struct mmc_command));    
++    cmd.opcode = MMC_APP_CMD;    
++#if 0   /* bug: we meet mmc->card is null when ACMD6 */   
++    cmd.arg = mmc->card->rca << 16;
++#else 
++    cmd.arg = host->app_cmd_arg;     
++#endif    
++    cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
++
++    memset(&mrq, 0, sizeof(struct mmc_request));
++    mrq.cmd = &cmd; cmd.mrq = &mrq;
++    cmd.data = NULL;        
++
++    err = msdc_do_command(host, &cmd, 0, CMD_TIMEOUT);     
++    return err;      	
++}
++
++static int msdc_tune_cmdrsp(struct msdc_host*host, struct mmc_command *cmd)
++{
++    int result = -1;
++    u32 base = host->base;
++    u32 rsmpl, cur_rsmpl, orig_rsmpl;
++    u32 rrdly, cur_rrdly = 0, orig_rrdly;
++    u32 skip = 1;
++    
++    /* ==== don't support 3.0 now ====
++           1: R_SMPL[1] 
++           2: PAD_CMD_RESP_RXDLY[26:22] 
++	    ==========================*/
++
++    // save the previous tune result 
++    sdr_get_field(MSDC_IOCON,    MSDC_IOCON_RSPL,        orig_rsmpl);
++    sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, orig_rrdly);
++
++    rrdly = 0; 
++    do {
++        for (rsmpl = 0; rsmpl < 2; rsmpl++) {
++            /* Lv1: R_SMPL[1] */    	
++            cur_rsmpl = (orig_rsmpl + rsmpl) % 2;         
++            if (skip == 1) {
++                skip = 0; 	
++                continue;	
++            }
++            sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, cur_rsmpl); 
++
++            if (host->app_cmd) {
++                result = msdc_app_cmd(host->mmc, host);	
++                if (result) {
++                    //printk("TUNE_CMD app_cmd<%d> failed: RESP_RXDLY<%d>,R_SMPL<%d>\n", 
++                      //   host->mrq->cmd->opcode, cur_rrdly, cur_rsmpl);
++                    continue;
++                } 
++            }          
++            result = msdc_do_command(host, cmd, 0, CMD_TIMEOUT); // not tune.             
++            //printk("TUNE_CMD<%d> %s PAD_CMD_RESP_RXDLY[26:22]<%d> R_SMPL[1]<%d>\n", cmd->opcode,
++//                       (result == 0) ? "PASS" : "FAIL", cur_rrdly, cur_rsmpl);
++                       	
++            if (result == 0) {
++                return 0; 	
++            }                        	
++            if (result != (unsigned int)(-EIO)) { 
++              //  printk("TUNE_CMD<%d> Error<%d> not -EIO\n", cmd->opcode, result);	
++                return result;	 
++            }
++
++            /* should be EIO */
++            if (sdr_read32(SDC_CMD) & 0x1800) { /* check if has data phase */ 
++                msdc_abort_data(host);
++            }
++        }
++		
++        /* Lv2: PAD_CMD_RESP_RXDLY[26:22] */              	
++        cur_rrdly = (orig_rrdly + rrdly + 1) % 32;
++        sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, cur_rrdly);		
++    }while (++rrdly < 32);
++	
++    return result;
++}
++
++/* Support SD2.0 Only */
++static int msdc_tune_bread(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++    struct msdc_host *host = mmc_priv(mmc);
++    u32 base = host->base;
++    u32 ddr=0;
++    u32 dcrc = 0;
++    u32 rxdly, cur_rxdly0, cur_rxdly1;
++    u32 dsmpl, cur_dsmpl,  orig_dsmpl;
++    u32 cur_dat0,  cur_dat1,  cur_dat2,  cur_dat3;
++    u32 cur_dat4,  cur_dat5,  cur_dat6,  cur_dat7;
++    u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
++    u32 orig_dat4, orig_dat5, orig_dat6, orig_dat7;
++    int result = -1;
++    u32 skip = 1;
++
++    sdr_get_field(MSDC_IOCON, MSDC_IOCON_DSPL, orig_dsmpl);
++	
++    /* Tune Method 2. */
++    sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
++
++    rxdly = 0; 
++    do {
++        for (dsmpl = 0; dsmpl < 2; dsmpl++) {
++            cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
++            if (skip == 1) {
++                skip = 0; 	
++                continue;	
++            }             
++            sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
++
++            if (host->app_cmd) {
++                result = msdc_app_cmd(host->mmc, host);	
++                if (result) {
++                    //printk("TUNE_BREAD app_cmd<%d> failed\n", host->mrq->cmd->opcode);	
++                    continue;
++                } 
++            } 
++            result = msdc_do_request(mmc,mrq);
++            
++            sdr_get_field(SDC_DCRC_STS, SDC_DCRC_STS_POS|SDC_DCRC_STS_NEG, dcrc); /* RO */
++            if (!ddr) dcrc &= ~SDC_DCRC_STS_NEG;
++            //printk("TUNE_BREAD<%s> dcrc<0x%x> DATRDDLY0/1<0x%x><0x%x> dsmpl<0x%x>\n",
++                       // (result == 0 && dcrc == 0) ? "PASS" : "FAIL", dcrc,
++                       // sdr_read32(MSDC_DAT_RDDLY0), sdr_read32(MSDC_DAT_RDDLY1), cur_dsmpl);
++
++            /* Fix me: result is 0, but dcrc is still exist */
++            if (result == 0 && dcrc == 0) {
++                goto done;
++            } else {
++                /* there is a case: command timeout, and data phase not processed */
++                if (mrq->data->error != 0 && mrq->data->error != (unsigned int)(-EIO)) {
++                    //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n", 
++                         //      result, mrq->cmd->error, mrq->data->error);	
++                    goto done;     	
++                }
++            }
++        }    
++
++        cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
++        cur_rxdly1 = sdr_read32(MSDC_DAT_RDDLY1);
++
++        /* E1 ECO. YD: Reverse */
++        if (sdr_read32(MSDC_ECO_VER) >= 4) {
++            orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
++            orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
++            orig_dat2 = (cur_rxdly0 >>  8) & 0x1F;
++            orig_dat3 = (cur_rxdly0 >>  0) & 0x1F;
++            orig_dat4 = (cur_rxdly1 >> 24) & 0x1F;
++            orig_dat5 = (cur_rxdly1 >> 16) & 0x1F;
++            orig_dat6 = (cur_rxdly1 >>  8) & 0x1F;
++            orig_dat7 = (cur_rxdly1 >>  0) & 0x1F;
++        } else {   
++            orig_dat0 = (cur_rxdly0 >>  0) & 0x1F;
++            orig_dat1 = (cur_rxdly0 >>  8) & 0x1F;
++            orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
++            orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
++            orig_dat4 = (cur_rxdly1 >>  0) & 0x1F;
++            orig_dat5 = (cur_rxdly1 >>  8) & 0x1F;
++            orig_dat6 = (cur_rxdly1 >> 16) & 0x1F;
++            orig_dat7 = (cur_rxdly1 >> 24) & 0x1F;
++        }
++                
++        if (ddr) {
++            cur_dat0 = (dcrc & (1 << 0) || dcrc & (1 << 8))  ? ((orig_dat0 + 1) % 32) : orig_dat0;
++            cur_dat1 = (dcrc & (1 << 1) || dcrc & (1 << 9))  ? ((orig_dat1 + 1) % 32) : orig_dat1;
++            cur_dat2 = (dcrc & (1 << 2) || dcrc & (1 << 10)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
++            cur_dat3 = (dcrc & (1 << 3) || dcrc & (1 << 11)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
++        } else {
++            cur_dat0 = (dcrc & (1 << 0)) ? ((orig_dat0 + 1) % 32) : orig_dat0;
++            cur_dat1 = (dcrc & (1 << 1)) ? ((orig_dat1 + 1) % 32) : orig_dat1;
++            cur_dat2 = (dcrc & (1 << 2)) ? ((orig_dat2 + 1) % 32) : orig_dat2;
++            cur_dat3 = (dcrc & (1 << 3)) ? ((orig_dat3 + 1) % 32) : orig_dat3;
++        }
++        cur_dat4 = (dcrc & (1 << 4)) ? ((orig_dat4 + 1) % 32) : orig_dat4;
++        cur_dat5 = (dcrc & (1 << 5)) ? ((orig_dat5 + 1) % 32) : orig_dat5;
++        cur_dat6 = (dcrc & (1 << 6)) ? ((orig_dat6 + 1) % 32) : orig_dat6;
++        cur_dat7 = (dcrc & (1 << 7)) ? ((orig_dat7 + 1) % 32) : orig_dat7;
++
++        cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);
++        cur_rxdly1 = (cur_dat4 << 24) | (cur_dat5 << 16) | (cur_dat6 << 8) | (cur_dat7 << 0);
++
++        sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);
++        sdr_write32(MSDC_DAT_RDDLY1, cur_rxdly1);
++
++    } while (++rxdly < 32);   
++          
++done:
++    return result;
++}
++
++static int msdc_tune_bwrite(struct mmc_host *mmc,struct mmc_request *mrq)
++{
++	  struct msdc_host *host = mmc_priv(mmc);
++    u32 base = host->base;
++
++    u32 wrrdly, cur_wrrdly = 0, orig_wrrdly;
++    u32 dsmpl,  cur_dsmpl,  orig_dsmpl;
++    u32 rxdly,  cur_rxdly0;
++    u32 orig_dat0, orig_dat1, orig_dat2, orig_dat3;
++    u32 cur_dat0,  cur_dat1,  cur_dat2,  cur_dat3;
++    int result = -1;
++    u32 skip = 1;
++
++    // MSDC_IOCON_DDR50CKD need to check. [Fix me] 
++    
++    sdr_get_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, orig_wrrdly);
++    sdr_get_field(MSDC_IOCON,    MSDC_IOCON_DSPL,        orig_dsmpl );
++
++    /* Tune Method 2. just DAT0 */  
++    sdr_set_field(MSDC_IOCON, MSDC_IOCON_DDLSEL, 1);
++    cur_rxdly0 = sdr_read32(MSDC_DAT_RDDLY0);
++    
++    /* E1 ECO. YD: Reverse */
++    if (sdr_read32(MSDC_ECO_VER) >= 4) {
++        orig_dat0 = (cur_rxdly0 >> 24) & 0x1F;
++        orig_dat1 = (cur_rxdly0 >> 16) & 0x1F;
++        orig_dat2 = (cur_rxdly0 >>  8) & 0x1F;
++        orig_dat3 = (cur_rxdly0 >>  0) & 0x1F;
++    } else {
++        orig_dat0 = (cur_rxdly0 >>  0) & 0x1F;
++        orig_dat1 = (cur_rxdly0 >>  8) & 0x1F;
++        orig_dat2 = (cur_rxdly0 >> 16) & 0x1F;
++        orig_dat3 = (cur_rxdly0 >> 24) & 0x1F;
++    }
++
++    rxdly = 0;
++    do {
++        wrrdly = 0;
++        do {    
++            for (dsmpl = 0; dsmpl < 2; dsmpl++) {
++                cur_dsmpl = (orig_dsmpl + dsmpl) % 2;
++                if (skip == 1) {
++                    skip = 0;
++                    continue; 	
++                }    
++                sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, cur_dsmpl);
++                
++                if (host->app_cmd) {
++                    result = msdc_app_cmd(host->mmc, host);	
++                    if (result) {
++                        //printk("TUNE_BWRITE app_cmd<%d> failed\n", host->mrq->cmd->opcode);	
++                        continue;
++                    } 
++                }             
++                result = msdc_do_request(mmc,mrq);
++            
++                //printk("TUNE_BWRITE<%s> DSPL<%d> DATWRDLY<%d> MSDC_DAT_RDDLY0<0x%x>\n", 
++                  //        result == 0 ? "PASS" : "FAIL", 
++                    //      cur_dsmpl, cur_wrrdly, cur_rxdly0);
++            
++                if (result == 0) {
++                    goto done;
++                }
++                else {
++                    /* there is a case: command timeout, and data phase not processed */
++                    if (mrq->data->error != (unsigned int)(-EIO)) {
++                        //printk("TUNE_READ: result<0x%x> cmd_error<%d> data_error<%d>\n", 
++                        //  &&         result, mrq->cmd->error, mrq->data->error);	
++                        goto done;     	
++                    }
++                }       
++            }
++            cur_wrrdly = (orig_wrrdly + wrrdly + 1) % 32;
++            sdr_set_field(MSDC_PAD_TUNE, MSDC_PAD_TUNE_DATWRDLY, cur_wrrdly);             
++        } while (++wrrdly < 32); 
++        
++        cur_dat0 = (orig_dat0 + rxdly) % 32; /* only adjust bit-1 for crc */
++        cur_dat1 = orig_dat1;
++        cur_dat2 = orig_dat2;
++        cur_dat3 = orig_dat3;                    
++    
++        cur_rxdly0 = (cur_dat0 << 24) | (cur_dat1 << 16) | (cur_dat2 << 8) | (cur_dat3 << 0);       
++        sdr_write32(MSDC_DAT_RDDLY0, cur_rxdly0);    
++    } while (++rxdly < 32); 
++
++done:
++    return result;
++}
++
++static int msdc_get_card_status(struct mmc_host *mmc, struct msdc_host *host, u32 *status)
++{
++	struct mmc_command cmd;
++	struct mmc_request mrq;
++	u32 err;
++
++	memset(&cmd, 0, sizeof(struct mmc_command));
++	cmd.opcode = MMC_SEND_STATUS;
++	if (mmc->card) {
++		cmd.arg = mmc->card->rca << 16;
++	} else {
++		//printk("cmd13 mmc card is null\n");
++		cmd.arg = host->app_cmd_arg;
++	}
++	cmd.flags = MMC_RSP_SPI_R2 | MMC_RSP_R1 | MMC_CMD_AC;
++
++	memset(&mrq, 0, sizeof(struct mmc_request));
++	mrq.cmd = &cmd; cmd.mrq = &mrq;
++	cmd.data = NULL;
++
++	err = msdc_do_command(host, &cmd, 1, CMD_TIMEOUT);
++
++	if (status)
++		*status = cmd.resp[0];
++
++	return err;
++}
++
++static int msdc_check_busy(struct mmc_host *mmc, struct msdc_host *host)
++{
++	u32 err = 0;
++	u32 status = 0;
++
++	do {
++		err = msdc_get_card_status(mmc, host, &status);
++		if (err)
++			return err;
++		/* need cmd12? */
++		//printk("cmd<13> resp<0x%x>\n", status);
++	} while (R1_CURRENT_STATE(status) == 7);
++
++	return err;
++}
++
++static int msdc_tune_request(struct mmc_host *mmc, struct mmc_request *mrq)
++{
++	struct msdc_host *host = mmc_priv(mmc);
++	struct mmc_command *cmd;
++	struct mmc_data *data;
++	int ret=0, read;
++
++	cmd  = mrq->cmd;
++	data = mrq->cmd->data;
++
++	read = data->flags & MMC_DATA_READ ? 1 : 0;
++
++	if (read) {
++		if (data->error == (unsigned int)(-EIO))
++			ret = msdc_tune_bread(mmc,mrq);
++	} else {
++		ret = msdc_check_busy(mmc, host);
++		if (ret){
++			//printk("XXX cmd13 wait program done failed\n");
++			return ret;
++		}
++		/* CRC and TO */
++		/* Fix me: don't care card status? */
++		ret = msdc_tune_bwrite(mmc,mrq);
++	}
++
++	return ret;
++}
++
++static void msdc_ops_request(struct mmc_host *mmc,struct mmc_request *mrq)
++{
++	struct msdc_host *host = mmc_priv(mmc);
++
++	if (host->mrq) {
++		//printk("XXX host->mrq<0x%.8x>\n", (int)host->mrq);
++		BUG();
++	}
++	if (!is_card_present(host) || host->power_mode == MMC_POWER_OFF) {
++		//printk("cmd<%d> card<%d> power<%d>\n", mrq->cmd->opcode, is_card_present(host), host->power_mode);
++		mrq->cmd->error = (unsigned int)-ENOMEDIUM;
++		mrq->done(mrq);
++		return;
++	}
++	spin_lock(&host->lock);
++
++	host->mrq = mrq;
++
++	if (msdc_do_request(mmc,mrq))
++		if(host->hw->flags & MSDC_REMOVABLE && mrq->data && mrq->data->error)
++			msdc_tune_request(mmc,mrq);
++
++	if (mrq->cmd->opcode == MMC_APP_CMD) {
++		host->app_cmd = 1;
++		host->app_cmd_arg = mrq->cmd->arg;  /* save the RCA */
++	} else {
++		host->app_cmd = 0;
++	}
++
++	host->mrq = NULL;
++
++	spin_unlock(&host->lock);
++
++	mmc_request_done(mmc, mrq);
++}
++
++/* called by ops.set_ios */
++static void msdc_set_buswidth(struct msdc_host *host, u32 width)
++{
++    u32 base = host->base;
++    u32 val = sdr_read32(SDC_CFG);
++    
++    val &= ~SDC_CFG_BUSWIDTH;
++    
++    switch (width) {
++    default:
++    case MMC_BUS_WIDTH_1:
++        width = 1;
++        val |= (MSDC_BUS_1BITS << 16);
++        break;
++    case MMC_BUS_WIDTH_4:
++        val |= (MSDC_BUS_4BITS << 16);
++        break;
++    case MMC_BUS_WIDTH_8:
++        val |= (MSDC_BUS_8BITS << 16);
++        break;
++    }
++    
++    sdr_write32(SDC_CFG, val);
++
++    //printk("Bus Width = %d\n", width);
++}
++
++/* ops.set_ios */
++static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
++{
++	struct msdc_host *host = mmc_priv(mmc);
++	struct msdc_hw *hw=host->hw;
++	u32 base = host->base;
++	u32 ddr = 0;
++
++#ifdef MT6575_SD_DEBUG
++	static char *vdd[] = {
++	"1.50v", "1.55v", "1.60v", "1.65v", "1.70v", "1.80v", "1.90v",
++	"2.00v", "2.10v", "2.20v", "2.30v", "2.40v", "2.50v", "2.60v",
++	"2.70v", "2.80v", "2.90v", "3.00v", "3.10v", "3.20v", "3.30v",
++	"3.40v", "3.50v", "3.60v"		
++	};
++	static char *power_mode[] = {
++	"OFF", "UP", "ON"
++	};
++	static char *bus_mode[] = {
++	"UNKNOWN", "OPENDRAIN", "PUSHPULL"
++	};
++	static char *timing[] = {
++	"LEGACY", "MMC_HS", "SD_HS"
++	};
++
++	/*printk("SET_IOS: CLK(%dkHz), BUS(%s), BW(%u), PWR(%s), VDD(%s), TIMING(%s)\n",
++	ios->clock / 1000, bus_mode[ios->bus_mode],
++	(ios->bus_width == MMC_BUS_WIDTH_4) ? 4 : 1,
++	power_mode[ios->power_mode], vdd[ios->vdd], timing[ios->timing]);*/
++#endif
++
++	msdc_set_buswidth(host, ios->bus_width);
++
++	/* Power control ??? */
++	switch (ios->power_mode) {
++	case MMC_POWER_OFF:
++	case MMC_POWER_UP:
++		// msdc_set_power_mode(host, ios->power_mode); /* --- by chhung */
++		break;
++	case MMC_POWER_ON:
++		host->power_mode = MMC_POWER_ON;
++		break;
++	default:
++		break;
++	}
++
++	/* Clock control */
++	if (host->mclk != ios->clock) {
++		if(ios->clock > 25000000) {
++			//printk("SD data latch edge<%d>\n", hw->data_edge);
++			sdr_set_field(MSDC_IOCON, MSDC_IOCON_RSPL, hw->cmd_edge);
++			sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL, hw->data_edge);
++		} else {
++			sdr_write32(MSDC_IOCON,      0x00000000);
++			sdr_write32(MSDC_DAT_RDDLY0, 0x10101010);	// for MT7620 E2 and afterward
++			sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
++			sdr_write32(MSDC_PAD_TUNE,   0x84101010);	// for MT7620 E2 and afterward
++		}
++		msdc_set_mclk(host, ddr, ios->clock);
++	}
++}
++
++/* ops.get_ro */
++static int msdc_ops_get_ro(struct mmc_host *mmc)
++{
++    struct msdc_host *host = mmc_priv(mmc);
++    u32 base = host->base;
++    unsigned long flags;
++    int ro = 0;
++
++    if (host->hw->flags & MSDC_WP_PIN_EN) { /* set for card */
++        spin_lock_irqsave(&host->lock, flags);
++        ro = (sdr_read32(MSDC_PS) >> 31);
++        spin_unlock_irqrestore(&host->lock, flags);
++    }
++    return ro;
++}
++
++/* ops.get_cd */
++static int msdc_ops_get_cd(struct mmc_host *mmc)
++{
++    struct msdc_host *host = mmc_priv(mmc);
++    u32 base = host->base;    
++    unsigned long flags;
++    int present = 1;
++
++    /* for sdio, MSDC_REMOVABLE not set, always return 1 */
++    if (!(host->hw->flags & MSDC_REMOVABLE)) {
++        /* For sdio, read H/W always get<1>, but may timeout some times */       	    	
++#if 1
++        host->card_inserted = 1;       
++        return 1;
++#else
++        host->card_inserted = (host->pm_state.event == PM_EVENT_USER_RESUME) ? 1 : 0; 
++        printk("sdio ops_get_cd<%d>\n", host->card_inserted);
++        return host->card_inserted; 
++#endif
++    }
++
++    /* MSDC_CD_PIN_EN set for card */
++    if (host->hw->flags & MSDC_CD_PIN_EN) {
++        spin_lock_irqsave(&host->lock, flags);
++#if 0        
++        present = host->card_inserted;  /* why not read from H/W: Fix me*/
++#else
++        present = (sdr_read32(MSDC_PS) & MSDC_PS_CDSTS) ? 0 : 1; 
++        host->card_inserted = present;  
++#endif        
++        spin_unlock_irqrestore(&host->lock, flags);
++    } else {
++        present = 0; /* TODO? Check DAT3 pins for card detection */
++    }
++
++    //printk("ops_get_cd return<%d>\n", present);
++    return present;
++}
++
++/* ops.enable_sdio_irq */
++static void msdc_ops_enable_sdio_irq(struct mmc_host *mmc, int enable)
++{
++    struct msdc_host *host = mmc_priv(mmc);
++    struct msdc_hw *hw = host->hw;
++    u32 base = host->base;
++    u32 tmp;
++
++    if (hw->flags & MSDC_EXT_SDIO_IRQ) { /* yes for sdio */
++        if (enable) {
++            hw->enable_sdio_eirq();  /* combo_sdio_enable_eirq */
++        } else {
++            hw->disable_sdio_eirq(); /* combo_sdio_disable_eirq */
++        }
++    } else { 
++    	  //printk("XXX \n");  /* so never enter here */
++        tmp = sdr_read32(SDC_CFG);
++        /* FIXME. Need to interrupt gap detection */
++        if (enable) {
++            tmp |= (SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);           
++        } else {
++            tmp &= ~(SDC_CFG_SDIOIDE | SDC_CFG_SDIOINTWKUP);
++        }
++        sdr_write32(SDC_CFG, tmp);      
++    }
++}
++
++static struct mmc_host_ops mt_msdc_ops = {
++    .request         = msdc_ops_request,
++    .set_ios         = msdc_ops_set_ios,
++    .get_ro          = msdc_ops_get_ro,
++    .get_cd          = msdc_ops_get_cd,
++    .enable_sdio_irq = msdc_ops_enable_sdio_irq,
++};
++
++/*--------------------------------------------------------------------------*/
++/* interrupt handler                                                    */
++/*--------------------------------------------------------------------------*/
++static irqreturn_t msdc_irq(int irq, void *dev_id)
++{
++    struct msdc_host  *host = (struct msdc_host *)dev_id;
++    struct mmc_data   *data = host->data;
++    struct mmc_command *cmd = host->cmd;
++    u32 base = host->base;
++        
++    u32 cmdsts = MSDC_INT_RSPCRCERR  | MSDC_INT_CMDTMO  | MSDC_INT_CMDRDY  |
++                 MSDC_INT_ACMDCRCERR | MSDC_INT_ACMDTMO | MSDC_INT_ACMDRDY |
++                 MSDC_INT_ACMD19_DONE;                 
++    u32 datsts = MSDC_INT_DATCRCERR  |MSDC_INT_DATTMO;
++
++    u32 intsts = sdr_read32(MSDC_INT);
++    u32 inten  = sdr_read32(MSDC_INTEN); inten &= intsts; 
++
++    sdr_write32(MSDC_INT, intsts);  /* clear interrupts */
++    /* MSG will cause fatal error */
++        
++    /* card change interrupt */
++    if (intsts & MSDC_INT_CDSC){
++        //printk("MSDC_INT_CDSC irq<0x%.8x>\n", intsts); 
++        tasklet_hi_schedule(&host->card_tasklet);
++        /* tuning when plug card ? */
++    }
++    
++    /* sdio interrupt */
++    if (intsts & MSDC_INT_SDIOIRQ){
++        //printk("XXX MSDC_INT_SDIOIRQ\n");  /* seems not sdio irq */
++        //mmc_signal_sdio_irq(host->mmc);
++    }
++
++    /* transfer complete interrupt */
++    if (data != NULL) {
++        if (inten & MSDC_INT_XFER_COMPL) {       	
++            data->bytes_xfered = host->dma.xfersz;
++            complete(&host->xfer_done);           
++        } 
++        
++        if (intsts & datsts) {         
++            /* do basic reset, or stop command will sdc_busy */
++            msdc_reset();
++            msdc_clr_fifo();        
++            msdc_clr_int();             
++            atomic_set(&host->abort, 1);  /* For PIO mode exit */
++            
++            if (intsts & MSDC_INT_DATTMO){
++               	//printk("XXX CMD<%d> MSDC_INT_DATTMO\n", host->mrq->cmd->opcode);
++               	data->error = (unsigned int)-ETIMEDOUT;
++            }
++            else if (intsts & MSDC_INT_DATCRCERR){
++                //printk("XXX CMD<%d> MSDC_INT_DATCRCERR, SDC_DCRC_STS<0x%x>\n", host->mrq->cmd->opcode, sdr_read32(SDC_DCRC_STS));
++                data->error = (unsigned int)-EIO;
++            }
++                                    
++            //if(sdr_read32(MSDC_INTEN) & MSDC_INT_XFER_COMPL) {  
++            if (host->dma_xfer) {
++                complete(&host->xfer_done); /* Read CRC come fast, XFER_COMPL not enabled */
++            } /* PIO mode can't do complete, because not init */
++        }
++    }
++
++    /* command interrupts */
++    if ((cmd != NULL) && (intsts & cmdsts)) {
++        if ((intsts & MSDC_INT_CMDRDY) || (intsts & MSDC_INT_ACMDRDY) || 
++            (intsts & MSDC_INT_ACMD19_DONE)) {
++            u32 *rsp = &cmd->resp[0];
++            
++            switch (host->cmd_rsp) {
++            case RESP_NONE:
++                break;
++            case RESP_R2:
++                *rsp++ = sdr_read32(SDC_RESP3); *rsp++ = sdr_read32(SDC_RESP2);
++                *rsp++ = sdr_read32(SDC_RESP1); *rsp++ = sdr_read32(SDC_RESP0);
++                break;
++            default: /* Response types 1, 3, 4, 5, 6, 7(1b) */
++                if ((intsts & MSDC_INT_ACMDRDY) || (intsts & MSDC_INT_ACMD19_DONE)) {
++                    *rsp = sdr_read32(SDC_ACMD_RESP);
++                } else {
++                    *rsp = sdr_read32(SDC_RESP0);    
++                }
++                break;
++            }
++        } else if ((intsts & MSDC_INT_RSPCRCERR) || (intsts & MSDC_INT_ACMDCRCERR)) {
++            if(intsts & MSDC_INT_ACMDCRCERR){
++                //printk("XXX CMD<%d> MSDC_INT_ACMDCRCERR\n",cmd->opcode);
++            } 
++            else {
++                //printk("XXX CMD<%d> MSDC_INT_RSPCRCERR\n",cmd->opcode);
++            }
++            cmd->error = (unsigned int)-EIO;
++        } else if ((intsts & MSDC_INT_CMDTMO) || (intsts & MSDC_INT_ACMDTMO)) {
++            if(intsts & MSDC_INT_ACMDTMO){
++                //printk("XXX CMD<%d> MSDC_INT_ACMDTMO\n",cmd->opcode);
++            }
++            else {
++                //printk("XXX CMD<%d> MSDC_INT_CMDTMO\n",cmd->opcode);
++            }
++            cmd->error = (unsigned int)-ETIMEDOUT;
++            msdc_reset();
++            msdc_clr_fifo();        
++            msdc_clr_int();            
++        }
++        complete(&host->cmd_done);
++    }
++
++    /* mmc irq interrupts */
++    if (intsts & MSDC_INT_MMCIRQ) {
++        //printk(KERN_INFO "msdc[%d] MMCIRQ: SDC_CSTS=0x%.8x\r\n", host->id, sdr_read32(SDC_CSTS));    
++    }
++    
++#ifdef MT6575_SD_DEBUG
++    {
++        msdc_int_reg *int_reg = (msdc_int_reg*)&intsts;
++        /*printk("IRQ_EVT(0x%x): MMCIRQ(%d) CDSC(%d), ACRDY(%d), ACTMO(%d), ACCRE(%d) AC19DN(%d)\n", 
++            intsts,
++            int_reg->mmcirq,
++            int_reg->cdsc,
++            int_reg->atocmdrdy,
++            int_reg->atocmdtmo,
++            int_reg->atocmdcrc,
++            int_reg->atocmd19done);
++        printk("IRQ_EVT(0x%x): SDIO(%d) CMDRDY(%d), CMDTMO(%d), RSPCRC(%d), CSTA(%d)\n", 
++            intsts,
++            int_reg->sdioirq,
++            int_reg->cmdrdy,
++            int_reg->cmdtmo,
++            int_reg->rspcrc,
++            int_reg->csta);
++        printk("IRQ_EVT(0x%x): XFCMP(%d) DXDONE(%d), DATTMO(%d), DATCRC(%d), DMAEMP(%d)\n", 
++            intsts,
++            int_reg->xfercomp,
++            int_reg->dxferdone,
++            int_reg->dattmo,
++            int_reg->datcrc,
++            int_reg->dmaqempty);*/
++
++    }
++#endif
++    
++    return IRQ_HANDLED;
++}
++
++/*--------------------------------------------------------------------------*/
++/* platform_driver members                                                      */
++/*--------------------------------------------------------------------------*/
++/* called by msdc_drv_probe/remove */
++static void msdc_enable_cd_irq(struct msdc_host *host, int enable)
++{
++	struct msdc_hw *hw = host->hw;
++	u32 base = host->base;
++
++	/* for sdio, not set */
++	if ((hw->flags & MSDC_CD_PIN_EN) == 0) {
++		/* Pull down card detection pin since it is not avaiable */
++		/*
++		   if (hw->config_gpio_pin) 
++		   hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
++		   */
++		sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
++		sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
++		sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
++		return;
++	}
++
++	//printk("CD IRQ Eanable(%d)\n", enable);
++
++	if (enable) {
++	    if (hw->enable_cd_eirq) { /* not set, never enter */
++		    hw->enable_cd_eirq();
++	    } else {
++		    /* card detection circuit relies on the core power so that the core power 
++		     * shouldn't be turned off. Here adds a reference count to keep 
++		     * the core power alive.
++		     */
++		    //msdc_vcore_on(host); //did in msdc_init_hw()
++
++		    if (hw->config_gpio_pin) /* NULL */
++			    hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_UP);
++
++		    sdr_set_field(MSDC_PS, MSDC_PS_CDDEBOUNCE, DEFAULT_DEBOUNCE);
++		    sdr_set_bits(MSDC_PS, MSDC_PS_CDEN);
++		    sdr_set_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
++		    sdr_set_bits(SDC_CFG, SDC_CFG_INSWKUP);  /* not in document! Fix me */
++	    }
++    } else {
++	    if (hw->disable_cd_eirq) {
++		    hw->disable_cd_eirq();
++	    } else {
++		    if (hw->config_gpio_pin) /* NULL */
++			    hw->config_gpio_pin(MSDC_CD_PIN, GPIO_PULL_DOWN);
++
++		    sdr_clr_bits(SDC_CFG, SDC_CFG_INSWKUP);
++		    sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
++		    sdr_clr_bits(MSDC_INTEN, MSDC_INTEN_CDSC);
++
++		    /* Here decreases a reference count to core power since card 
++		     * detection circuit is shutdown.
++		     */
++		    //msdc_vcore_off(host);
++	    }
++    }
++}
++
++/* called by msdc_drv_probe */
++static void msdc_init_hw(struct msdc_host *host)
++{
++    u32 base = host->base;
++    struct msdc_hw *hw = host->hw;
++
++#ifdef MT6575_SD_DEBUG	
++    msdc_reg[host->id] = (struct msdc_regs *)host->base;
++#endif
++
++    /* Power on */
++#if 0 /* --- chhung */
++    msdc_vcore_on(host);
++    msdc_pin_reset(host, MSDC_PIN_PULL_UP);
++    msdc_select_clksrc(host, hw->clk_src);
++    enable_clock(PERI_MSDC0_PDN + host->id, "SD");
++    msdc_vdd_on(host);
++#endif /* end of --- */
++    /* Configure to MMC/SD mode */
++    sdr_set_field(MSDC_CFG, MSDC_CFG_MODE, MSDC_SDMMC); 
++       
++    /* Reset */
++    msdc_reset();
++    msdc_clr_fifo();
++
++    /* Disable card detection */
++    sdr_clr_bits(MSDC_PS, MSDC_PS_CDEN);
++
++    /* Disable and clear all interrupts */
++    sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
++    sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
++    
++#if 1
++	/* reset tuning parameter */
++    sdr_write32(MSDC_PAD_CTL0,   0x00090000);
++    sdr_write32(MSDC_PAD_CTL1,   0x000A0000);
++    sdr_write32(MSDC_PAD_CTL2,   0x000A0000);
++    // sdr_write32(MSDC_PAD_TUNE,   0x00000000);
++    sdr_write32(MSDC_PAD_TUNE,   0x84101010);		// for MT7620 E2 and afterward
++    // sdr_write32(MSDC_DAT_RDDLY0, 0x00000000);
++    sdr_write32(MSDC_DAT_RDDLY0, 0x10101010);		// for MT7620 E2 and afterward
++    sdr_write32(MSDC_DAT_RDDLY1, 0x00000000);
++    sdr_write32(MSDC_IOCON,      0x00000000);
++#if 0 // use MT7620 default value: 0x403c004f
++    sdr_write32(MSDC_PATCH_BIT0, 0x003C000F); /* bit0 modified: Rx Data Clock Source: 1 -> 2.0*/
++#endif
++
++    if (sdr_read32(MSDC_ECO_VER) >= 4) { 
++        if (host->id == 1) {	
++            sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_WRDAT_CRCS, 1); 
++            sdr_set_field(MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMD_RSP,    1);
++            
++            /* internal clock: latch read data */  
++            sdr_set_bits(MSDC_PATCH_BIT0, MSDC_PATCH_BIT_CKGEN_CK);  
++        }       	
++    }   
++#endif    
++
++    /* for safety, should clear SDC_CFG.SDIO_INT_DET_EN & set SDC_CFG.SDIO in 
++       pre-loader,uboot,kernel drivers. and SDC_CFG.SDIO_INT_DET_EN will be only
++       set when kernel driver wants to use SDIO bus interrupt */
++    /* Configure to enable SDIO mode. it's must otherwise sdio cmd5 failed */
++    sdr_set_bits(SDC_CFG, SDC_CFG_SDIO);
++
++    /* disable detect SDIO device interupt function */
++    sdr_clr_bits(SDC_CFG, SDC_CFG_SDIOIDE);
++
++    /* eneable SMT for glitch filter */
++    sdr_set_bits(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKSMT);
++    sdr_set_bits(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDSMT);
++    sdr_set_bits(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATSMT);
++
++#if 1
++    /* set clk, cmd, dat pad driving */
++    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, hw->clk_drv);
++    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, hw->clk_drv);
++    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, hw->cmd_drv);
++    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, hw->cmd_drv);
++    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, hw->dat_drv);
++    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, hw->dat_drv);
++#else 
++    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVN, 0);
++    sdr_set_field(MSDC_PAD_CTL0, MSDC_PAD_CTL0_CLKDRVP, 0);
++    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVN, 0);
++    sdr_set_field(MSDC_PAD_CTL1, MSDC_PAD_CTL1_CMDDRVP, 0);
++    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVN, 0);
++    sdr_set_field(MSDC_PAD_CTL2, MSDC_PAD_CTL2_DATDRVP, 0);
++#endif
++
++    /* set sampling edge */
++
++    /* write crc timeout detection */
++    sdr_set_field(MSDC_PATCH_BIT0, 1 << 30, 1);
++
++    /* Configure to default data timeout */
++    sdr_set_field(SDC_CFG, SDC_CFG_DTOC, DEFAULT_DTOC);
++
++    msdc_set_buswidth(host, MMC_BUS_WIDTH_1);
++
++    //printk("init hardware done!\n");
++}
++
++/* called by msdc_drv_remove */
++static void msdc_deinit_hw(struct msdc_host *host)
++{
++    u32 base = host->base;
++
++    /* Disable and clear all interrupts */
++    sdr_clr_bits(MSDC_INTEN, sdr_read32(MSDC_INTEN));
++    sdr_write32(MSDC_INT, sdr_read32(MSDC_INT));
++
++    /* Disable card detection */
++    msdc_enable_cd_irq(host, 0);
++    // msdc_set_power_mode(host, MMC_POWER_OFF);   /* make sure power down */ /* --- by chhung */
++}
++
++/* init gpd and bd list in msdc_drv_probe */
++static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
++{
++    gpd_t *gpd = dma->gpd; 
++    bd_t  *bd  = dma->bd; 	
++    bd_t  *ptr, *prev;
++    
++    /* we just support one gpd */     
++    int bdlen = MAX_BD_PER_GPD;   	
++
++    /* init the 2 gpd */
++    memset(gpd, 0, sizeof(gpd_t) * 2);
++    //gpd->next = (void *)virt_to_phys(gpd + 1); /* pointer to a null gpd, bug! kmalloc <-> virt_to_phys */  
++    //gpd->next = (dma->gpd_addr + 1);    /* bug */
++    gpd->next = (void *)((u32)dma->gpd_addr + sizeof(gpd_t));    
++
++    //gpd->intr = 0;
++    gpd->bdp  = 1;   /* hwo, cs, bd pointer */      
++    //gpd->ptr  = (void*)virt_to_phys(bd); 
++    gpd->ptr = (void *)dma->bd_addr; /* physical address */
++    
++    memset(bd, 0, sizeof(bd_t) * bdlen);
++    ptr = bd + bdlen - 1;
++    //ptr->eol  = 1;  /* 0 or 1 [Fix me]*/
++    //ptr->next = 0;    
++    
++    while (ptr != bd) {
++        prev = ptr - 1;
++        prev->next = (void *)(dma->bd_addr + sizeof(bd_t) *(ptr - bd));
++        ptr = prev;
++    }
++}
++
++static int msdc_drv_probe(struct platform_device *pdev)
++{
++	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	__iomem void *base;
++    struct mmc_host *mmc;
++    struct resource *mem;
++    struct msdc_host *host;
++    struct msdc_hw *hw;
++    int ret, irq;
++     pdev->dev.platform_data = &msdc0_hw;
++ 
++    /* Allocate MMC host for this device */
++    mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
++    if (!mmc) return -ENOMEM;
++
++    hw   = (struct msdc_hw*)pdev->dev.platform_data;
++    mem  = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    irq  = platform_get_irq(pdev, 0);
++
++    //BUG_ON((!hw) || (!mem) || (irq < 0)); /* --- by chhung */
++    
++	base = devm_request_and_ioremap(&pdev->dev, res);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++/*    mem = request_mem_region(mem->start - 0xa0000000, (mem->end - mem->start + 1) - 0xa0000000, dev_name(&pdev->dev));
++    if (mem == NULL) {
++        mmc_free_host(mmc);
++        return -EBUSY;
++    }
++*/
++    /* Set host parameters to mmc */
++    mmc->ops        = &mt_msdc_ops;
++    mmc->f_min      = HOST_MIN_MCLK;
++    mmc->f_max      = HOST_MAX_MCLK;
++    mmc->ocr_avail  = MSDC_OCR_AVAIL;
++    
++    /* For sd card: MSDC_SYS_SUSPEND | MSDC_WP_PIN_EN | MSDC_CD_PIN_EN | MSDC_REMOVABLE | MSDC_HIGHSPEED, 
++       For sdio   : MSDC_EXT_SDIO_IRQ | MSDC_HIGHSPEED */
++    if (hw->flags & MSDC_HIGHSPEED) {
++        mmc->caps   = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
++    }
++    if (hw->data_pins == 4) { /* current data_pins are all 4*/
++        mmc->caps  |= MMC_CAP_4_BIT_DATA;
++    } else if (hw->data_pins == 8) {
++        mmc->caps  |= MMC_CAP_8_BIT_DATA;
++    }
++    if ((hw->flags & MSDC_SDIO_IRQ) || (hw->flags & MSDC_EXT_SDIO_IRQ))
++        mmc->caps |= MMC_CAP_SDIO_IRQ;  /* yes for sdio */
++
++    /* MMC core transfer sizes tunable parameters */
++  //  mmc->max_hw_segs   = MAX_HW_SGMTS;
++//    mmc->max_phys_segs = MAX_PHY_SGMTS;
++    mmc->max_seg_size  = MAX_SGMT_SZ;
++    mmc->max_blk_size  = HOST_MAX_BLKSZ;
++    mmc->max_req_size  = MAX_REQ_SZ; 
++    mmc->max_blk_count = mmc->max_req_size;
++
++    host = mmc_priv(mmc);
++    host->hw        = hw;
++    host->mmc       = mmc;
++    host->id        = pdev->id;
++    host->error     = 0;
++    host->irq       = irq;    
++    host->base      = (unsigned long) base;
++    host->mclk      = 0;                   /* mclk: the request clock of mmc sub-system */
++    host->hclk      = hclks[hw->clk_src];  /* hclk: clock of clock source to msdc controller */
++    host->sclk      = 0;                   /* sclk: the really clock after divition */
++    host->pm_state  = PMSG_RESUME;
++    host->suspend   = 0;
++    host->core_clkon = 0;
++    host->card_clkon = 0;    
++    host->core_power = 0;
++    host->power_mode = MMC_POWER_OFF;
++//    host->card_inserted = hw->flags & MSDC_REMOVABLE ? 0 : 1;
++    host->timeout_ns = 0;
++    host->timeout_clks = DEFAULT_DTOC * 65536;
++  
++    host->mrq = NULL; 
++    //init_MUTEX(&host->sem); /* we don't need to support multiple threads access */
++   
++    host->dma.used_gpd = 0;
++    host->dma.used_bd = 0;
++
++    /* using dma_alloc_coherent*/  /* todo: using 1, for all 4 slots */
++    host->dma.gpd = dma_alloc_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), &host->dma.gpd_addr, GFP_KERNEL); 
++    host->dma.bd =  dma_alloc_coherent(NULL, MAX_BD_NUM  * sizeof(bd_t),  &host->dma.bd_addr,  GFP_KERNEL); 
++    BUG_ON((!host->dma.gpd) || (!host->dma.bd));    
++    msdc_init_gpd_bd(host, &host->dma);
++    /*for emmc*/
++    msdc_6575_host[pdev->id] = host;
++    
++    tasklet_init(&host->card_tasklet, msdc_tasklet_card, (ulong)host);
++    spin_lock_init(&host->lock);
++    msdc_init_hw(host);
++
++    ret = request_irq((unsigned int)irq, msdc_irq, IRQF_TRIGGER_LOW, dev_name(&pdev->dev), host);
++    if (ret) goto release;
++    // mt65xx_irq_unmask(irq); /* --- by chhung */
++    
++    if (hw->flags & MSDC_CD_PIN_EN) { /* not set for sdio */
++        if (hw->request_cd_eirq) { /* not set for MT6575 */
++            hw->request_cd_eirq(msdc_eirq_cd, (void*)host); /* msdc_eirq_cd will not be used! */
++        }
++    }
++
++    if (hw->request_sdio_eirq) /* set to combo_sdio_request_eirq() for WIFI */
++        hw->request_sdio_eirq(msdc_eirq_sdio, (void*)host); /* msdc_eirq_sdio() will be called when EIRQ */
++
++    if (hw->register_pm) {/* yes for sdio */
++        if(hw->flags & MSDC_SYS_SUSPEND) { /* will not set for WIFI */
++            //printk("MSDC_SYS_SUSPEND and register_pm both set\n");
++        }
++        //mmc->pm_flags |= MMC_PM_IGNORE_PM_NOTIFY; /* pm not controlled by system but by client. */ /* --- by chhung */
++    }
++    
++    platform_set_drvdata(pdev, mmc);
++
++    ret = mmc_add_host(mmc);
++    if (ret) goto free_irq;
++
++    /* Config card detection pin and enable interrupts */
++    if (hw->flags & MSDC_CD_PIN_EN) {  /* set for card */
++        msdc_enable_cd_irq(host, 1);
++    } else {
++        msdc_enable_cd_irq(host, 0);
++    }  
++
++    return 0;
++
++free_irq:
++    free_irq(irq, host);
++release:
++    platform_set_drvdata(pdev, NULL);
++    msdc_deinit_hw(host);
++
++    tasklet_kill(&host->card_tasklet);
++
++/*    if (mem)
++        release_mem_region(mem->start, mem->end - mem->start + 1);
++*/
++    mmc_free_host(mmc);
++
++    return ret;
++}
++
++/* 4 device share one driver, using "drvdata" to show difference */
++static int msdc_drv_remove(struct platform_device *pdev)
++{
++    struct mmc_host *mmc;
++    struct msdc_host *host;
++    struct resource *mem;
++
++
++    mmc  = platform_get_drvdata(pdev);
++    BUG_ON(!mmc);
++    
++    host = mmc_priv(mmc);   
++    BUG_ON(!host);
++
++    //printk("removed !!!\n");
++
++    platform_set_drvdata(pdev, NULL);
++    mmc_remove_host(host->mmc);
++    msdc_deinit_hw(host);
++
++    tasklet_kill(&host->card_tasklet);
++    free_irq(host->irq, host);
++
++    dma_free_coherent(NULL, MAX_GPD_NUM * sizeof(gpd_t), host->dma.gpd, host->dma.gpd_addr);
++    dma_free_coherent(NULL, MAX_BD_NUM  * sizeof(bd_t),  host->dma.bd,  host->dma.bd_addr);
++
++    mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++
++    if (mem)
++        release_mem_region(mem->start, mem->end - mem->start + 1);
++
++    mmc_free_host(host->mmc);
++
++    return 0;
++}
++
++static const struct of_device_id mt7620a_sdhci_match[] = {
++	{ .compatible = "ralink,mt7620a-sdhci" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, rt288x_wdt_match);
++
++/* Fix me: Power Flow */
++static struct platform_driver mt_msdc_driver = {
++    .probe   = msdc_drv_probe,
++    .remove  = msdc_drv_remove,
++    .driver  = {
++        .name  = DRV_NAME,
++        .owner = THIS_MODULE,
++        .of_match_table = mt7620a_sdhci_match,
++
++    },
++};
++
++static int __init mt_msdc_init(void)
++{
++    int ret;
++/* +++ chhung */
++    unsigned int reg;
++
++    mtk_sd_device.dev.platform_data = &msdc0_hw;
++    printk("MTK MSDC device init.\n");
++    reg = sdr_read32((__iomem void *) 0xb0000060) & ~(0x3<<18);
++    reg |= 0x1 << 18;
++    sdr_write32((__iomem void *) 0xb0000060, reg);
++/* end of +++ */
++    ret = platform_driver_register(&mt_msdc_driver);
++    if (ret) {
++        printk(KERN_ERR DRV_NAME ": Can't register driver");
++        return ret;
++    }
++    printk(KERN_INFO DRV_NAME ": MediaTek MT6575 MSDC Driver\n");
++
++    //msdc_debug_proc_init();
++    return 0;
++}
++
++static void __exit mt_msdc_exit(void)
++{
++    platform_driver_unregister(&mt_msdc_driver);
++}
++
++module_init(mt_msdc_init);
++module_exit(mt_msdc_exit);
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("MediaTek MT6575 SD/MMC Card Driver");
++MODULE_AUTHOR("Infinity Chen <infinity.chen@mediatek.com>");
++
++EXPORT_SYMBOL(msdc_6575_host);
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0028-reset-MIPS-ralink-add-core-device-reset-wrapper.patch b/target/linux/ramips/patches-3.10/0028-reset-MIPS-ralink-add-core-device-reset-wrapper.patch
new file mode 100644
index 0000000..beae34e
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0028-reset-MIPS-ralink-add-core-device-reset-wrapper.patch
@@ -0,0 +1,135 @@
+From 0cc20912b376305452cdc5c8e7b97e156ba90e93 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Wed, 8 May 2013 22:08:39 +0200
+Subject: [PATCH 28/33] reset: MIPS: ralink: add core/device reset wrapper
+
+Add a helper for reseting different devices ont he SoC.
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/Kconfig        |    1 +
+ arch/mips/ralink/of.c    |   59 ++++++++++++++++++++++++++++++++++++++++++++++
+ arch/mips/ralink/reset.c |    1 +
+ 3 files changed, 61 insertions(+)
+
+diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
+index 5737c4b..8258e8e 100644
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -444,6 +444,7 @@ config RALINK
+ 	select HAVE_MACH_CLKDEV
+ 	select CLKDEV_LOOKUP
+ 	select ARCH_REQUIRE_GPIOLIB
++	select ARCH_HAS_RESET_CONTROLLER
+ 
+ config SGI_IP22
+ 	bool "SGI IP22 (Indy/Indigo2)"
+diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
+index 8efb02b..2faf478 100644
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -14,16 +14,22 @@
+ #include <linux/sizes.h>
+ #include <linux/of_fdt.h>
+ #include <linux/kernel.h>
++#include <linux/module.h>
+ #include <linux/bootmem.h>
+ #include <linux/of_platform.h>
+ #include <linux/of_address.h>
++#include <linux/reset-controller.h>
+ 
+ #include <asm/reboot.h>
+ #include <asm/bootinfo.h>
+ #include <asm/addrspace.h>
+ 
++#include <asm/mach-ralink/ralink_regs.h>
++
+ #include "common.h"
+ 
++#define SYSC_REG_RESET_CTRL     0x034
++
+ __iomem void *rt_sysc_membase;
+ __iomem void *rt_memc_membase;
+ 
+@@ -96,6 +102,53 @@ void __init plat_mem_setup(void)
+ 				     soc_info.mem_size_max * SZ_1M);
+ }
+ 
++static int ralink_assert_device(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	u32 val;
++
++	if (id < 8)
++		return -1;
++
++	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
++	val |= BIT(id);
++	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
++
++	return 0;
++}
++
++static int ralink_deassert_device(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	u32 val;
++
++	if (id < 8)
++		return -1;
++
++	val = rt_sysc_r32(SYSC_REG_RESET_CTRL);
++	val &= ~BIT(id);
++	rt_sysc_w32(val, SYSC_REG_RESET_CTRL);
++
++	return 0;
++}
++
++static int ralink_reset_device(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	ralink_assert_device(rcdev, id);
++	return ralink_deassert_device(rcdev, id);
++}
++
++static struct reset_control_ops reset_ops = {
++	.reset = ralink_reset_device,
++	.assert = ralink_assert_device,
++	.deassert = ralink_deassert_device,
++};
++
++static struct reset_controller_dev reset_dev = {
++	.ops			= &reset_ops,
++	.owner			= THIS_MODULE,
++	.nr_resets		= 32,
++	.of_reset_n_cells	= 1,
++};
++
+ static int __init plat_of_setup(void)
+ {
+ 	static struct of_device_id of_ids[3];
+@@ -110,6 +163,12 @@ static int __init plat_of_setup(void)
+ 	if (of_platform_populate(NULL, of_ids, NULL, NULL))
+ 		panic("failed to populate DT\n");
+ 
++	reset_dev.of_node = of_find_compatible_node(NULL, NULL, "ralink,rt2880-reset");
++	if (!reset_dev.of_node)
++		panic("Failed to find reset controller node");
++
++	reset_controller_register(&reset_dev);
++
+ 	ralink_pinmux();
+ 
+ 	return 0;
+diff --git a/arch/mips/ralink/reset.c b/arch/mips/ralink/reset.c
+index 22120e5..6c15f4f 100644
+--- a/arch/mips/ralink/reset.c
++++ b/arch/mips/ralink/reset.c
+@@ -10,6 +10,7 @@
+ 
+ #include <linux/pm.h>
+ #include <linux/io.h>
++#include <linux/module.h>
+ 
+ #include <asm/reboot.h>
+ 
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0029-owrt-GPIO-add-gpio_export_with_name.patch b/target/linux/ramips/patches-3.10/0029-owrt-GPIO-add-gpio_export_with_name.patch
new file mode 100644
index 0000000..8789812
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0029-owrt-GPIO-add-gpio_export_with_name.patch
@@ -0,0 +1,338 @@
+From 8f3ed1fffa35d18c2b20ebb866c71a22cc0589ff Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 23 Jun 2013 00:16:22 +0200
+Subject: [PATCH 29/33] owrt: GPIO: add gpio_export_with_name
+
+http://lists.infradead.org/pipermail/linux-arm-kernel/2012-November/133856.html
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ Documentation/devicetree/bindings/gpio/gpio.txt |   60 ++++++++++++++++++++
+ drivers/gpio/gpiolib-of.c                       |   68 +++++++++++++++++++++++
+ drivers/gpio/gpiolib.c                          |   24 +++++---
+ include/asm-generic/gpio.h                      |    6 +-
+ include/linux/gpio.h                            |   26 ++++++++-
+ 5 files changed, 172 insertions(+), 12 deletions(-)
+
+diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
+index d933af3..c264748 100644
+--- a/Documentation/devicetree/bindings/gpio/gpio.txt
++++ b/Documentation/devicetree/bindings/gpio/gpio.txt
+@@ -112,3 +112,63 @@ where,
+ 
+ The pinctrl node must have "#gpio-range-cells" property to show number of
+ arguments to pass with phandle from gpio controllers node.
++
++3) gpio-export
++--------------
++
++gpio-export will allow you to automatically export gpio
++
++required properties:
++- compatible: Should be "gpio-export"
++
++in each child node will reprensent a gpio or if no name is specified
++a list of gpio to export
++
++required properties:
++- gpios: gpio to export
++
++optional properties:
++ - gpio-export,name: export name
++ - gpio-export,output: to set the as output with default value
++ 		       if no present gpio as input
++ - pio-export,direction_may_change: boolean to allow the direction to be controllable
++
++Example:
++
++
++gpio_export {
++	compatible = "gpio-export";
++	#size-cells = <0>;
++
++	in {
++		gpio-export,name = "in";
++		gpios = <&pioC 20 0>;
++	};
++
++	out {
++		gpio-export,name = "out";
++		gpio-export,output = <1>;
++		gpio-export,direction_may_change;
++		gpios = <&pioC 21 0>;
++	};
++
++	in_out {
++		gpio-export,name = "in_out";
++		gpio-export,direction_may_change;
++		gpios = <&pioC 21 0>;
++	};
++
++	gpios_in {
++		gpios = <&pioB 0 0
++			 &pioB 3 0
++			 &pioC 4 0>;
++		gpio-export,direction_may_change;
++	};
++
++	gpios_out {
++		gpios = <&pioB 1 0
++			 &pioB 2 0
++			 &pioC 3 0>;
++		gpio-export,output = <1>;
++	};
++};
+diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
+index 665f953..15ec5e5 100644
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -21,6 +21,8 @@
+ #include <linux/of_gpio.h>
+ #include <linux/pinctrl/pinctrl.h>
+ #include <linux/slab.h>
++#include <linux/init.h>
++#include <linux/platform_device.h>
+ 
+ /* Private data structure for of_gpiochip_find_and_xlate */
+ struct gg_data {
+@@ -242,3 +244,69 @@ void of_gpiochip_remove(struct gpio_chip *chip)
+ 	if (chip->of_node)
+ 		of_node_put(chip->of_node);
+ }
++
++static struct of_device_id gpio_export_ids[] = {
++	{ .compatible = "gpio-export" },
++	{ /* sentinel */ }
++};
++
++static int __init of_gpio_export_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct device_node *cnp;
++	u32 val;
++	int nb = 0;
++
++	for_each_child_of_node(np, cnp) {
++		const char *name = NULL;
++		int gpio;
++		bool dmc;
++		int max_gpio = 1;
++		int i;
++
++		of_property_read_string(cnp, "gpio-export,name", &name);
++
++		if (!name)
++			max_gpio = of_gpio_count(cnp);
++
++		for (i = 0; i < max_gpio; i++) {
++			unsigned flags = 0;
++			enum of_gpio_flags of_flags;
++
++			gpio = of_get_gpio_flags(cnp, i, &of_flags);
++
++			if (of_flags == OF_GPIO_ACTIVE_LOW)
++				flags |= GPIOF_ACTIVE_LOW;
++
++			if (!of_property_read_u32(cnp, "gpio-export,output", &val))
++				flags |= val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
++			else
++				flags |= GPIOF_IN;
++
++			if (devm_gpio_request_one(&pdev->dev, gpio, flags, name ? name : of_node_full_name(np)))
++				continue;
++
++			dmc = of_property_read_bool(cnp, "gpio-export,direction_may_change");
++			gpio_export_with_name(gpio, dmc, name);
++			nb++;
++		}
++	}
++
++	dev_info(&pdev->dev, "%d gpio(s) exported\n", nb);
++
++	return 0;
++}
++
++static struct platform_driver gpio_export_driver = {
++	.driver		= {
++		.name		= "gpio-export",
++		.owner	= THIS_MODULE,
++		.of_match_table	= of_match_ptr(gpio_export_ids),
++	},
++};
++
++static int __init of_gpio_export_init(void)
++{
++	return platform_driver_probe(&gpio_export_driver, of_gpio_export_probe);
++}
++device_initcall(of_gpio_export_init);
+diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
+index c2534d6..8697c82 100644
+--- a/drivers/gpio/gpiolib.c
++++ b/drivers/gpio/gpiolib.c
+@@ -96,7 +96,7 @@ static int gpiod_get_value(const struct gpio_desc *desc);
+ static void gpiod_set_value(struct gpio_desc *desc, int value);
+ static int gpiod_cansleep(const struct gpio_desc *desc);
+ static int gpiod_to_irq(const struct gpio_desc *desc);
+-static int gpiod_export(struct gpio_desc *desc, bool direction_may_change);
++static int gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name);
+ static int gpiod_export_link(struct device *dev, const char *name,
+ 			     struct gpio_desc *desc);
+ static int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value);
+@@ -674,7 +674,7 @@ static ssize_t export_store(struct class *class,
+ 			status = -ENODEV;
+ 		goto done;
+ 	}
+-	status = gpiod_export(desc, true);
++	status = gpiod_export(desc, true, NULL);
+ 	if (status < 0)
+ 		gpiod_free(desc);
+ 	else
+@@ -736,9 +736,10 @@ static struct class gpio_class = {
+ 
+ 
+ /**
+- * gpio_export - export a GPIO through sysfs
++ * gpio_export_with_name - export a GPIO through sysfs
+  * @gpio: gpio to make available, already requested
+  * @direction_may_change: true if userspace may change gpio direction
++ * @name: gpio name
+  * Context: arch_initcall or later
+  *
+  * When drivers want to make a GPIO accessible to userspace after they
+@@ -750,7 +751,7 @@ static struct class gpio_class = {
+  *
+  * Returns zero on success, else an error.
+  */
+-static int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
++static int gpiod_export(struct gpio_desc *desc, bool direction_may_change, const char *name)
+ {
+ 	unsigned long		flags;
+ 	int			status;
+@@ -783,6 +784,8 @@ static int gpiod_export(struct gpio_desc *desc, bool direction_may_change)
+ 		goto fail_unlock;
+ 	}
+ 
++	if (name)
++		ioname = name;
+ 	if (!desc->chip->direction_input || !desc->chip->direction_output)
+ 		direction_may_change = false;
+ 	spin_unlock_irqrestore(&gpio_lock, flags);
+@@ -829,11 +832,11 @@ fail_unlock:
+ 	return status;
+ }
+ 
+-int gpio_export(unsigned gpio, bool direction_may_change)
++int gpio_export_with_name(unsigned gpio, bool direction_may_change, const char *name)
+ {
+-	return gpiod_export(gpio_to_desc(gpio), direction_may_change);
++	return gpiod_export(gpio_to_desc(gpio), direction_may_change, name);
+ }
+-EXPORT_SYMBOL_GPL(gpio_export);
++EXPORT_SYMBOL_GPL(gpio_export_with_name);
+ 
+ static int match_export(struct device *dev, const void *data)
+ {
+@@ -1092,7 +1095,7 @@ static inline void gpiochip_unexport(struct gpio_chip *chip)
+ }
+ 
+ static inline int gpiod_export(struct gpio_desc *desc,
+-			       bool direction_may_change)
++			       bool direction_may_change, const char *name)
+ {
+ 	return -ENOSYS;
+ }
+@@ -1521,6 +1524,9 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
+ 	if (flags & GPIOF_OPEN_SOURCE)
+ 		set_bit(FLAG_OPEN_SOURCE, &desc->flags);
+ 
++	if (flags & GPIOF_ACTIVE_LOW)
++		set_bit(FLAG_ACTIVE_LOW, &gpio_desc[gpio].flags);
++
+ 	if (flags & GPIOF_DIR_IN)
+ 		err = gpiod_direction_input(desc);
+ 	else
+@@ -1531,7 +1537,7 @@ int gpio_request_one(unsigned gpio, unsigned long flags, const char *label)
+ 		goto free_gpio;
+ 
+ 	if (flags & GPIOF_EXPORT) {
+-		err = gpiod_export(desc, flags & GPIOF_EXPORT_CHANGEABLE);
++		err = gpiod_export(desc, flags & GPIOF_EXPORT_CHANGEABLE, NULL);
+ 		if (err)
+ 			goto free_gpio;
+ 	}
+diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
+index bde6469..3290572 100644
+--- a/include/asm-generic/gpio.h
++++ b/include/asm-generic/gpio.h
+@@ -202,7 +202,8 @@ extern void gpio_free_array(const struct gpio *array, size_t num);
+  * A sysfs interface can be exported by individual drivers if they want,
+  * but more typically is configured entirely from userspace.
+  */
+-extern int gpio_export(unsigned gpio, bool direction_may_change);
++extern int gpio_export_with_name(unsigned gpio, bool direction_may_change,
++			const char *name);
+ extern int gpio_export_link(struct device *dev, const char *name,
+ 			unsigned gpio);
+ extern int gpio_sysfs_set_active_low(unsigned gpio, int value);
+@@ -284,7 +285,8 @@ struct device;
+ 
+ /* sysfs support is only available with gpiolib, where it's optional */
+ 
+-static inline int gpio_export(unsigned gpio, bool direction_may_change)
++static inline int gpio_export_with_name(unsigned gpio,
++	bool direction_may_change, const char *name)
+ {
+ 	return -ENOSYS;
+ }
+diff --git a/include/linux/gpio.h b/include/linux/gpio.h
+index 552e3f4..07bbbcc7 100644
+--- a/include/linux/gpio.h
++++ b/include/linux/gpio.h
+@@ -27,6 +27,9 @@
+ #define GPIOF_EXPORT_DIR_FIXED	(GPIOF_EXPORT)
+ #define GPIOF_EXPORT_DIR_CHANGEABLE (GPIOF_EXPORT | GPIOF_EXPORT_CHANGEABLE)
+ 
++#define GPIOF_ACTIVE_LOW	(1 << 6)
++
++
+ /**
+  * struct gpio - a structure describing a GPIO with configuration
+  * @gpio:	the GPIO number
+@@ -169,7 +172,8 @@ static inline void gpio_set_value_cansleep(unsigned gpio, int value)
+ 	WARN_ON(1);
+ }
+ 
+-static inline int gpio_export(unsigned gpio, bool direction_may_change)
++static inline int gpio_export_with_name(unsigned gpio,
++	bool direction_may_change, const char *name)
+ {
+ 	/* GPIO can never have been requested or set as {in,out}put */
+ 	WARN_ON(1);
+@@ -236,4 +240,24 @@ int devm_gpio_request_one(struct device *dev, unsigned gpio,
+ 			  unsigned long flags, const char *label);
+ void devm_gpio_free(struct device *dev, unsigned int gpio);
+ 
++/**
++ * gpio_export - export a GPIO through sysfs
++ * @gpio: gpio to make available, already requested
++ * @direction_may_change: true if userspace may change gpio direction
++ * Context: arch_initcall or later
++ *
++ * When drivers want to make a GPIO accessible to userspace after they
++ * have requested it -- perhaps while debugging, or as part of their
++ * public interface -- they may use this routine.  If the GPIO can
++ * change direction (some can't) and the caller allows it, userspace
++ * will see "direction" sysfs attribute which may be used to change
++ * the gpio's direction.  A "value" attribute will always be provided.
++ *
++ * Returns zero on success, else an error.
++ */
++static inline int gpio_export(unsigned gpio,bool direction_may_change)
++{
++	return gpio_export_with_name(gpio, direction_may_change, NULL);
++}
++
+ #endif /* __LINUX_GPIO_H */
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0030-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch b/target/linux/ramips/patches-3.10/0030-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch
new file mode 100644
index 0000000..6874870
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0030-owrt-MIPS-ralink-add-pseudo-pwm-led-trigger-based-on.patch
@@ -0,0 +1,306 @@
+From daf08289dc0ac69af0d8293dacd5ca6291400593 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Sun, 24 Mar 2013 17:17:17 +0100
+Subject: [PATCH 30/33] owrt: MIPS: ralink: add pseudo pwm led trigger based
+ on timer0
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/ralink/timer.c |  213 ++++++++++++++++++++++++++++++++++++++++++----
+ 1 file changed, 197 insertions(+), 16 deletions(-)
+
+diff --git a/arch/mips/ralink/timer.c b/arch/mips/ralink/timer.c
+index 0a6856c..b156419 100644
+--- a/arch/mips/ralink/timer.c
++++ b/arch/mips/ralink/timer.c
+@@ -12,6 +12,8 @@
+ #include <linux/timer.h>
+ #include <linux/of_gpio.h>
+ #include <linux/clk.h>
++#include <linux/leds.h>
++#include <linux/slab.h>
+ 
+ #include <asm/mach-ralink/ralink_regs.h>
+ 
+@@ -23,16 +25,34 @@
+ 
+ #define TMR0CTL_ENABLE			BIT(7)
+ #define TMR0CTL_MODE_PERIODIC		BIT(4)
+-#define TMR0CTL_PRESCALER		1
++#define TMR0CTL_PRESCALER		2
+ #define TMR0CTL_PRESCALE_VAL		(0xf - TMR0CTL_PRESCALER)
+ #define TMR0CTL_PRESCALE_DIV		(65536 / BIT(TMR0CTL_PRESCALER))
+ 
++struct rt_timer_gpio {
++	struct list_head	list;
++	struct led_classdev	*led;
++};
++
+ struct rt_timer {
+-	struct device	*dev;
+-	void __iomem	*membase;
+-	int		irq;
+-	unsigned long	timer_freq;
+-	unsigned long	timer_div;
++	struct device		*dev;
++	void __iomem		*membase;
++	int			irq;
++
++	unsigned long		timer_freq;
++	unsigned long		timer_div;
++
++	struct list_head	gpios;
++	struct led_trigger	led_trigger;
++	unsigned int		duty_cycle;
++	unsigned int		duty;
++
++	unsigned int		fade;
++	unsigned int		fade_min;
++	unsigned int		fade_max;
++	unsigned int		fade_speed;
++	unsigned int		fade_dir;
++	unsigned int		fade_count;
+ };
+ 
+ static inline void rt_timer_w32(struct rt_timer *rt, u8 reg, u32 val)
+@@ -48,18 +68,46 @@ static inline u32 rt_timer_r32(struct rt_timer *rt, u8 reg)
+ static irqreturn_t rt_timer_irq(int irq, void *_rt)
+ {
+ 	struct rt_timer *rt =  (struct rt_timer *) _rt;
++	struct rt_timer_gpio *gpio;
++	unsigned int val;
+ 
+-	rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
++	if (rt->fade && (rt->fade_count++ > rt->fade_speed)) {
++		rt->fade_count = 0;
++		if (rt->duty_cycle <= rt->fade_min)
++			rt->fade_dir = 1;
++		else if (rt->duty_cycle >= rt->fade_max)
++			rt->fade_dir = 0;
++
++		if (rt->fade_dir)
++			rt->duty_cycle += 1;
++		else
++			rt->duty_cycle -= 1;
++
++	}
++
++	val = rt->timer_freq / rt->timer_div;
++	if (rt->duty)
++		val *= rt->duty_cycle;
++	else
++		val *= (100 - rt->duty_cycle);
++	val /= 100;
++
++	if (!list_empty(&rt->gpios))
++		list_for_each_entry(gpio, &rt->gpios, list)
++			led_set_brightness(gpio->led, !!rt->duty);
++
++	rt->duty = !rt->duty;
++
++	rt_timer_w32(rt, TIMER_REG_TMR0LOAD, val + 1);
+ 	rt_timer_w32(rt, TIMER_REG_TMRSTAT, TMRSTAT_TMR0INT);
+ 
+ 	return IRQ_HANDLED;
+ }
+ 
+-
+ static int rt_timer_request(struct rt_timer *rt)
+ {
+-	int err = request_irq(rt->irq, rt_timer_irq, IRQF_DISABLED,
+-						dev_name(rt->dev), rt);
++	int err = devm_request_irq(rt->dev, rt->irq, rt_timer_irq,
++					IRQF_DISABLED, dev_name(rt->dev), rt);
+ 	if (err) {
+ 		dev_err(rt->dev, "failed to request irq\n");
+ 	} else {
+@@ -81,8 +129,6 @@ static int rt_timer_config(struct rt_timer *rt, unsigned long divisor)
+ 	else
+ 		rt->timer_div = divisor;
+ 
+-	rt_timer_w32(rt, TIMER_REG_TMR0LOAD, rt->timer_freq / rt->timer_div);
+-
+ 	return 0;
+ }
+ 
+@@ -108,11 +154,128 @@ static void rt_timer_disable(struct rt_timer *rt)
+ 	rt_timer_w32(rt, TIMER_REG_TMR0CTL, t);
+ }
+ 
++static ssize_t led_fade_show(struct device *dev,
++				struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++
++	return sprintf(buf, "speed: %d, min: %d, max: %d\n", rt->fade_speed, rt->fade_min, rt->fade_max);
++}
++
++static ssize_t led_fade_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t size)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++	unsigned int speed = 0, min = 0, max = 0;
++	ssize_t ret = -EINVAL;
++
++	ret = sscanf(buf, "%u %u %u", &speed, &min, &max);
++
++	if (ret == 3) {
++		rt->fade_speed = speed;
++		rt->fade_min = min;
++		rt->fade_max = max;
++		rt->fade = 1;
++	} else {
++		rt->fade = 0;
++	}
++
++	return size;
++}
++
++static DEVICE_ATTR(fade, 0644, led_fade_show, led_fade_store);
++
++static ssize_t led_duty_cycle_show(struct device *dev,
++				struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++
++	return sprintf(buf, "%u\n", rt->duty_cycle);
++}
++
++static ssize_t led_duty_cycle_store(struct device *dev,
++		struct device_attribute *attr, const char *buf, size_t size)
++{
++	struct led_classdev *led_cdev = dev_get_drvdata(dev);
++	struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++	unsigned long state;
++	ssize_t ret = -EINVAL;
++
++	ret = kstrtoul(buf, 10, &state);
++	if (ret)
++		return ret;
++
++	if (state <= 100)
++		rt->duty_cycle = state;
++	else
++		rt->duty_cycle = 100;
++
++	rt->fade = 0;
++
++	return size;
++}
++
++static DEVICE_ATTR(duty_cycle, 0644, led_duty_cycle_show, led_duty_cycle_store);
++
++static void rt_timer_trig_activate(struct led_classdev *led_cdev)
++{
++	struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++	struct rt_timer_gpio *gpio_data;
++	int rc;
++
++	led_cdev->trigger_data = NULL;
++	gpio_data = kzalloc(sizeof(*gpio_data), GFP_KERNEL);
++	if (!gpio_data)
++		return;
++
++	rc = device_create_file(led_cdev->dev, &dev_attr_duty_cycle);
++	if (rc)
++		goto err_gpio;
++	rc = device_create_file(led_cdev->dev, &dev_attr_fade);
++	if (rc)
++		goto err_out_duty_cycle;
++
++	led_cdev->activated = true;
++	led_cdev->trigger_data = gpio_data;
++	gpio_data->led = led_cdev;
++	list_add(&gpio_data->list, &rt->gpios);
++	led_cdev->trigger_data = gpio_data;
++	rt_timer_enable(rt);
++	return;
++
++err_out_duty_cycle:
++	device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
++
++err_gpio:
++	kfree(gpio_data);
++}
++
++static void rt_timer_trig_deactivate(struct led_classdev *led_cdev)
++{
++	struct rt_timer *rt = container_of(led_cdev->trigger, struct rt_timer, led_trigger);
++	struct rt_timer_gpio *gpio_data = (struct rt_timer_gpio*) led_cdev->trigger_data;
++
++	if (led_cdev->activated) {
++		device_remove_file(led_cdev->dev, &dev_attr_duty_cycle);
++		device_remove_file(led_cdev->dev, &dev_attr_fade);
++		led_cdev->activated = false;
++	}
++
++	list_del(&gpio_data->list);
++	rt_timer_disable(rt);
++	led_set_brightness(led_cdev, LED_OFF);
++}
++
+ static int rt_timer_probe(struct platform_device *pdev)
+ {
+ 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	const __be32 *divisor;
+ 	struct rt_timer *rt;
+ 	struct clk *clk;
++	int ret;
+ 
+ 	if (!res) {
+ 		dev_err(&pdev->dev, "no memory resource found\n");
+@@ -147,12 +310,29 @@ static int rt_timer_probe(struct platform_device *pdev)
+ 	if (!rt->timer_freq)
+ 		return -EINVAL;
+ 
++	rt->duty_cycle = 100;
+ 	rt->dev = &pdev->dev;
+ 	platform_set_drvdata(pdev, rt);
+ 
+-	rt_timer_request(rt);
+-	rt_timer_config(rt, 2);
+-	rt_timer_enable(rt);
++	ret = rt_timer_request(rt);
++	if (ret)
++		return ret;
++
++	divisor = of_get_property(pdev->dev.of_node, "ralink,divisor", NULL);
++	if (divisor)
++		rt_timer_config(rt, be32_to_cpu(*divisor));
++	else
++		rt_timer_config(rt, 200);
++
++	rt->led_trigger.name = "pwmtimer",
++	rt->led_trigger.activate = rt_timer_trig_activate,
++	rt->led_trigger.deactivate = rt_timer_trig_deactivate,
++
++	ret = led_trigger_register(&rt->led_trigger);
++	if (ret)
++		return ret;
++
++	INIT_LIST_HEAD(&rt->gpios);
+ 
+ 	dev_info(&pdev->dev, "maximum frequncy is %luHz\n", rt->timer_freq);
+ 
+@@ -163,6 +343,7 @@ static int rt_timer_remove(struct platform_device *pdev)
+ {
+ 	struct rt_timer *rt = platform_get_drvdata(pdev);
+ 
++	led_trigger_unregister(&rt->led_trigger);
+ 	rt_timer_disable(rt);
+ 	rt_timer_free(rt);
+ 
+@@ -187,6 +368,6 @@ static struct platform_driver rt_timer_driver = {
+ 
+ module_platform_driver(rt_timer_driver);
+ 
+-MODULE_DESCRIPTION("Ralink RT2880 timer");
++MODULE_DESCRIPTION("Ralink RT2880 timer / pseudo pwm");
+ MODULE_AUTHOR("John Crispin <blogic@openwrt.org");
+ MODULE_LICENSE("GPL");
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0031-owrt-MIPS-add-OWRTDTB-secion.patch b/target/linux/ramips/patches-3.10/0031-owrt-MIPS-add-OWRTDTB-secion.patch
new file mode 100644
index 0000000..77606cf
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0031-owrt-MIPS-add-OWRTDTB-secion.patch
@@ -0,0 +1,61 @@
+From c174d2250e402399ad7dbdd57d51883d8804bba0 Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:40:37 +0200
+Subject: [PATCH 31/33] owrt: MIPS: add OWRTDTB secion
+
+Signed-off-by: John Crispin <blogic@openwrt.org>
+---
+ arch/mips/kernel/head.S   |    3 +++
+ arch/mips/ralink/Makefile |    2 +-
+ arch/mips/ralink/of.c     |    4 +++-
+ 3 files changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
+index c61cdae..b4e55bb 100644
+--- a/arch/mips/kernel/head.S
++++ b/arch/mips/kernel/head.S
+@@ -140,6 +140,9 @@ FEXPORT(__kernel_entry)
+ 	j	kernel_entry
+ #endif
+ 
++	.ascii  "OWRTDTB:"
++	EXPORT(__image_dtb)
++	.fill   0x4000
+ 	__REF
+ 
+ NESTED(kernel_entry, 16, sp)			# kernel entry point
+diff --git a/arch/mips/ralink/Makefile b/arch/mips/ralink/Makefile
+index 03af636..9b32626 100644
+--- a/arch/mips/ralink/Makefile
++++ b/arch/mips/ralink/Makefile
+@@ -19,4 +19,4 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+ 
+ obj-$(CONFIG_DEBUG_FS) += bootrom.o
+ 
+-obj-y += dts/
++#obj-y += dts/
+diff --git a/arch/mips/ralink/of.c b/arch/mips/ralink/of.c
+index 2faf478..d87222f 100644
+--- a/arch/mips/ralink/of.c
++++ b/arch/mips/ralink/of.c
+@@ -83,6 +83,8 @@ void __init device_tree_init(void)
+ 	//free_bootmem(base, size);
+ }
+ 
++extern struct boot_param_header __image_dtb;
++
+ void __init plat_mem_setup(void)
+ {
+ 	set_io_port_base(KSEG1);
+@@ -91,7 +93,7 @@ void __init plat_mem_setup(void)
+ 	 * Load the builtin devicetree. This causes the chosen node to be
+ 	 * parsed resulting in our memory appearing
+ 	 */
+-	__dt_setup_arch(&__dtb_start);
++	__dt_setup_arch(&__image_dtb);
+ 
+ 	if (soc_info.mem_size)
+ 		add_memory_region(soc_info.mem_base, soc_info.mem_size * SZ_1M,
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0032-mtd-fix-cfi-cmdset-0002-erase-status-check.patch b/target/linux/ramips/patches-3.10/0032-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
new file mode 100644
index 0000000..e3797eb
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0032-mtd-fix-cfi-cmdset-0002-erase-status-check.patch
@@ -0,0 +1,34 @@
+From 413b2ed67d8e4dc1242edb9286ea3f634d10a6ba Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:38:51 +0200
+Subject: [PATCH 32/33] mtd: fix cfi cmdset 0002 erase status check
+
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c |    4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
+index fff665d..ab8eb03 100644
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -1956,7 +1956,7 @@ static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr))
++		if (chip_good(map, adr, map_word_ff(map)))
+ 			break;
+ 
+ 		if (time_after(jiffies, timeo)) {
+@@ -2045,7 +2045,7 @@ static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip,
+ 			chip->erase_suspended = 0;
+ 		}
+ 
+-		if (chip_ready(map, adr)) {
++		if (chip_good(map, adr, map_word_ff(map))) {
+ 			xip_enable(map, chip, adr);
+ 			break;
+ 		}
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0033-mtd-cfi-cmdset-0002-force-word-write.patch b/target/linux/ramips/patches-3.10/0033-mtd-cfi-cmdset-0002-force-word-write.patch
new file mode 100644
index 0000000..62fc1cd
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0033-mtd-cfi-cmdset-0002-force-word-write.patch
@@ -0,0 +1,75 @@
+From d5b094ea6d435817d295d554d652a97a5014c64f Mon Sep 17 00:00:00 2001
+From: John Crispin <blogic@openwrt.org>
+Date: Mon, 15 Jul 2013 00:39:21 +0200
+Subject: [PATCH 33/33] mtd: cfi cmdset 0002 force word write
+
+---
+ drivers/mtd/chips/cfi_cmdset_0002.c |    9 +++++++--
+ 1 file changed, 7 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mtd/chips/cfi_cmdset_0002.c b/drivers/mtd/chips/cfi_cmdset_0002.c
+index ab8eb03..d84668d 100644
+--- a/drivers/mtd/chips/cfi_cmdset_0002.c
++++ b/drivers/mtd/chips/cfi_cmdset_0002.c
+@@ -41,7 +41,7 @@
+ #include <linux/mtd/xip.h>
+ 
+ #define AMD_BOOTLOC_BUG
+-#define FORCE_WORD_WRITE 0
++#define FORCE_WORD_WRITE 1
+ 
+ #define MAX_WORD_RETRIES 3
+ 
+@@ -52,7 +52,9 @@
+ 
+ static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
+ static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#if !FORCE_WORD_WRITE
+ static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
++#endif
+ static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
+ static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
+ static void cfi_amdstd_sync (struct mtd_info *);
+@@ -192,6 +194,7 @@ static void fixup_amd_bootblock(struct mtd_info *mtd)
+ }
+ #endif
+ 
++#if !FORCE_WORD_WRITE
+ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ {
+ 	struct map_info *map = mtd->priv;
+@@ -201,6 +204,7 @@ static void fixup_use_write_buffers(struct mtd_info *mtd)
+ 		mtd->_write = cfi_amdstd_write_buffers;
+ 	}
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /* Atmel chips don't use the same PRI format as AMD chips */
+ static void fixup_convert_atmel_pri(struct mtd_info *mtd)
+@@ -1461,6 +1465,7 @@ static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
+ /*
+  * FIXME: interleaved mode not tested, and probably not supported!
+  */
++#if !FORCE_WORD_WRITE
+ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 				    unsigned long adr, const u_char *buf,
+ 				    int len)
+@@ -1584,7 +1589,6 @@ static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
+ 	return ret;
+ }
+ 
+-
+ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+ 				    size_t *retlen, const u_char *buf)
+ {
+@@ -1659,6 +1663,7 @@ static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
+ 
+ 	return 0;
+ }
++#endif /* !FORCE_WORD_WRITE */
+ 
+ /*
+  * Wait for the flash chip to become ready to write data
+-- 
+1.7.10.4
+
diff --git a/target/linux/ramips/patches-3.10/0034-mtd-split-remove-padding.patch b/target/linux/ramips/patches-3.10/0034-mtd-split-remove-padding.patch
new file mode 100644
index 0000000..b08fb1d
--- /dev/null
+++ b/target/linux/ramips/patches-3.10/0034-mtd-split-remove-padding.patch
@@ -0,0 +1,15 @@
+Index: linux-3.10.1/drivers/mtd/mtdpart.c
+===================================================================
+--- linux-3.10.1.orig/drivers/mtd/mtdpart.c	2013-07-15 11:39:25.376669514 +0200
++++ linux-3.10.1/drivers/mtd/mtdpart.c	2013-07-15 11:49:53.040684471 +0200
+@@ -807,10 +807,6 @@
+ 		return;
+ 
+ 	len = be32_to_cpu(hdr.size) + 0x40;
+-	len = mtd_pad_erasesize(master, part->offset, len);
+-	if (len + master->erasesize > part->mtd.size)
+-		return;
+-
+ 	__mtd_add_partition(master, "rootfs", part->offset + len,
+ 			    part->mtd.size - len, false);
+ }