ralink: make pci driver handle mt7628

Signed-off-by: John Crispin <blogic@openwrt.org>

SVN-Revision: 43198

1 files changed, 138 insertions, 90 deletions

diff --git a/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch b/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
index d1dec60..9946c1a 100644
--- a/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
+++ b/target/linux/ramips/patches-3.14/0032-PCI-MIPS-adds-mt7620a-pcie-driver.patch
@@ -23,7 +23,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  obj-$(CONFIG_TANBAC_TB0219)	+= fixup-tb0219.o
 --- /dev/null
 +++ b/arch/mips/pci/pci-mt7620a.c
-@@ -0,0 +1,363 @@
+@@ -0,0 +1,401 @@
 +/*
 + *  Ralink MT7620A SoC PCI support
 + *
@@ -49,12 +49,12 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#include <linux/platform_device.h>
 +
 +#include <asm/mach-ralink/ralink_regs.h>
++#include <asm/mach-ralink/mt7620.h>
 +
 +#define RALINK_PCI_MM_MAP_BASE		0x20000000
 +#define RALINK_PCI_IO_MAP_BASE		0x10160000
 +
 +#define RALINK_INT_PCIE0		4
-+#define RALINK_SYSTEM_CONTROL_BASE	0xb0000000
 +#define RALINK_SYSCFG1			0x14
 +#define RALINK_CLKCFG1			0x30
 +#define RALINK_GPIOMODE			0x60
@@ -63,19 +63,11 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define PCIEPHY0_CFG			0x90
 +#define PPLL_CFG1			0x9c
 +#define PPLL_DRV			0xa0
-+#define RALINK_PCI_HOST_MODE_EN		(1<<7)
-+#define RALINK_PCIE_RC_MODE_EN		(1<<8)
-+#define RALINK_PCIE_RST			(1<<23)
-+#define RALINK_PCI_RST			(1<<24)
-+#define RALINK_PCI_CLK_EN		(1<<19)
-+#define RALINK_PCIE_CLK_EN		(1<<21)
-+#define PCI_SLOTx2			(1<<11)
-+#define PCI_SLOTx1			(2<<11)
 +#define PDRV_SW_SET			(1<<31)
 +#define LC_CKDRVPD_			(1<<19)
 +
 +#define RALINK_PCI_CONFIG_ADDR		0x20
-+#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
++#define RALINK_PCI_CONFIG_DATA_VIRT_REG	0x24
 +#define MEMORY_BASE			0x0
 +#define RALINK_PCIE0_RST		(1<<26)
 +#define RALINK_PCI_BASE			0xB0140000
@@ -93,6 +85,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define RALINK_PCI0_STATUS		0x50
 +#define RALINK_PCI_PCIMSK_ADDR		0x0C
 +
++#define RALINK_PCIEPHY_P0_CTL_OFFSET	0x7498
 +#define RALINK_PCIE0_CLK_EN		(1 << 26)
 +
 +#define BUSY				0x80000000
@@ -101,7 +94,6 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +#define DATA_SHIFT			0
 +#define ADDR_SHIFT			8
 +
-+
 +static void __iomem *bridge_base;
 +static void __iomem *pcie_base;
 +
@@ -130,17 +122,17 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
 +{
 +	u32 val = pcie_r32(reg);
++
 +	val &= ~clr;
 +	val |= set;
 +	pcie_w32(val, reg);
 +}
 +
-+int wait_pciephy_busy(void)
++static int wait_pciephy_busy(void)
 +{
 +	unsigned long reg_value = 0x0, retry = 0;
 +
 +	while (1) {
-+		//reg_value = rareg(READMODE, PCIEPHY0_CFG, 0);
 +		reg_value = pcie_r32(PCIEPHY0_CFG);
 +
 +		if (reg_value & BUSY)
@@ -169,10 +161,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	u8 func = PCI_FUNC(devfn);
 +	u32 address;
 +	u32 data;
++	u32 num = 0;
++
++	if (bus)
++		num = bus->number;
 +
-+	address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 +	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
++	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 +
 +	switch (size) {
 +	case 1:
@@ -195,10 +191,14 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	u8 func = PCI_FUNC(devfn);
 +	u32 address;
 +	u32 data;
++	u32 num = 0;
 +
-+	address = (((where & 0xF00) >> 8) << 24) | (bus->number << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
++	if (bus)
++		num = bus->number;
++
++	address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) | (func << 8) | (where & 0xfc) | 0x80000000;
 +	bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
-+	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
++	data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
 +
 +	switch (size) {
 +	case 1:
@@ -214,69 +214,39 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +		break;
 +	}
 +
-+	bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
++	bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
 +
 +	return PCIBIOS_SUCCESSFUL;
 +}
 +
-+struct pci_ops mt7620a_pci_ops= {
++struct pci_ops mt7620_pci_ops= {
 +	.read	= pci_config_read,
 +	.write	= pci_config_write,
 +};
 +
-+static struct resource mt7620a_res_pci_mem1 = {
-+	.name	= "pci memory",
-+	.start	= RALINK_PCI_MM_MAP_BASE,
-+	.end	= (u32) ((RALINK_PCI_MM_MAP_BASE + (unsigned char *)0x0fffffff)),
-+	.flags	= IORESOURCE_MEM,
-+};
-+static struct resource mt7620a_res_pci_io1 = {
-+	.name	= "pci io",
-+	.start	= RALINK_PCI_IO_MAP_BASE,
-+	.end	= (u32) ((RALINK_PCI_IO_MAP_BASE + (unsigned char *)0x0ffff)),
-+	.flags	= IORESOURCE_IO,
-+};
-+
-+struct pci_controller mt7620a_controller = {
-+	.pci_ops	= &mt7620a_pci_ops,
-+	.mem_resource	= &mt7620a_res_pci_mem1,
-+	.io_resource	= &mt7620a_res_pci_io1,
++static struct resource mt7620_res_pci_mem1;
++static struct resource mt7620_res_pci_io1;
++struct pci_controller mt7620_controller = {
++	.pci_ops	= &mt7620_pci_ops,
++	.mem_resource	= &mt7620_res_pci_mem1,
 +	.mem_offset	= 0x00000000UL,
++	.io_resource	= &mt7620_res_pci_io1,
 +	.io_offset	= 0x00000000UL,
 +	.io_map_base	= 0xa0000000,
 +};
 +
-+static int mt7620a_pci_probe(struct platform_device *pdev)
-+{
-+	struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+	struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+
-+	rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
-+	if (IS_ERR(rstpcie0))
-+		return PTR_ERR(rstpcie0);
-+
-+	bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
-+        if (!bridge_base)
-+		return -ENOMEM;
-+
-+	pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
-+        if (!pcie_base)
-+		return -ENOMEM;
-+
-+	iomem_resource.start = 0;
-+	iomem_resource.end= ~0;
-+	ioport_resource.start= 0;
-+	ioport_resource.end = ~0;
-+
++static int mt7620_pci_hw_init(struct platform_device *pdev) {
 +	/* PCIE: bypass PCIe DLL */
 +	pcie_phy(0x0, 0x80);
 +	pcie_phy(0x1, 0x04);
++
 +	/* PCIE: Elastic buffer control */
 +	pcie_phy(0x68, 0xB4);
 +
 +	reset_control_assert(rstpcie0);
++
 +	rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+	rt_sysc_m32(1<<19, 1<<31, PPLL_DRV);
++	rt_sysc_m32(BIT(19), BIT(31), PPLL_DRV);
 +	rt_sysc_m32(0x3 << 16, 0, RALINK_GPIOMODE);
 +
 +	reset_control_deassert(rstpcie0);
@@ -284,13 +254,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +
 +	mdelay(100);
 +
-+	if (!(rt_sysc_r32(PPLL_CFG1) & 1<<23)) {
-+		printk("MT7620 PPLL unlock\n");
++	if (!(rt_sysc_r32(PPLL_CFG1) & BIT(23))) {
++		dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
 +		reset_control_assert(rstpcie0);
-+		rt_sysc_m32(BIT(26), 0, RALINK_CLKCFG1);
-+		return 0;
++		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
++		return -1;
 +	}
-+	rt_sysc_m32((0x1<<18) | (0x1<<17), (0x1 << 19) | (0x1 << 31), PPLL_DRV);
++	rt_sysc_m32(BIT(18) | BIT(17), BIT(19) | BIT(31), PPLL_DRV);
 +
 +	mdelay(100);
 +	reset_control_assert(rstpcie0);
@@ -299,39 +269,111 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	rt_sysc_m32(~0x7fffffff, 0x80000000, RALINK_PCIE_CLK_GEN);
 +	rt_sysc_m32(~0x80ffffff, 0xa << 24, RALINK_PCIE_CLK_GEN1);
 +
-+	mdelay(50);
++	return 0;
++}
++
++static int mt7628_pci_hw_init(struct platform_device *pdev) {
++	u32 val = 0;
++
++	rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
 +	reset_control_deassert(rstpcie0);
++	rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
++	mdelay(100);
++
++	pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
++
++	pci_config_read(NULL, 0, 0x70c, 4, &val);
++	val &= ~(0xff) << 8;
++	val |= 0x50 << 8;
++	pci_config_write(NULL, 0, 0x70c, 4, val);
++
++	pci_config_read(NULL, 0, 0x70c, 4, &val);
++	dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
++
++	return 0;
++}
++
++static int mt7620_pci_probe(struct platform_device *pdev)
++{
++	struct resource *bridge_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	struct resource *pcie_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++	u32 val = 0;
++
++	rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
++	if (IS_ERR(rstpcie0))
++		return PTR_ERR(rstpcie0);
++
++	bridge_base = devm_request_and_ioremap(&pdev->dev, bridge_res);
++        if (!bridge_base)
++		return -ENOMEM;
++
++	pcie_base = devm_request_and_ioremap(&pdev->dev, pcie_res);
++        if (!pcie_base)
++		return -ENOMEM;
++
++	iomem_resource.start = 0;
++	iomem_resource.end = ~0;
++	ioport_resource.start = 0;
++	ioport_resource.end = ~0;
++
++	/* bring up the pci core */
++	switch (mt762x_soc) {
++	case MT762X_SOC_MT7620A:
++		if (mt7620_pci_hw_init(pdev))
++			return -1;
++		break;
++
++	case MT762X_SOC_MT7628AN:
++		if (mt7628_pci_hw_init(pdev))
++			return -1;
++		break;
++
++	default:
++		dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
++		return -1;
++	}
++	mdelay(50);
++
++	/* enable write access */
 +	pcie_m32(BIT(1), 0, RALINK_PCI_PCICFG_ADDR);
 +	mdelay(100);
 +
-+	if (( pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
++	/* check if there is a card present */
++	if ((pcie_r32(RALINK_PCI0_STATUS) & 0x1) == 0) {
 +		reset_control_assert(rstpcie0);
 +		rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-+		rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
-+		printk("PCIE0 no card, disable it(RST&CLK)\n");
++		if (mt762x_soc == MT762X_SOC_MT7620A)
++			rt_sysc_m32(LC_CKDRVPD_, PDRV_SW_SET, PPLL_DRV);
++		dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
++		return -1;
 +	}
 +
++	/* setup ranges */
 +	bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
 +	bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
 +
-+	pcie_w32(0x7FFF0000, RALINK_PCI0_BAR0SETUP_ADDR);
++	pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
 +	pcie_w32(MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
-+	pcie_w32(0x08021814, RALINK_PCI0_ID);
 +	pcie_w32(0x06040001, RALINK_PCI0_CLASS);
-+	pcie_w32(0x28801814, RALINK_PCI0_SUBID);
++
++	/* enable interrupts */
 +	pcie_m32(0, BIT(20), RALINK_PCI_PCIMSK_ADDR);
 +
-+	register_pci_controller(&mt7620a_controller);
++	/* voodoo from the SDK driver */
++	pci_config_read(NULL, 0, 4, 4, &val);
++	pci_config_write(NULL, 0, 4, 4, val | 0x7);
++
++	pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
++	register_pci_controller(&mt7620_controller);
 +
 +	return 0;
 +}
 +
 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 +{
-+	const struct resource *res;
 +	u16 cmd;
 +	u32 val;
-+	int i, irq = 0;
++	int irq = 0;
 +
 +	if ((dev->bus->number == 0) && (slot == 0)) {
 +		pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR); //open 7FFF:2G; ENABLE
@@ -340,14 +382,10 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	} else if ((dev->bus->number == 1) && (slot == 0x0)) {
 +		irq = RALINK_INT_PCIE0;
 +	} else {
-+		printk("bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
++		dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n", dev->bus->number, slot);
 +		return 0;
 +	}
 +
-+	for (i = 0; i < 6; i++) {
-+		res = &dev->resource[i];
-+	}
-+
 +	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);  //configure cache line size 0x14
 +	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF);  //configure latency timer 0x10
 +	pci_read_config_word(dev, PCI_COMMAND, &cmd);
@@ -366,27 +404,27 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return 0;
 +}
 +
-+static const struct of_device_id mt7620a_pci_ids[] = {
-+	{ .compatible = "ralink,mt7620a-pci" },
++static const struct of_device_id mt7620_pci_ids[] = {
++	{ .compatible = "mediatek,mt7620-pci" },
 +	{},
 +};
-+MODULE_DEVICE_TABLE(of, mt7620a_pci_ids);
++MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
 +
-+static struct platform_driver mt7620a_pci_driver = {
-+	.probe = mt7620a_pci_probe,
++static struct platform_driver mt7620_pci_driver = {
++	.probe = mt7620_pci_probe,
 +	.driver = {
-+		.name = "mt7620a-pci",
++		.name = "mt7620-pci",
 +		.owner = THIS_MODULE,
-+		.of_match_table = of_match_ptr(mt7620a_pci_ids),
++		.of_match_table = of_match_ptr(mt7620_pci_ids),
 +	},
 +};
 +
-+static int __init mt7620a_pci_init(void)
++static int __init mt7620_pci_init(void)
 +{
-+	return platform_driver_register(&mt7620a_pci_driver);
++	return platform_driver_register(&mt7620_pci_driver);
 +}
 +
-+arch_initcall(mt7620a_pci_init);
++arch_initcall(mt7620_pci_init);
 --- a/arch/mips/ralink/Kconfig
 +++ b/arch/mips/ralink/Kconfig
 @@ -39,6 +39,7 @@ choice
@@ -397,3 +435,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	config SOC_MT7621
  		bool "MT7621"
+--- a/arch/mips/include/asm/mach-ralink/mt7620.h
++++ b/arch/mips/include/asm/mach-ralink/mt7620.h
+@@ -19,6 +19,7 @@ enum mt762x_soc_type {
+ 	MT762X_SOC_MT7620N,
+ 	MT762X_SOC_MT7628AN,
+ };
++extern enum mt762x_soc_type mt762x_soc;
+ 
+ #define MT7620_SYSC_BASE		0x10000000
+