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| author | Hauke Mehrtens <hauke@hauke-m.de> | 2017-04-02 11:53:42 +0200 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-04-02 14:37:49 +0200 |
| commit | 0dcc4d239da78bc20b091d50c097c386e0e61902 (patch) | |
| tree | 47a71ebb1271cb26429c20e34dcad1f8e3d5e945 /target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch | |
| parent | 1adc6db0362d2fdede68a3f1f3a5f119ca39d30a (diff) | |
| download | mtk-20170518-0dcc4d239da78bc20b091d50c097c386e0e61902.zip mtk-20170518-0dcc4d239da78bc20b091d50c097c386e0e61902.tar.gz mtk-20170518-0dcc4d239da78bc20b091d50c097c386e0e61902.tar.bz2 | |
kernel: update kernel 4.4 to 4.4.59
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch')
| -rw-r--r-- | target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch b/target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch index 56bca78..a3f2677 100644 --- a/target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch +++ b/target/linux/ramips/patches-4.4/0010-MIPS-ralink-Add-a-few-missing-clocks.patch @@ -28,7 +28,7 @@ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> if (IS_ENABLED(CONFIG_USB) && is_mt76x8()) { --- a/arch/mips/ralink/rt305x.c +++ b/arch/mips/ralink/rt305x.c -@@ -201,6 +201,7 @@ void __init ralink_clk_init(void) +@@ -190,6 +190,7 @@ void __init ralink_clk_init(void) ralink_clk_add("cpu", cpu_rate); ralink_clk_add("sys", sys_rate); ralink_clk_add("10000b00.spi", sys_rate); @@ -38,7 +38,7 @@ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> ralink_clk_add("10000500.uart", uart_rate); --- a/arch/mips/ralink/rt3883.c +++ b/arch/mips/ralink/rt3883.c -@@ -109,6 +109,7 @@ void __init ralink_clk_init(void) +@@ -99,6 +99,7 @@ void __init ralink_clk_init(void) ralink_clk_add("10000120.watchdog", sys_rate); ralink_clk_add("10000500.uart", 40000000); ralink_clk_add("10000b00.spi", sys_rate); |