diff options
| author | Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk> | 2017-05-15 15:03:47 +0100 |
|---|---|---|
| committer | Hauke Mehrtens <hauke@hauke-m.de> | 2017-05-21 21:48:16 +0200 |
| commit | 088e28772c504ad622ba909b0f6d2986910e7a97 (patch) | |
| tree | 9bb961a4819da65df64f0088780395fa5ccf2426 /target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch | |
| parent | 0a05fbd1356631a1f903adcd63ffb05550537667 (diff) | |
| download | mtk-20170518-088e28772c504ad622ba909b0f6d2986910e7a97.zip mtk-20170518-088e28772c504ad622ba909b0f6d2986910e7a97.tar.gz mtk-20170518-088e28772c504ad622ba909b0f6d2986910e7a97.tar.bz2 | |
kernel: update kernel 4.4 to version 4.4.69
Refresh patches. A number of patches have landed upstream & hence are no
longer required locally:
062-[1-6]-MIPS-* series
042-0004-mtd-bcm47xxpart-fix-parsing-first-block
Reintroduced lantiq/patches-4.4/0050-MIPS-Lantiq-Fix-cascaded-IRQ-setup
as it was incorrectly included upstream thus dropped from LEDE.
As it has now been reverted upstream it needs to be included again for
LEDE.
Run tested ar71xx Archer C7 v2 and lantiq.
Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
[update from 4.4.68 to 4.4.69]
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Diffstat (limited to 'target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch')
| -rw-r--r-- | target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch b/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch index 10db076..35d1bd0 100644 --- a/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch +++ b/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch @@ -51,7 +51,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org> #define GSW_REG_PORT_PMCR(x) (0x3000 + (x * 0x100)) #define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100)) #define GSW_REG_SMACCR0 0x3fE4 -@@ -76,6 +78,7 @@ +@@ -82,6 +84,7 @@ #define PHY_PRE_EN BIT(30) #define PMY_MDC_CONF(_x) ((_x & 0x3f) << 24) |