ramips: add MT7620 MIB support for switch and port

Move definitions to header. Replace array size definitions with macro.

Signed-off-by: Vitaly Chekryzhev <13hakta@gmail.com>
[merged into 0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch]
Signed-off-by: Mathias Kresin <dev@kresin.me>
Acked-by: John Crispin <john@phrozen.org>

2 files changed, 351 insertions, 72 deletions

diff --git a/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch b/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch
index 3076e16..3ae5f51 100644
--- a/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch
+++ b/target/linux/ramips/patches-4.4/0513-net-mediatek-add-swconfig-driver-for-gsw_mt762x.patch
@@ -5,13 +5,15 @@ Subject: [PATCH 513/513] net: mediatek: add swconfig driver for gsw_mt762x
 
 Signed-off-by: John Crispin <blogic@openwrt.org>
 ---
- drivers/net/ethernet/mediatek/Makefile      |    4 +-
- drivers/net/ethernet/mediatek/mt7530.c      |  804 +++++++++++++++++++++++++++
- drivers/net/ethernet/mediatek/mt7530.h      |   20 +
- drivers/net/ethernet/mediatek/mtk_eth_soc.c |    9 +-
- drivers/net/ethernet/mediatek/mtk_eth_soc.h |    1 +
- drivers/net/ethernet/mediatek/soc_mt7620.c  |    1 +
- 6 files changed, 835 insertions(+), 4 deletions(-)
+ drivers/net/ethernet/mediatek/Makefile      |   4 +-
+ drivers/net/ethernet/mediatek/gsw_mt7620.c  |   3 +
+ drivers/net/ethernet/mediatek/gsw_mt7620.h  |   3 +
+ drivers/net/ethernet/mediatek/mt7530.c      | 884 ++++++++++++++++++++++++++++
+ drivers/net/ethernet/mediatek/mt7530.h      | 186 ++++++
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c |   9 +-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h |   1 +
+ drivers/net/ethernet/mediatek/soc_mt7620.c  |   1 +
+ 8 files changed, 1087 insertions(+), 4 deletions(-)
  create mode 100644 drivers/net/ethernet/mediatek/mt7530.c
  create mode 100644 drivers/net/ethernet/mediatek/mt7530.h
 
@@ -26,9 +28,40 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +obj-$(CONFIG_NET_MEDIATEK_GSW_MT7620)		+= gsw_mt7620.o mt7530.o
 +obj-$(CONFIG_NET_MEDIATEK_GSW_MT7621)		+= gsw_mt7621.o mt7530.o
  obj-$(CONFIG_NET_MEDIATEK_SOC)			+= mtk-eth-soc.o
+--- a/drivers/net/ethernet/mediatek/gsw_mt7620.c
++++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
+@@ -67,6 +67,9 @@ static void mt7620_hw_init(struct mt7620
+ 	rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
+ 	mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
+ 
++	/* Enable MIB stats */
++	mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
++
+ 	if (of_property_read_bool(np, "mediatek,mt7530")) {
+ 		u32 val;
+ 
+--- a/drivers/net/ethernet/mediatek/gsw_mt7620.h
++++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
+@@ -35,6 +35,8 @@
+ #define GSW_MDIO_ADDR_SHIFT	20
+ #define GSW_MDIO_REG_SHIFT	25
+ 
++#define GSW_REG_MIB_CNT_EN	0x4000
++
+ #define GSW_REG_PORT_PMCR(x)	(0x3000 + (x * 0x100))
+ #define GSW_REG_PORT_STATUS(x)	(0x3008 + (x * 0x100))
+ #define GSW_REG_SMACCR0		0x3fE4
+@@ -76,6 +78,7 @@
+ #define PHY_PRE_EN		BIT(30)
+ #define PMY_MDC_CONF(_x)	((_x & 0x3f) << 24)
+ 
++
+ enum {
+ 	/* Global attributes. */
+ 	GSW_ATTR_ENABLE_VLAN,
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mt7530.c
-@@ -0,0 +1,804 @@
+@@ -0,0 +1,884 @@
 +/*
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
@@ -41,6 +74,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 + * GNU General Public License for more details.
 + *
 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
 + */
 +
 +#include <linux/if.h>
@@ -107,49 +141,50 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	const char *name;
 +};
 +
-+#define MT7621_MIB_COUNTER_BASE	0x4000
-+#define MT7621_MIB_COUNTER_PORT_OFFSET	0x100
-+#define MT7621_STATS_TDPC	0x00
-+#define MT7621_STATS_TCRC	0x04
-+#define MT7621_STATS_TUPC	0x08
-+#define MT7621_STATS_TMPC	0x0C
-+#define MT7621_STATS_TBPC	0x10
-+#define MT7621_STATS_TCEC	0x14
-+#define MT7621_STATS_TSCEC	0x18
-+#define MT7621_STATS_TMCEC	0x1C
-+#define MT7621_STATS_TDEC	0x20
-+#define MT7621_STATS_TLCEC	0x24
-+#define MT7621_STATS_TXCEC	0x28
-+#define MT7621_STATS_TPPC	0x2C
-+#define MT7621_STATS_TL64PC	0x30
-+#define MT7621_STATS_TL65PC	0x34
-+#define MT7621_STATS_TL128PC	0x38
-+#define MT7621_STATS_TL256PC	0x3C
-+#define MT7621_STATS_TL512PC	0x40
-+#define MT7621_STATS_TL1024PC	0x44
-+#define MT7621_STATS_TOC	0x48
-+#define MT7621_STATS_RDPC	0x60
-+#define MT7621_STATS_RFPC	0x64
-+#define MT7621_STATS_RUPC	0x68
-+#define MT7621_STATS_RMPC	0x6C
-+#define MT7621_STATS_RBPC	0x70
-+#define MT7621_STATS_RAEPC	0x74
-+#define MT7621_STATS_RCEPC	0x78
-+#define MT7621_STATS_RUSPC	0x7C
-+#define MT7621_STATS_RFEPC	0x80
-+#define MT7621_STATS_ROSPC	0x84
-+#define MT7621_STATS_RJEPC	0x88
-+#define MT7621_STATS_RPPC	0x8C
-+#define MT7621_STATS_RL64PC	0x90
-+#define MT7621_STATS_RL65PC	0x94
-+#define MT7621_STATS_RL128PC	0x98
-+#define MT7621_STATS_RL256PC	0x9C
-+#define MT7621_STATS_RL512PC	0xA0
-+#define MT7621_STATS_RL1024PC	0xA4
-+#define MT7621_STATS_ROC	0xA8
-+#define MT7621_STATS_RDPC_CTRL	0xB0
-+#define MT7621_STATS_RDPC_ING	0xB4
-+#define MT7621_STATS_RDPC_ARL	0xB8
++static const struct mt7xxx_mib_desc mt7620_mibs[] = {
++	MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT0, "PPE_AC_BCNT0"),
++	MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT0, "PPE_AC_PCNT0"),
++	MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_BCNT63, "PPE_AC_BCNT63"),
++	MIB_DESC(1, MT7620_MIB_STATS_PPE_AC_PCNT63, "PPE_AC_PCNT63"),
++	MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT0, "PPE_MTR_CNT0"),
++	MIB_DESC(1, MT7620_MIB_STATS_PPE_MTR_CNT63, "PPE_MTR_CNT63"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GBCNT, "GDM1_TX_GBCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_GPCNT, "GDM1_TX_GPCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_SKIPCNT, "GDM1_TX_SKIPCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_TX_COLCNT, "GDM1_TX_COLCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GBCNT1, "GDM1_RX_GBCNT1"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_GPCNT1, "GDM1_RX_GPCNT1"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_OERCNT, "GDM1_RX_OERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FERCNT, "GDM1_RX_FERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_SERCNT, "GDM1_RX_SERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_LERCNT, "GDM1_RX_LERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_CERCNT, "GDM1_RX_CERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM1_RX_FCCNT, "GDM1_RX_FCCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GBCNT, "GDM2_TX_GBCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_GPCNT, "GDM2_TX_GPCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_SKIPCNT, "GDM2_TX_SKIPCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_TX_COLCNT, "GDM2_TX_COLCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GBCNT, "GDM2_RX_GBCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_GPCNT, "GDM2_RX_GPCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_OERCNT, "GDM2_RX_OERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FERCNT, "GDM2_RX_FERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_SERCNT, "GDM2_RX_SERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_LERCNT, "GDM2_RX_LERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_CERCNT, "GDM2_RX_CERCNT"),
++	MIB_DESC(1, MT7620_MIB_STATS_GDM2_RX_FCCNT, "GDM2_RX_FCCNT")
++};
++
++static const struct mt7xxx_mib_desc mt7620_port_mibs[] = {
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_TGPCN,  "TxGPC"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_TBOCN,  "TxBOC"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_TGOCN,  "TxGOC"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_TEPCN,  "TxEPC"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_RGPCN,  "RxGPC"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_RBOCN,  "RxBOC"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_RGOCN,  "RxGOC"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC1N, "RxEPC1"),
++	MIB_DESC(1, MT7620_MIB_STATS_PORT_REPC2N, "RxEPC2")
++};
 +
 +static const struct mt7xxx_mib_desc mt7621_mibs[] = {
 +	MIB_DESC(1, MT7621_STATS_TDPC, "TxDrop"),
@@ -650,35 +685,23 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return 0;
 +}
 +
-+static const struct switch_attr mt7530_global[] = {
-+	{
-+		.type = SWITCH_TYPE_INT,
-+		.name = "enable_vlan",
-+		.description = "VLAN mode (1:enabled)",
-+		.max = 1,
-+		.id = MT7530_ATTR_ENABLE_VLAN,
-+		.get = mt7530_get_vlan_enable,
-+		.set = mt7530_set_vlan_enable,
-+	},
-+};
-+
 +static u64 get_mib_counter(struct mt7530_priv *priv, int i, int port)
 +{
 +	unsigned int port_base;
-+	u64 t;
++	u64 lo;
 +
 +	port_base = MT7621_MIB_COUNTER_BASE +
 +		    MT7621_MIB_COUNTER_PORT_OFFSET * port;
 +
-+	t = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
++	lo = mt7530_r32(priv, port_base + mt7621_mibs[i].offset);
 +	if (mt7621_mibs[i].size == 2) {
 +		u64 hi;
 +
 +		hi = mt7530_r32(priv, port_base + mt7621_mibs[i].offset + 4);
-+		t |= hi << 32;
++		lo |= hi << 32;
 +	}
 +
-+	return t;
++	return lo;
 +}
 +
 +static int mt7621_sw_get_port_mib(struct switch_dev *dev,
@@ -695,7 +718,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	len += snprintf(buf + len, sizeof(buf) - len,
 +			"Port %d MIB counters\n", val->port_vlan);
 +
-+	for (i = 0; i < sizeof(mt7621_mibs) / sizeof(*mt7621_mibs); ++i) {
++	for (i = 0; i < ARRAY_SIZE(mt7621_mibs); ++i) {
 +		u64 counter;
 +		len += snprintf(buf + len, sizeof(buf) - len,
 +				"%-11s: ", mt7621_mibs[i].name);
@@ -709,6 +732,89 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +	return 0;
 +}
 +
++static u64 get_mib_counter_7620(struct mt7530_priv *priv, int i)
++{
++	return mt7530_r32(priv, MT7620_MIB_COUNTER_BASE + mt7620_mibs[i].offset);
++}
++
++static u64 get_mib_counter_port_7620(struct mt7530_priv *priv, int i, int port)
++{
++	return mt7530_r32(priv,
++			MT7620_MIB_COUNTER_BASE_PORT +
++			(MT7620_MIB_COUNTER_PORT_OFFSET * port) +
++			mt7620_port_mibs[i].offset);
++}
++
++static int mt7530_sw_get_mib(struct switch_dev *dev,
++				  const struct switch_attr *attr,
++				  struct switch_val *val)
++{
++	static char buf[4096];
++	struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++	int i, len = 0;
++
++	len += snprintf(buf + len, sizeof(buf) - len, "Switch MIB counters\n");
++
++	for (i = 0; i < ARRAY_SIZE(mt7620_mibs); ++i) {
++		u64 counter;
++		len += snprintf(buf + len, sizeof(buf) - len,
++				"%-11s: ", mt7620_mibs[i].name);
++		counter = get_mib_counter_7620(priv, i);
++		len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
++				counter);
++	}
++
++	val->value.s = buf;
++	val->len = len;
++	return 0;
++}
++
++static int mt7530_sw_get_port_mib(struct switch_dev *dev,
++				  const struct switch_attr *attr,
++				  struct switch_val *val)
++{
++	static char buf[4096];
++	struct mt7530_priv *priv = container_of(dev, struct mt7530_priv, swdev);
++	int i, len = 0;
++
++	if (val->port_vlan >= MT7530_NUM_PORTS)
++		return -EINVAL;
++
++	len += snprintf(buf + len, sizeof(buf) - len,
++			"Port %d MIB counters\n", val->port_vlan);
++
++	for (i = 0; i < ARRAY_SIZE(mt7620_port_mibs); ++i) {
++		u64 counter;
++		len += snprintf(buf + len, sizeof(buf) - len,
++				"%-11s: ", mt7620_port_mibs[i].name);
++		counter = get_mib_counter_port_7620(priv, i, val->port_vlan);
++		len += snprintf(buf + len, sizeof(buf) - len, "%llu\n",
++				counter);
++	}
++
++	val->value.s = buf;
++	val->len = len;
++	return 0;
++}
++
++static const struct switch_attr mt7530_global[] = {
++	{
++		.type = SWITCH_TYPE_INT,
++		.name = "enable_vlan",
++		.description = "VLAN mode (1:enabled)",
++		.max = 1,
++		.id = MT7530_ATTR_ENABLE_VLAN,
++		.get = mt7530_get_vlan_enable,
++		.set = mt7530_set_vlan_enable,
++	}, {
++		.type = SWITCH_TYPE_STRING,
++		.name = "mib",
++		.description = "Get MIB counters for switch",
++		.get = mt7530_sw_get_mib,
++		.set = NULL,
++	},
++};
++
 +static const struct switch_attr mt7621_port[] = {
 +	{
 +		.type = SWITCH_TYPE_STRING,
@@ -720,6 +826,13 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +};
 +
 +static const struct switch_attr mt7530_port[] = {
++	{
++		.type = SWITCH_TYPE_STRING,
++		.name = "mib",
++		.description = "Get MIB counters for port",
++		.get = mt7530_sw_get_port_mib,
++		.set = NULL,
++	},
 +};
 +
 +static const struct switch_attr mt7530_vlan[] = {
@@ -835,7 +948,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 +}
 --- /dev/null
 +++ b/drivers/net/ethernet/mediatek/mt7530.h
-@@ -0,0 +1,20 @@
+@@ -0,0 +1,186 @@
 +/*
 + * This program is free software; you can redistribute it and/or
 + * modify it under the terms of the GNU General Public License
@@ -848,11 +961,177 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
 + * GNU General Public License for more details.
 + *
 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
++ * Copyright (C) 2016 Vitaly Chekryzhev <13hakta@gmail.com>
 + */
 +
 +#ifndef _MT7530_H__
 +#define _MT7530_H__
 +
++#define MT7620_MIB_COUNTER_BASE_PORT	0x4000
++#define MT7620_MIB_COUNTER_PORT_OFFSET	0x100
++#define MT7620_MIB_COUNTER_BASE	0x1010
++
++/* PPE Accounting Group #0 Byte Counter */
++#define MT7620_MIB_STATS_PPE_AC_BCNT0	0x000
++
++/* PPE Accounting Group #0 Packet Counter */
++#define MT7620_MIB_STATS_PPE_AC_PCNT0	0x004
++
++/* PPE Accounting Group #63 Byte Counter */
++#define MT7620_MIB_STATS_PPE_AC_BCNT63	0x1F8
++
++/* PPE Accounting Group #63 Packet Counter */
++#define MT7620_MIB_STATS_PPE_AC_PCNT63	0x1FC
++
++/* PPE Meter Group #0 */
++#define MT7620_MIB_STATS_PPE_MTR_CNT0	0x200
++
++/* PPE Meter Group #63 */
++#define MT7620_MIB_STATS_PPE_MTR_CNT63	0x2FC
++
++/* Transmit good byte count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_TX_GBCNT	0x300
++
++/* Transmit good packet count for CPU GDM (exclude flow control frames) */
++#define MT7620_MIB_STATS_GDM1_TX_GPCNT	0x304
++
++/* Transmit abort count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_TX_SKIPCNT	0x308
++
++/* Transmit collision count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_TX_COLCNT	0x30C
++
++/* Received good byte count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_RX_GBCNT1	0x320
++
++/* Received good packet count for CPU GDM (exclude flow control frame) */
++#define MT7620_MIB_STATS_GDM1_RX_GPCNT1	0x324
++
++/* Received overflow error packet count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_RX_OERCNT	0x328
++
++/* Received FCS error packet count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_RX_FERCNT	0x32C
++
++/* Received too short error packet count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_RX_SERCNT	0x330
++
++/* Received too long error packet count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_RX_LERCNT	0x334
++
++/* Received IP/TCP/UDP checksum error packet count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_RX_CERCNT	0x338
++
++/* Received flow control pkt count for CPU GDM */
++#define MT7620_MIB_STATS_GDM1_RX_FCCNT	0x33C
++
++/* Transmit good byte count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_TX_GBCNT	0x340
++
++/* Transmit good packet count for PPE GDM (exclude flow control frames) */
++#define MT7620_MIB_STATS_GDM2_TX_GPCNT	0x344
++
++/* Transmit abort count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_TX_SKIPCNT	0x348
++
++/* Transmit collision count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_TX_COLCNT	0x34C
++
++/* Received good byte count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_RX_GBCNT	0x360
++
++/* Received good packet count for PPE GDM (exclude flow control frame) */
++#define MT7620_MIB_STATS_GDM2_RX_GPCNT	0x364
++
++/* Received overflow error packet count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_RX_OERCNT	0x368
++
++/* Received FCS error packet count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_RX_FERCNT	0x36C
++
++/* Received too short error packet count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_RX_SERCNT	0x370
++
++/* Received too long error packet count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_RX_LERCNT	0x374
++
++/* Received IP/TCP/UDP checksum error packet count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_RX_CERCNT	0x378
++
++/* Received flow control pkt count for PPE GDM */
++#define MT7620_MIB_STATS_GDM2_RX_FCCNT	0x37C
++
++/* Tx Packet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_TGPCN	0x10
++
++/* Tx Bad Octet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_TBOCN	0x14
++
++/* Tx Good Octet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_TGOCN	0x18
++
++/* Tx Event Packet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_TEPCN	0x1C
++
++/* Rx Packet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_RGPCN	0x20
++
++/* Rx Bad Octet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_RBOCN	0x24
++
++/* Rx Good Octet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_RGOCN	0x28
++
++/* Rx Event Packet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_REPC1N	0x2C
++
++/* Rx Event Packet Counter of Port n */
++#define MT7620_MIB_STATS_PORT_REPC2N	0x30
++
++#define MT7621_MIB_COUNTER_BASE	0x4000
++#define MT7621_MIB_COUNTER_PORT_OFFSET	0x100
++#define MT7621_STATS_TDPC	0x00
++#define MT7621_STATS_TCRC	0x04
++#define MT7621_STATS_TUPC	0x08
++#define MT7621_STATS_TMPC	0x0C
++#define MT7621_STATS_TBPC	0x10
++#define MT7621_STATS_TCEC	0x14
++#define MT7621_STATS_TSCEC	0x18
++#define MT7621_STATS_TMCEC	0x1C
++#define MT7621_STATS_TDEC	0x20
++#define MT7621_STATS_TLCEC	0x24
++#define MT7621_STATS_TXCEC	0x28
++#define MT7621_STATS_TPPC	0x2C
++#define MT7621_STATS_TL64PC	0x30
++#define MT7621_STATS_TL65PC	0x34
++#define MT7621_STATS_TL128PC	0x38
++#define MT7621_STATS_TL256PC	0x3C
++#define MT7621_STATS_TL512PC	0x40
++#define MT7621_STATS_TL1024PC	0x44
++#define MT7621_STATS_TOC	0x48
++#define MT7621_STATS_RDPC	0x60
++#define MT7621_STATS_RFPC	0x64
++#define MT7621_STATS_RUPC	0x68
++#define MT7621_STATS_RMPC	0x6C
++#define MT7621_STATS_RBPC	0x70
++#define MT7621_STATS_RAEPC	0x74
++#define MT7621_STATS_RCEPC	0x78
++#define MT7621_STATS_RUSPC	0x7C
++#define MT7621_STATS_RFEPC	0x80
++#define MT7621_STATS_ROSPC	0x84
++#define MT7621_STATS_RJEPC	0x88
++#define MT7621_STATS_RPPC	0x8C
++#define MT7621_STATS_RL64PC	0x90
++#define MT7621_STATS_RL65PC	0x94
++#define MT7621_STATS_RL128PC	0x98
++#define MT7621_STATS_RL256PC	0x9C
++#define MT7621_STATS_RL512PC	0xA0
++#define MT7621_STATS_RL1024PC	0xA4
++#define MT7621_STATS_ROC	0xA8
++#define MT7621_STATS_RDPC_CTRL	0xB0
++#define MT7621_STATS_RDPC_ING	0xB4
++#define MT7621_STATS_RDPC_ARL	0xB8
++
 +int mt7530_probe(struct device *dev, void __iomem *base, struct mii_bus *bus, int vlan);
 +
 +#endif
diff --git a/target/linux/ramips/patches-4.4/0519-gsw_mt7621.patch b/target/linux/ramips/patches-4.4/0519-gsw_mt7621.patch
index 67e9060..45e320b 100644
--- a/target/linux/ramips/patches-4.4/0519-gsw_mt7621.patch
+++ b/target/linux/ramips/patches-4.4/0519-gsw_mt7621.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/ethernet/mediatek/mt7530.c
 +++ b/drivers/net/ethernet/mediatek/mt7530.c
-@@ -539,6 +539,7 @@ mt7530_apply_config(struct switch_dev *d
+@@ -541,6 +541,7 @@ mt7530_apply_config(struct switch_dev *d
  		u8 etags = priv->vlan_entries[i].etags;
  		u32 val;
  
@@ -8,7 +8,7 @@
  		/* vid of vlan */
  		val = mt7530_r32(priv, REG_ESW_VLAN_VTIM(i));
  		if (i % 2 == 0) {
-@@ -549,7 +550,7 @@ mt7530_apply_config(struct switch_dev *d
+@@ -551,7 +552,7 @@ mt7530_apply_config(struct switch_dev *d
  			val |= (vid << 12);
  		}
  		mt7530_w32(priv, REG_ESW_VLAN_VTIM(i), val);
@@ -17,7 +17,7 @@
  		/* vlan port membership */
  		if (member)
  			mt7530_w32(priv, REG_ESW_VLAN_VAWD1, REG_ESW_VLAN_VAWD1_IVL_MAC |
-@@ -569,7 +570,11 @@ mt7530_apply_config(struct switch_dev *d
+@@ -571,7 +572,11 @@ mt7530_apply_config(struct switch_dev *d
  		mt7530_w32(priv, REG_ESW_VLAN_VAWD2, val);
  
  		/* write to vlan table */