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| author | Zoltan Herpai <wigyori@uid0.hu> | 2013-11-14 23:12:52 +0000 |
|---|---|---|
| committer | Zoltan Herpai <wigyori@uid0.hu> | 2013-11-14 23:12:52 +0000 |
| commit | f58bfd1df4e4a9b84a0e94691986c38bab6d8730 (patch) | |
| tree | 9efce69525f7b07a108c03ba53b6721ebb1c8be2 /target/linux/sunxi/patches-3.12/143-add-dtsi-for-reset.patch | |
| parent | 2077361f128ff32dd6bb9fed7a4b3cd813863a9c (diff) | |
| download | mtk-20170518-f58bfd1df4e4a9b84a0e94691986c38bab6d8730.zip mtk-20170518-f58bfd1df4e4a9b84a0e94691986c38bab6d8730.tar.gz mtk-20170518-f58bfd1df4e4a9b84a0e94691986c38bab6d8730.tar.bz2 | |
sunxi: rework target - update kernel to 3.12 - add patches for clocks, i2c, usb, sid, rtc - support common image for A10/A13/A20 - add support for a couple boards - most drivers are configured into the kernel as of now
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
SVN-Revision: 38811
Diffstat (limited to 'target/linux/sunxi/patches-3.12/143-add-dtsi-for-reset.patch')
| -rw-r--r-- | target/linux/sunxi/patches-3.12/143-add-dtsi-for-reset.patch | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/target/linux/sunxi/patches-3.12/143-add-dtsi-for-reset.patch b/target/linux/sunxi/patches-3.12/143-add-dtsi-for-reset.patch new file mode 100644 index 0000000..62ade36 --- /dev/null +++ b/target/linux/sunxi/patches-3.12/143-add-dtsi-for-reset.patch @@ -0,0 +1,94 @@ +From 2a906d06b21968803ce504348864908ad1ed66ac Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Tue, 24 Sep 2013 11:10:41 +0300 +Subject: [PATCH] ARM: sun6i: Add the reset controller to the DTSI + +The A31 has a reset controller IP that maintains a few other IPs in +reset, among which we can find the UARTs, high speed timers or the I2C. +Now that we have support for them, add the reset controllers to the DTSI. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm/boot/dts/sun6i-a31.dtsi | 24 ++++++++++++++++++++++++ + 1 file changed, 24 insertions(+) + +diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi +index c1751a6..c7e0658 100644 +--- a/arch/arm/boot/dts/sun6i-a31.dtsi ++++ b/arch/arm/boot/dts/sun6i-a31.dtsi +@@ -209,6 +209,24 @@ + }; + }; + ++ ahb1_rst: reset@01c202c0 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun6i-a31-ahb1-reset"; ++ reg = <0x01c202c0 0xc>; ++ }; ++ ++ apb1_rst: reset@01c202d0 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun4i-clock-reset"; ++ reg = <0x01c202d0 0x4>; ++ }; ++ ++ apb2_rst: reset@01c202d8 { ++ #reset-cells = <1>; ++ compatible = "allwinner,sun4i-clock-reset"; ++ reg = <0x01c202d8 0x4>; ++ }; ++ + timer@01c20c00 { + compatible = "allwinner,sun4i-timer"; + reg = <0x01c20c00 0xa0>; +@@ -232,6 +250,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 16>; ++ resets = <&apb2_rst 16>; + status = "disabled"; + }; + +@@ -242,6 +261,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 17>; ++ resets = <&apb2_rst 17>; + status = "disabled"; + }; + +@@ -252,6 +272,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 18>; ++ resets = <&apb2_rst 18>; + status = "disabled"; + }; + +@@ -262,6 +283,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 19>; ++ resets = <&apb2_rst 19>; + status = "disabled"; + }; + +@@ -272,6 +294,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 20>; ++ resets = <&apb2_rst 20>; + status = "disabled"; + }; + +@@ -282,6 +305,7 @@ + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&apb2_gates 21>; ++ resets = <&apb2_rst 21>; + status = "disabled"; + }; + +-- +1.8.4 + |