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authorZoltan Herpai <wigyori@uid0.hu>2014-03-05 23:19:25 +0000
committerZoltan Herpai <wigyori@uid0.hu>2014-03-05 23:19:25 +0000
commit301baf34ddbc838b61dfd8564b27a440f0b85e5a (patch)
treee676718f90241c41d5dc1da4b8a94eba0ab3fddd /target/linux/sunxi/patches-3.12/185-clk-sunxi-mmc-phasectrl.patch
parent6892ed8193e8a195a6b5302bb55b24acdbf79abc (diff)
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sunxi: deprecate 3.12 support
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu> SVN-Revision: 39780
Diffstat (limited to 'target/linux/sunxi/patches-3.12/185-clk-sunxi-mmc-phasectrl.patch')
-rw-r--r--target/linux/sunxi/patches-3.12/185-clk-sunxi-mmc-phasectrl.patch62
1 files changed, 0 insertions, 62 deletions
diff --git a/target/linux/sunxi/patches-3.12/185-clk-sunxi-mmc-phasectrl.patch b/target/linux/sunxi/patches-3.12/185-clk-sunxi-mmc-phasectrl.patch
deleted file mode 100644
index f75394b..0000000
--- a/target/linux/sunxi/patches-3.12/185-clk-sunxi-mmc-phasectrl.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From e074907f73e0bc70740901fb4a05fdf5fc81b3ff Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?Emilio=20L=C3=B3pez?= <emilio@elopez.com.ar>
-Date: Fri, 20 Sep 2013 20:29:17 -0300
-Subject: [PATCH] clk: sunxi: Implement MMC phase control
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Signed-off-by: Emilio López <emilio@elopez.com.ar>
----
- drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
- 1 file changed, 35 insertions(+)
-
-diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
-index 360d705..d2b8d3c 100644
---- a/drivers/clk/sunxi/clk-sunxi.c
-+++ b/drivers/clk/sunxi/clk-sunxi.c
-@@ -352,6 +352,41 @@ static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
-
-
- /**
-+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
-+ */
-+
-+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
-+{
-+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
-+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
-+
-+ struct clk_composite *composite = to_clk_composite(hw);
-+ struct clk_hw *rate_hw = composite->rate_hw;
-+ struct clk_factors *factors = to_clk_factors(rate_hw);
-+ unsigned long flags = 0;
-+ u32 reg;
-+
-+ if (factors->lock)
-+ spin_lock_irqsave(factors->lock, flags);
-+
-+ reg = readl(factors->reg);
-+
-+ /* set sample clock phase control */
-+ reg &= ~(0x7 << 20);
-+ reg |= ((sample & 0x7) << 20);
-+
-+ /* set output clock phase control */
-+ reg &= ~(0x7 << 8);
-+ reg |= ((output & 0x7) << 8);
-+
-+ writel(reg, factors->reg);
-+
-+ if (factors->lock)
-+ spin_unlock_irqrestore(factors->lock, flags);
-+}
-+
-+
-+/**
- * sunxi_factors_clk_setup() - Setup function for factor clocks
- */
-
---
-1.8.5.1
-