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authorGabor Juhos <juhosg@openwrt.org>2012-03-19 11:11:22 +0000
committerGabor Juhos <juhosg@openwrt.org>2012-03-19 11:11:22 +0000
commite89df990836b705b52a3d558a86987e8f9340c07 (patch)
tree04f912f76b2c84bfd05af538021b778ff71039fb /target/linux
parente9b45ebaba6dbc17bfc0cd8085e53828216c1457 (diff)
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ar71xx: use a different pll value on DB120
SVN-Revision: 31018
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch3
-rw-r--r--target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch3
2 files changed, 4 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch
index a758dc0..a7f1afc 100644
--- a/target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch
+++ b/target/linux/ar71xx/patches-3.2/605-MIPS-ath79-db120-fixes.patch
@@ -62,7 +62,7 @@
};
static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-@@ -95,66 +111,89 @@ static struct gpio_keys_button db120_gpi
+@@ -95,66 +111,90 @@ static struct gpio_keys_button db120_gpi
},
};
@@ -176,6 +176,7 @@
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = BIT(0);
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++ ath79_eth0_pll_data.pll_1000 = 0x06000000;
+ ath79_register_eth(0);
+
+ /* GMAC1 is connected to the internal switch */
diff --git a/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
index a758dc0..a7f1afc 100644
--- a/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
+++ b/target/linux/ar71xx/patches-3.3/605-MIPS-ath79-db120-fixes.patch
@@ -62,7 +62,7 @@
};
static struct gpio_keys_button db120_gpio_keys[] __initdata = {
-@@ -95,66 +111,89 @@ static struct gpio_keys_button db120_gpi
+@@ -95,66 +111,90 @@ static struct gpio_keys_button db120_gpi
},
};
@@ -176,6 +176,7 @@
+ ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
+ ath79_eth0_data.phy_mask = BIT(0);
+ ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
++ ath79_eth0_pll_data.pll_1000 = 0x06000000;
+ ath79_register_eth(0);
+
+ /* GMAC1 is connected to the internal switch */