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authorFelix Fietkau <nbd@openwrt.org>2013-07-13 22:29:53 +0000
committerFelix Fietkau <nbd@openwrt.org>2013-07-13 22:29:53 +0000
commit9b9c6facfc9f887e5bee3628752ff4572730fbfa (patch)
tree499f7ff2313a573c259dc9e45bb764cf96ad68ea /target/linux
parente041d370a74a68c6cd0d45880bc22a87d08ea97d (diff)
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ar71xx: fix ar933x watchdog clock (#13866)
Signed-off-by: Felix Fietkau <nbd@openwrt.org> SVN-Revision: 37273
Diffstat (limited to 'target/linux')
-rw-r--r--target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch15
-rw-r--r--target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch15
2 files changed, 30 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch b/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch
new file mode 100644
index 0000000..b3a3cd3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.10/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch
@@ -0,0 +1,15 @@
+From: Felix Fietkau <nbd@openwrt.org>
+Subject: [PATCH] MIPS: ath79: fix ar933x watchdog clock
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -164,7 +164,7 @@ static void __init ar933x_clocks_init(vo
+ ath79_ahb_clk.rate = freq / t;
+ }
+
+- ath79_wdt_clk.rate = ath79_ref_clk.rate;
++ ath79_wdt_clk.rate = ath79_ahb_clk.rate;
+ ath79_uart_clk.rate = ath79_ref_clk.rate;
+ }
+
diff --git a/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch b/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch
new file mode 100644
index 0000000..b3a3cd3
--- /dev/null
+++ b/target/linux/ar71xx/patches-3.8/200-MIPS-ath79-fix-ar933x-watchdog-clock.patch
@@ -0,0 +1,15 @@
+From: Felix Fietkau <nbd@openwrt.org>
+Subject: [PATCH] MIPS: ath79: fix ar933x watchdog clock
+
+Signed-off-by: Felix Fietkau <nbd@openwrt.org>
+--- a/arch/mips/ath79/clock.c
++++ b/arch/mips/ath79/clock.c
+@@ -164,7 +164,7 @@ static void __init ar933x_clocks_init(vo
+ ath79_ahb_clk.rate = freq / t;
+ }
+
+- ath79_wdt_clk.rate = ath79_ref_clk.rate;
++ ath79_wdt_clk.rate = ath79_ahb_clk.rate;
+ ath79_uart_clk.rate = ath79_ref_clk.rate;
+ }
+