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authorJohn Crispin <john@openwrt.org>2015-08-17 06:15:34 +0000
committerJohn Crispin <john@openwrt.org>2015-08-17 06:15:34 +0000
commit9ed654e389efe969785f7b0e4c40c9c63fed9bbe (patch)
tree37040b1f19cca716abc3a54170b152f601b5eeec /target
parent27a40c79b0f1b1f09465eea661e7847c2cd65d88 (diff)
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ramips: Fix uart2/uart3 pinmux order on MT7621
The uart3 setting in GPIO_MODE register is before the uart2 setting. Also don't mix uart2 and uart3 function/groups. Signed-off-by: Sven Eckelmann <sven@open-mesh.com> SVN-Revision: 46643
Diffstat (limited to 'target')
-rw-r--r--target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch8
1 files changed, 4 insertions, 4 deletions
diff --git a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
index 771de12..f08ecb0 100644
--- a/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
+++ b/target/linux/ramips/patches-3.18/0012-MIPS-ralink-add-MT7621-support.patch
@@ -555,8 +555,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+
+#define MT7621_GPIO_MODE_UART1 1
+#define MT7621_GPIO_MODE_I2C 2
-+#define MT7621_GPIO_MODE_UART2 3
-+#define MT7621_GPIO_MODE_UART3 5
++#define MT7621_GPIO_MODE_UART3 3
++#define MT7621_GPIO_MODE_UART2 5
+#define MT7621_GPIO_MODE_JTAG 7
+#define MT7621_GPIO_MODE_WDT_MASK 0x3
+#define MT7621_GPIO_MODE_WDT_SHIFT 8
@@ -604,8 +604,8 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+static struct rt2880_pmx_group mt7621_pinmux_data[] = {
+ GRP("uart1", uart1_grp, 1, MT7621_GPIO_MODE_UART1),
+ GRP("i2c", i2c_grp, 1, MT7621_GPIO_MODE_I2C),
-+ GRP("uart3", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
-+ GRP("uart2", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
++ GRP("uart3", uart3_grp, 1, MT7621_GPIO_MODE_UART3),
++ GRP("uart2", uart2_grp, 1, MT7621_GPIO_MODE_UART2),
+ GRP("jtag", jtag_grp, 1, MT7621_GPIO_MODE_JTAG),
+ GRP_G("wdt", wdt_grp, MT7621_GPIO_MODE_WDT_MASK,
+ MT7621_GPIO_MODE_WDT_GPIO, MT7621_GPIO_MODE_WDT_SHIFT),