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authorGabor Juhos <juhosg@openwrt.org>2008-12-02 08:49:22 +0000
committerGabor Juhos <juhosg@openwrt.org>2008-12-02 08:49:22 +0000
commit19a57a77948f0fef8f4a7d5367517644c810a9cf (patch)
treee7a308ab377f1c32f1c6e9e277263f3d881e6dfa /target
parent2d3a12991c14b28c2760119b4481dd09d072426b (diff)
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ag71xx driver: fix RX_STATUS_OF bitmask, and add DMA status register bit descriptions
SVN-Revision: 13463
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
index 5d97fdf..ab9887f 100644
--- a/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
+++ b/target/linux/ar71xx/files/drivers/net/ag71xx/ag71xx.h
@@ -37,7 +37,7 @@
#define ETH_FCS_LEN 4
#define AG71XX_DRV_NAME "ag71xx"
-#define AG71XX_DRV_VERSION "0.5.4"
+#define AG71XX_DRV_VERSION "0.5.5"
#define AG71XX_NAPI_TX 1
@@ -287,17 +287,17 @@ static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
#define MII_IND_BUSY BIT(0)
#define MII_IND_INVALID BIT(2)
-#define TX_CTRL_TXE BIT(0)
+#define TX_CTRL_TXE BIT(0) /* Tx Enable */
-#define TX_STATUS_PS BIT(0)
-#define TX_STATUS_UR BIT(1)
-#define TX_STATUS_BE BIT(3)
+#define TX_STATUS_PS BIT(0) /* Packet Sent */
+#define TX_STATUS_UR BIT(1) /* Tx Underrun */
+#define TX_STATUS_BE BIT(3) /* Bus Error */
-#define RX_CTRL_RXE BIT(0)
+#define RX_CTRL_RXE BIT(0) /* Rx Enable */
-#define RX_STATUS_PR BIT(0)
-#define RX_STATUS_OF BIT(1)
-#define RX_STATUS_BE BIT(3)
+#define RX_STATUS_PR BIT(0) /* Packet Received */
+#define RX_STATUS_OF BIT(2) /* Rx Overflow */
+#define RX_STATUS_BE BIT(3) /* Bus Error */
#define MII_CTRL_IF_MASK 3
#define MII_CTRL_SPEED_SHIFT 4