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authorFelix Fietkau <nbd@nbd.name>2017-02-17 11:51:42 +0100
committerFelix Fietkau <nbd@nbd.name>2017-02-17 12:17:39 +0100
commitf88bd7cd0f7c03d959330443be5adabf70351a27 (patch)
tree497a5d5729dc8ae611ae8847adbbfd2674e1101e /target
parent828a024c81bfee065aecfc88d7fe0f2409ef77d7 (diff)
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ar71xx: fix ethernet PLL configuration for QCA956x
QCA956x is configured like AR934x, not like the older chips. Should fix ethernet hangs when using the WAN port without SGMII Signed-off-by: Felix Fietkau <nbd@nbd.name>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 07cb12c..790c2d3 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -1075,7 +1075,7 @@ void __init ath79_register_eth(unsigned int id)
if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
pdata->set_speed = qca956x_set_speed_sgmii;
else
- pdata->set_speed = ath79_set_speed_ge0;
+ pdata->set_speed = ar934x_set_speed_ge0;
} else {
pdata->reset_bit = QCA955X_RESET_GE1_MAC |
QCA955X_RESET_GE1_MDIO;