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authorFelix Fietkau <nbd@openwrt.org>2014-09-07 09:45:32 +0000
committerFelix Fietkau <nbd@openwrt.org>2014-09-07 09:45:32 +0000
commit60b81acd602496d9b929d680c78b387d06b80ed1 (patch)
treeb86a1dd7080a4909e6e45f818d24b8393daa6692 /target
parent288e50a79ced282f4396d42bb0c21cecd6e2e31e (diff)
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ath79: dev-eth: Don't advertise 1gbit in link code word on ar9331
While the AR9331 has a gigabit MAC towards the internal switch, the integrated PHYs however are only 100-base-tx capable. The existing code however advertieses gigabit capability in the link status word. If you attach such a PHY to a gigabit capable switch on the remote end, with some probability it attempts to negotiate gigabit and fails, falling baco to the AR9331 assuming a 10mbit half-duplex link. This has been observed quite frequently with the Carambola2 and gigabit capable switches. In ath79_register_eth(), "pdata->has_gbit = 1;" is set unconditionally for both AR9331 ethernet ports. This is most likely wrong. Despite the two MAC IP cores being gigabit MACs, the MAC for eth1 is connected to a 100base-T PHY via MII. The has_gbit attribute is used in the ethernet driver to determine the supported link modes. So either pdata->has_gbit is not set to 1 anymore, or the ethernet driver needs to be modified to determine the advertised link code word on another criteria than pdata->has_gbit. This patch implements the former solution. Signed-off-by: Harald Welte <laforge@gnumonks.org> SVN-Revision: 42432
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
index 227f16e..f106e22 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
@@ -940,13 +940,13 @@ void __init ath79_register_eth(unsigned int id)
pdata->set_speed = ath79_set_speed_dummy;
pdata->speed = SPEED_1000;
+ pdata->has_gbit = 1;
pdata->duplex = DUPLEX_FULL;
pdata->switch_data = &ath79_switch_data;
ath79_switch_data.phy_poll_mask |= BIT(4);
}
- pdata->has_gbit = 1;
pdata->is_ar724x = 1;
if (!pdata->fifo_cfg1)