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authorGabor Juhos <juhosg@openwrt.org>2010-03-18 19:18:58 +0000
committerGabor Juhos <juhosg@openwrt.org>2010-03-18 19:18:58 +0000
commit695e989c6f12f1c01a02f5464f2e2547cf257415 (patch)
tree5ba245087f8a9c7b69f89430e4c119300eddff71 /target
parent5f109ef2f3297cf05a7bc7e9ba190911e9d65286 (diff)
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ar71xx: move ar724x_pci_* helpers to ar724x-pci.c
SVN-Revision: 20282
Diffstat (limited to 'target')
-rw-r--r--target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h30
-rw-r--r--target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c30
2 files changed, 30 insertions, 30 deletions
diff --git a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
index 8ac5598..31d2fd8 100644
--- a/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
+++ b/target/linux/ar71xx/files/arch/mips/include/asm/mach-ar71xx/ar71xx.h
@@ -356,36 +356,6 @@ void ar71xx_ddr_flush(u32 reg);
#define AR724X_PCI_INT_DEV0 BIT(14)
-static inline void ar724x_pci_wr(unsigned reg, u32 val)
-{
- void __iomem *base;
-
- base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
- __raw_writel(val, base + reg);
- (void) __raw_readl(base + reg);
- iounmap(base);
-}
-
-static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
-{
- void __iomem *base;
-
- base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
- __raw_writel(val, base + reg);
- iounmap(base);
-}
-
-static inline u32 ar724x_pci_rr(unsigned reg)
-{
- void __iomem *base;
- u32 ret;
-
- base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
- ret = __raw_readl(base + reg);
- iounmap(base);
- return ret;
-}
-
/*
* RESET block
*/
diff --git a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
index 617d1eb..9d37561 100644
--- a/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
+++ b/target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c
@@ -34,6 +34,36 @@ static int ar724x_pci_fixup_enable;
static DEFINE_SPINLOCK(ar724x_pci_lock);
+static inline void ar724x_pci_wr(unsigned reg, u32 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ __raw_writel(val, base + reg);
+ (void) __raw_readl(base + reg);
+ iounmap(base);
+}
+
+static inline void ar724x_pci_wr_nf(unsigned reg, u32 val)
+{
+ void __iomem *base;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ __raw_writel(val, base + reg);
+ iounmap(base);
+}
+
+static inline u32 ar724x_pci_rr(unsigned reg)
+{
+ void __iomem *base;
+ u32 ret;
+
+ base = ioremap_nocache(AR724X_PCI_CTRL_BASE, AR724X_PCI_CTRL_SIZE);
+ ret = __raw_readl(base + reg);
+ iounmap(base);
+ return ret;
+}
+
static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
{
unsigned long flags;