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authorFelix Fietkau <nbd@openwrt.org>2015-08-04 23:09:55 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-08-04 23:09:55 +0000
commitf7651fdba51fae235bb9e43fcecc0478faf927d0 (patch)
treedf2c2dfd4c247210c9ba11828619b5eaf1584b91 /target
parentc4c986e419d7098104681c364978d065a3b7f2e1 (diff)
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ipq806x: fix pcie pinmux naming in ipq806x dts
PCIe controller nodes are numbers 0/1/2 in the chipset dtsi file, but the pinmux nodes are numbers 1/2/3. We'll make it consistent by changing the pinmux numbering to match the controller's one. Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> SVN-Revision: 46556
Diffstat (limited to 'target')
-rw-r--r--target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch31
-rw-r--r--target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch10
-rw-r--r--target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch13
-rw-r--r--target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch25
-rw-r--r--target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch4
-rw-r--r--target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch6
6 files changed, 40 insertions, 49 deletions
diff --git a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index 80ac25f..bdc91fb 100644
--- a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -15,11 +15,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -30,6 +30,22 @@
+@@ -35,6 +35,22 @@
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -27,7 +27,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -38,7 +38,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
-@@ -133,5 +149,19 @@
+@@ -138,5 +154,19 @@
usb30@1 {
status = "ok";
};
@@ -46,14 +46,14 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -64,7 +64,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -80,7 +80,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie3_pins: pcie3_pinmux {
++ pcie2_pins: pcie2_pinmux {
+ mux {
+ pins = "gpio63";
+ drive-strength = <2>;
@@ -99,21 +99,21 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie2: pci@1b900000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 63 0>;
-+ pinctrl-0 = <&pcie3_pins>;
++ pinctrl-0 = <&pcie2_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -259,10 +259,3 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
hs_phy_1: phy@100f8800 {
compatible = "qcom,dwc3-hs-usb-phy";
reg = <0x100f8800 0x30>;
-@@ -389,6 +514,5 @@
- dr_mode = "host";
- };
- };
--
- };
- };
diff --git a/target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch b/target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
index 809d743..851682a 100644
--- a/target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
+++ b/target/linux/ipq806x/patches-3.18/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
@@ -11,7 +11,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -14,8 +14,9 @@
+@@ -19,8 +19,9 @@
};
};
@@ -22,7 +22,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
chosen {
-@@ -54,6 +55,15 @@
+@@ -59,6 +60,15 @@
bias-none;
};
};
@@ -38,8 +38,8 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
gsbi@16300000 {
-@@ -163,5 +173,33 @@
- pinctrl-0 = <&pcie2_pins>;
+@@ -168,5 +178,33 @@
+ pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
};
+
@@ -99,7 +99,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
gsbi2: gsbi@12480000 {
@@ -173,5 +183,44 @@
- pinctrl-0 = <&pcie3_pins>;
+ pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
};
+
diff --git a/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
index cce30b0..c7177d4 100644
--- a/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-3.18/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
@@ -12,7 +12,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
-@@ -64,6 +64,16 @@
+@@ -71,6 +71,16 @@
bias-disable;
};
};
@@ -29,7 +29,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
gsbi@16300000 {
-@@ -201,5 +211,26 @@
+@@ -208,5 +218,26 @@
reg = <4>;
};
};
@@ -58,7 +58,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
-@@ -72,6 +72,14 @@
+@@ -75,6 +75,14 @@
bias-disable;
};
};
@@ -73,7 +73,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
gsbi2: gsbi@12480000 {
-@@ -222,5 +230,40 @@
+@@ -225,5 +233,40 @@
reg = <7>;
};
};
@@ -116,11 +116,10 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -638,5 +638,91 @@
- dr_mode = "host";
+@@ -657,5 +657,90 @@
};
};
-+
+
+ nss_common: syscon@03000000 {
+ compatible = "syscon";
+ reg = <0x03000000 0x0000FFFF>;
diff --git a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index e494d32..df96ad5 100644
--- a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -19,7 +19,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -27,7 +27,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -46,14 +46,14 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -64,7 +64,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -80,7 +80,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie3_pins: pcie3_pinmux {
++ pcie2_pins: pcie2_pinmux {
+ mux {
+ pins = "gpio63";
+ drive-strength = <2>;
@@ -99,21 +99,21 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie2: pci@1b900000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 63 0>;
-+ pinctrl-0 = <&pcie3_pins>;
++ pinctrl-0 = <&pcie2_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -125,11 +125,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
-+#include <include/dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Qualcomm IPQ8064";
-@@ -329,5 +331,128 @@
+@@ -329,5 +331,127 @@
#reset-cells = <1>;
};
@@ -255,6 +255,5 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+
+ status = "disabled";
+ };
-+
};
};
diff --git a/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch b/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
index 846f738..f327050 100644
--- a/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
+++ b/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
@@ -39,7 +39,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
gsbi@16300000 {
@@ -144,5 +154,33 @@
- pinctrl-0 = <&pcie2_pins>;
+ pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
};
+
@@ -99,7 +99,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
gsbi2: gsbi@12480000 {
@@ -173,5 +183,44 @@
- pinctrl-0 = <&pcie3_pins>;
+ pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
};
+
diff --git a/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
index 8019713..7f290d9 100644
--- a/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
@@ -116,10 +116,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -578,5 +578,91 @@
+@@ -577,5 +577,91 @@
+
status = "disabled";
};
-
++
+ nss_common: syscon@03000000 {
+ compatible = "syscon";
+ reg = <0x03000000 0x0000FFFF>;
@@ -205,6 +206,5 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+
+ status = "disabled";
+ };
-+
};
};
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