diff options
| author | Alexandros C. Couloumbis <alex@ozo.com> | 2010-09-04 17:00:55 +0000 |
|---|---|---|
| committer | Alexandros C. Couloumbis <alex@ozo.com> | 2010-09-04 17:00:55 +0000 |
| commit | f097df694456072541b89d3c0e08967c02cae868 (patch) | |
| tree | cc25b7d38b347b93c6a808bfc63bffa52e46027c /toolchain/gcc/patches | |
| parent | f1303bd07435374a025821098b3d5587e1cd9c2c (diff) | |
| download | mtk-20170518-f097df694456072541b89d3c0e08967c02cae868.zip mtk-20170518-f097df694456072541b89d3c0e08967c02cae868.tar.gz mtk-20170518-f097df694456072541b89d3c0e08967c02cae868.tar.bz2 | |
toolchain/gcc: fix -Os recursion on ARMv5 for gcc 4.5.0 & 4.5.1 (http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44392)
SVN-Revision: 22899
Diffstat (limited to 'toolchain/gcc/patches')
| -rw-r--r-- | toolchain/gcc/patches/4.5.0/002-fix_pr44392.patch | 70 | ||||
| -rw-r--r-- | toolchain/gcc/patches/4.5.1/002-fix_pr44392.patch | 70 |
2 files changed, 140 insertions, 0 deletions
diff --git a/toolchain/gcc/patches/4.5.0/002-fix_pr44392.patch b/toolchain/gcc/patches/4.5.0/002-fix_pr44392.patch new file mode 100644 index 0000000..4ad6c44 --- /dev/null +++ b/toolchain/gcc/patches/4.5.0/002-fix_pr44392.patch @@ -0,0 +1,70 @@ +>From d0557763b0713a4c006bd2405eede3924569cafd Mon Sep 17 00:00:00 2001 +From: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> +Date: Mon, 5 Jul 2010 11:28:49 +0100 +Subject: [PATCH 2/2] Fix PR44392 + +--- + gcc/config/arm/arm.md | 43 +++++++++++++++++++------------------------ + 1 files changed, 19 insertions(+), 24 deletions(-) + +diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md +index 2096ec6..f0348f3 100644 +--- a/gcc/config/arm/arm.md ++++ b/gcc/config/arm/arm.md +@@ -11318,34 +11318,29 @@ + (define_expand "bswapsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] +-"TARGET_EITHER" ++"TARGET_EITHER && (arm_arch6 || !optimize_size)" + " +- if (!arm_arch6) +- { +- if (!optimize_size) +- { +- rtx op2 = gen_reg_rtx (SImode); +- rtx op3 = gen_reg_rtx (SImode); ++ if (!arm_arch6) ++ { ++ rtx op2 = gen_reg_rtx (SImode); ++ rtx op3 = gen_reg_rtx (SImode); + +- if (TARGET_THUMB) +- { +- rtx op4 = gen_reg_rtx (SImode); +- rtx op5 = gen_reg_rtx (SImode); ++ if (TARGET_THUMB) ++ { ++ rtx op4 = gen_reg_rtx (SImode); ++ rtx op5 = gen_reg_rtx (SImode); + +- emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], +- op2, op3, op4, op5)); +- } +- else +- { +- emit_insn (gen_arm_legacy_rev (operands[0], operands[1], +- op2, op3)); +- } ++ emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], ++ op2, op3, op4, op5)); ++ } ++ else ++ { ++ emit_insn (gen_arm_legacy_rev (operands[0], operands[1], ++ op2, op3)); ++ } + +- DONE; +- } +- else +- FAIL; +- } ++ DONE; ++ } + " + ) + +-- +1.6.2 + diff --git a/toolchain/gcc/patches/4.5.1/002-fix_pr44392.patch b/toolchain/gcc/patches/4.5.1/002-fix_pr44392.patch new file mode 100644 index 0000000..4ad6c44 --- /dev/null +++ b/toolchain/gcc/patches/4.5.1/002-fix_pr44392.patch @@ -0,0 +1,70 @@ +>From d0557763b0713a4c006bd2405eede3924569cafd Mon Sep 17 00:00:00 2001 +From: Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> +Date: Mon, 5 Jul 2010 11:28:49 +0100 +Subject: [PATCH 2/2] Fix PR44392 + +--- + gcc/config/arm/arm.md | 43 +++++++++++++++++++------------------------ + 1 files changed, 19 insertions(+), 24 deletions(-) + +diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md +index 2096ec6..f0348f3 100644 +--- a/gcc/config/arm/arm.md ++++ b/gcc/config/arm/arm.md +@@ -11318,34 +11318,29 @@ + (define_expand "bswapsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (bswap:SI (match_operand:SI 1 "s_register_operand" "r")))] +-"TARGET_EITHER" ++"TARGET_EITHER && (arm_arch6 || !optimize_size)" + " +- if (!arm_arch6) +- { +- if (!optimize_size) +- { +- rtx op2 = gen_reg_rtx (SImode); +- rtx op3 = gen_reg_rtx (SImode); ++ if (!arm_arch6) ++ { ++ rtx op2 = gen_reg_rtx (SImode); ++ rtx op3 = gen_reg_rtx (SImode); + +- if (TARGET_THUMB) +- { +- rtx op4 = gen_reg_rtx (SImode); +- rtx op5 = gen_reg_rtx (SImode); ++ if (TARGET_THUMB) ++ { ++ rtx op4 = gen_reg_rtx (SImode); ++ rtx op5 = gen_reg_rtx (SImode); + +- emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], +- op2, op3, op4, op5)); +- } +- else +- { +- emit_insn (gen_arm_legacy_rev (operands[0], operands[1], +- op2, op3)); +- } ++ emit_insn (gen_thumb_legacy_rev (operands[0], operands[1], ++ op2, op3, op4, op5)); ++ } ++ else ++ { ++ emit_insn (gen_arm_legacy_rev (operands[0], operands[1], ++ op2, op3)); ++ } + +- DONE; +- } +- else +- FAIL; +- } ++ DONE; ++ } + " + ) + +-- +1.6.2 + |