diff options
3 files changed, 79 insertions, 0 deletions
diff --git a/target/linux/sunxi/image/Makefile b/target/linux/sunxi/image/Makefile index 04cddd8..313abef 100644 --- a/target/linux/sunxi/image/Makefile +++ b/target/linux/sunxi/image/Makefile @@ -12,6 +12,7 @@ BOARDS:= \ sun4i-a10-olinuxino-lime \ sun4i-a10-pcduino \ sun5i-a13-olinuxino \ + sun6i-a31-colombus \ sun7i-a20-cubieboard2 \ sun7i-a20-cubietruck \ sun7i-a20-olinuxino-micro diff --git a/target/linux/sunxi/patches-3.13/127-dt-sun6i-add-nodes-for-additional-cores.patch b/target/linux/sunxi/patches-3.13/127-dt-sun6i-add-nodes-for-additional-cores.patch new file mode 100644 index 0000000..a9f18ff --- /dev/null +++ b/target/linux/sunxi/patches-3.13/127-dt-sun6i-add-nodes-for-additional-cores.patch @@ -0,0 +1,36 @@ +From d3861805e84e1b54073e20dc499b9380b38bb7ab Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Sun, 3 Nov 2013 10:30:12 +0100 +Subject: [PATCH] ARM: sun6i: dt: Add IP needed to bring up the additional + cores + +Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm/boot/dts/sun6i-a31.dtsi | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi +index 97966b0..5256ad9 100644 +--- a/arch/arm/boot/dts/sun6i-a31.dtsi ++++ b/arch/arm/boot/dts/sun6i-a31.dtsi +@@ -322,5 +322,15 @@ + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; ++ ++ cpucfg@01f01c00 { ++ compatible = "allwinner,sun6i-a31-cpuconfig"; ++ reg = <0x01f01c00 0x300>; ++ }; ++ ++ prcm@01f01c00 { ++ compatible = "allwinner,sun6i-a31-prcm"; ++ reg = <0x01f01400 0x200>; ++ }; + }; + }; +-- +1.8.5.1 + diff --git a/target/linux/sunxi/patches-3.13/146-4-dt-sun6i-a31-add-hstimer.patch b/target/linux/sunxi/patches-3.13/146-4-dt-sun6i-a31-add-hstimer.patch new file mode 100644 index 0000000..d4f5593 --- /dev/null +++ b/target/linux/sunxi/patches-3.13/146-4-dt-sun6i-a31-add-hstimer.patch @@ -0,0 +1,42 @@ +From 28a9c5d93113cab73dd3a4b4a74a983151c08b9d Mon Sep 17 00:00:00 2001 +From: Maxime Ripard <maxime.ripard@free-electrons.com> +Date: Fri, 20 Dec 2013 22:41:09 +0100 +Subject: [PATCH] ARM: sun6i: a31: Add support for the High Speed Timers + +The Allwinner A31 has support for four high speed timers. Apart for the +number of timers (4 vs 2), it's basically the same logic than the high +speed timers found in the sun5i chips. + +Now that we have a driver to support it, we can enable them in the +device tree. + +Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> +--- + arch/arm/boot/dts/sun6i-a31.dtsi | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi +index ab6ea43..4b97449 100644 +--- a/arch/arm/boot/dts/sun6i-a31.dtsi ++++ b/arch/arm/boot/dts/sun6i-a31.dtsi +@@ -312,6 +312,17 @@ + status = "disabled"; + }; + ++ hstimer@01c60000 { ++ compatible = "allwinner,sun7i-a20-hstimer"; ++ reg = <0x01c60000 0x1000>; ++ interrupts = <0 51 4>, ++ <0 52 4>, ++ <0 53 4>, ++ <0 54 4>; ++ clocks = <&ahb1_gates 19>; ++ resets = <&ahb1_rst 19>; ++ }; ++ + gic: interrupt-controller@01c81000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c81000 0x1000>, +-- +1.8.5.1 + |