diff options
60 files changed, 8333 insertions, 3103 deletions
diff --git a/package/boot/uboot-lantiq/Makefile b/package/boot/uboot-lantiq/Makefile index b71b1e8..9bf6c01 100644 --- a/package/boot/uboot-lantiq/Makefile +++ b/package/boot/uboot-lantiq/Makefile @@ -8,7 +8,7 @@ include $(TOPDIR)/rules.mk PKG_NAME:=u-boot -PKG_VERSION:=2013.01 +PKG_VERSION:=2013.10 PKG_RELEASE:=1 PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION) @@ -16,7 +16,7 @@ PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.bz2 PKG_SOURCE_URL:= \ http://mirror2.openwrt.org/sources \ ftp://ftp.denx.de/pub/u-boot -PKG_MD5SUM:=e58a8a7f78972248190d83de0dc362ce +PKG_MD5SUM:=a076a044b64371edc52f7e562b13f6b2 PKG_TARGETS:=bin PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_NAME)-$(BUILD_VARIANT)/$(PKG_NAME)-$(PKG_VERSION) diff --git a/package/boot/uboot-lantiq/README b/package/boot/uboot-lantiq/README new file mode 100644 index 0000000..44ed2bb --- /dev/null +++ b/package/boot/uboot-lantiq/README @@ -0,0 +1,6 @@ +# How to refresh patches + +$ git clone git@github.com:danielschwierzeck/u-boot-lantiq.git +$ mkdir -p $OPENWRT_ROOT/packages/boot/uboot-lantiq/patches +$ cd u-boot-lantiq.git +$ git format-patch -p -k --no-renames --no-binary -o $OPENWRT_ROOT/package/boot/uboot-lantiq/patches v2013.10..u-boot-lantiq-v2013.10-openwrtN diff --git a/package/boot/uboot-lantiq/patches/0001-sf-fix-out-of-order-calls-for-spi_claim_bus-and-spi_.patch b/package/boot/uboot-lantiq/patches/0001-sf-fix-out-of-order-calls-for-spi_claim_bus-and-spi_.patch new file mode 100644 index 0000000..b5d7ac8 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0001-sf-fix-out-of-order-calls-for-spi_claim_bus-and-spi_.patch @@ -0,0 +1,175 @@ +From 909840ef844013379e5ec399c1e76c65d1a6eb1d Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sat, 12 Oct 2013 21:09:47 +0200 +Subject: sf: fix out-of-order calls for spi_claim_bus and spi_release_bus + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c +index 108665f..d34747b 100644 +--- a/drivers/mtd/spi/sf_ops.c ++++ b/drivers/mtd/spi/sf_ops.c +@@ -132,12 +132,6 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, + if (buf == NULL) + timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT; + +- ret = spi_claim_bus(flash->spi); +- if (ret) { +- debug("SF: unable to claim SPI bus\n"); +- return ret; +- } +- + ret = spi_flash_cmd_write_enable(flash); + if (ret < 0) { + debug("SF: enabling write failed\n"); +@@ -158,8 +152,6 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, + return ret; + } + +- spi_release_bus(spi); +- + return ret; + } + +@@ -175,12 +167,18 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + return -1; + } + ++ ret = spi_claim_bus(flash->spi); ++ if (ret) { ++ debug("SF: unable to claim SPI bus\n"); ++ return ret; ++ } ++ + cmd[0] = flash->erase_cmd; + while (len) { + #ifdef CONFIG_SPI_FLASH_BAR + ret = spi_flash_bank(flash, offset); + if (ret < 0) +- return ret; ++ goto done; + #endif + spi_flash_addr(offset, cmd); + +@@ -190,13 +188,16 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); + if (ret < 0) { + debug("SF: erase failed\n"); +- break; ++ goto done; + } + + offset += erase_size; + len -= erase_size; + } + ++done: ++ spi_release_bus(flash->spi); ++ + return ret; + } + +@@ -208,6 +209,12 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + u8 cmd[4]; + int ret = -1; + ++ ret = spi_claim_bus(flash->spi); ++ if (ret) { ++ debug("SF: unable to claim SPI bus\n"); ++ return ret; ++ } ++ + page_size = flash->page_size; + + cmd[0] = CMD_PAGE_PROGRAM; +@@ -215,7 +222,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + #ifdef CONFIG_SPI_FLASH_BAR + ret = spi_flash_bank(flash, offset); + if (ret < 0) +- return ret; ++ goto done; + #endif + byte_addr = offset % page_size; + chunk_len = min(len - actual, page_size - byte_addr); +@@ -232,12 +239,15 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: write failed\n"); +- break; ++ goto done; + } + + offset += chunk_len; + } + ++done: ++ spi_release_bus(flash->spi); ++ + return ret; + } + +@@ -247,20 +257,12 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + struct spi_slave *spi = flash->spi; + int ret; + +- ret = spi_claim_bus(flash->spi); +- if (ret) { +- debug("SF: unable to claim SPI bus\n"); +- return ret; +- } +- + ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len); + if (ret < 0) { + debug("SF: read cmd failed\n"); + return ret; + } + +- spi_release_bus(spi); +- + return ret; + } + +@@ -271,6 +273,12 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + u32 remain_len, read_len; + int ret = -1; + ++ ret = spi_claim_bus(flash->spi); ++ if (ret) { ++ debug("SF: unable to claim SPI bus\n"); ++ return ret; ++ } ++ + /* Handle memory-mapped SPI */ + if (flash->memory_map) { + spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP); +@@ -289,7 +297,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + ret = spi_flash_cmd_bankaddr_write(flash, bank_sel); + if (ret) { + debug("SF: fail to set bank%d\n", bank_sel); +- return ret; ++ goto done; + } + #endif + remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; +@@ -304,7 +312,7 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + data, read_len); + if (ret < 0) { + debug("SF: read failed\n"); +- break; ++ goto done; + } + + offset += read_len; +@@ -312,6 +320,9 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + data += read_len; + } + ++done: ++ spi_release_bus(flash->spi); ++ + return ret; + } + +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0002-sf-consistently-use-debug-for-warning-error-messages.patch b/package/boot/uboot-lantiq/patches/0002-sf-consistently-use-debug-for-warning-error-messages.patch new file mode 100644 index 0000000..597c2c1 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0002-sf-consistently-use-debug-for-warning-error-messages.patch @@ -0,0 +1,54 @@ +From bb7df8c6ff30be3786483767d3afb0e77a69a640 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sat, 12 Oct 2013 21:21:18 +0200 +Subject: sf: consistently use debug() for warning/error messages + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index 5eb8ffe..04356f1 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -176,8 +176,8 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, + } + + if (i == ARRAY_SIZE(spi_flash_params_table)) { +- printf("SF: Unsupported flash IDs: "); +- printf("manuf %02x, jedec %04x, ext_jedec %04x\n", ++ debug("SF: Unsupported flash IDs: "); ++ debug("manuf %02x, jedec %04x, ext_jedec %04x\n", + idcode[0], jedec, ext_jedec); + return NULL; + } +@@ -296,7 +296,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + /* Setup spi_slave */ + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { +- printf("SF: Failed to set up slave\n"); ++ debug("SF: Failed to set up slave\n"); + return NULL; + } + +@@ -310,7 +310,7 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + /* Read the ID codes */ + ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); + if (ret) { +- printf("SF: Failed to get idcodes\n"); ++ debug("SF: Failed to get idcodes\n"); + goto err_read_id; + } + +@@ -341,8 +341,8 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + #endif + #ifndef CONFIG_SPI_FLASH_BAR + if (flash->size > SPI_FLASH_16MB_BOUN) { +- puts("SF: Warning - Only lower 16MiB accessible,"); +- puts(" Full access #define CONFIG_SPI_FLASH_BAR\n"); ++ debug("SF: Warning - Only lower 16MiB accessible,"); ++ debug(" Full access #define CONFIG_SPI_FLASH_BAR\n"); + } + #endif + +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0002-sf-handle-CONFIG_MANUAL_RELOC.patch b/package/boot/uboot-lantiq/patches/0002-sf-handle-CONFIG_MANUAL_RELOC.patch deleted file mode 100644 index 63a21af..0000000 --- a/package/boot/uboot-lantiq/patches/0002-sf-handle-CONFIG_MANUAL_RELOC.patch +++ /dev/null @@ -1,46 +0,0 @@ -From 60e8a35f0efa5a7e5d797a3f239971c84061ef11 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Tue, 6 Nov 2012 21:39:47 +0100 -Subject: sf: handle CONFIG_MANUAL_RELOC - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spi_flash.c -+++ b/drivers/mtd/spi/spi_flash.c -@@ -293,7 +293,7 @@ int spi_flash_cmd_write_status(struct sp - */ - #define IDCODE_CONT_LEN 0 - #define IDCODE_PART_LEN 5 --static const struct { -+static struct { - const u8 shift; - const u8 idcode; - struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); -@@ -335,6 +335,10 @@ static const struct { - }; - #define IDCODE_LEN (IDCODE_CONT_LEN + IDCODE_PART_LEN) - -+#ifdef CONFIG_NEEDS_MANUAL_RELOC -+DECLARE_GLOBAL_DATA_PTR; -+#endif -+ - struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode) - { -@@ -342,6 +346,16 @@ struct spi_flash *spi_flash_probe(unsign - struct spi_flash *flash = NULL; - int ret, i, shift; - u8 idcode[IDCODE_LEN], *idp; -+#ifdef CONFIG_NEEDS_MANUAL_RELOC -+ static int relocated; -+ -+ if (!relocated) { -+ for (i = 0; i < ARRAY_SIZE(flashes); i++) -+ flashes[i].probe += gd->reloc_off; -+ -+ relocated = 1; -+ } -+#endif - - spi = spi_setup_slave(bus, cs, max_hz, spi_mode); - if (!spi) { diff --git a/package/boot/uboot-lantiq/patches/0003-sf-factor-out-malloc-from-SPI-flash-drivers.patch b/package/boot/uboot-lantiq/patches/0003-sf-factor-out-malloc-from-SPI-flash-drivers.patch deleted file mode 100644 index 7f44675..0000000 --- a/package/boot/uboot-lantiq/patches/0003-sf-factor-out-malloc-from-SPI-flash-drivers.patch +++ /dev/null @@ -1,719 +0,0 @@ -From 73d127565b5a4b19bcaacabc505689ee039f16fd Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Sun, 11 Nov 2012 03:11:38 +0100 -Subject: sf: factor out malloc from SPI flash drivers - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/atmel.c -+++ b/drivers/mtd/spi/atmel.c -@@ -40,18 +40,6 @@ struct atmel_spi_flash_params { - const char *name; - }; - --/* spi_flash needs to be first so upper layers can free() it */ --struct atmel_spi_flash { -- struct spi_flash flash; -- const struct atmel_spi_flash_params *params; --}; -- --static inline struct atmel_spi_flash * --to_atmel_spi_flash(struct spi_flash *flash) --{ -- return container_of(flash, struct atmel_spi_flash, flash); --} -- - static const struct atmel_spi_flash_params atmel_spi_flash_table[] = { - { - .idcode1 = 0x22, -@@ -156,7 +144,8 @@ static int at45_wait_ready(struct spi_fl - * Assemble the address part of a command for AT45 devices in - * non-power-of-two page size mode. - */ --static void at45_build_address(struct atmel_spi_flash *asf, u8 *cmd, u32 offset) -+static void at45_build_address(const struct atmel_spi_flash_params *params, -+ u8 *cmd, u32 offset) - { - unsigned long page_addr; - unsigned long byte_addr; -@@ -167,7 +156,7 @@ static void at45_build_address(struct at - * The "extra" space per page is the power-of-two page size - * divided by 32. - */ -- page_shift = asf->params->l2_page_size; -+ page_shift = params->l2_page_size; - page_size = (1 << page_shift) + (1 << (page_shift - 5)); - page_shift++; - page_addr = offset / page_size; -@@ -181,11 +170,11 @@ static void at45_build_address(struct at - static int dataflash_read_fast_at45(struct spi_flash *flash, - u32 offset, size_t len, void *buf) - { -- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); -+ const struct atmel_spi_flash_params *params = flash->priv; - u8 cmd[5]; - - cmd[0] = CMD_READ_ARRAY_FAST; -- at45_build_address(asf, cmd + 1, offset); -+ at45_build_address(params, cmd + 1, offset); - cmd[4] = 0x00; - - return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); -@@ -197,7 +186,7 @@ static int dataflash_read_fast_at45(stru - static int dataflash_write_p2(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) - { -- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); -+ const struct atmel_spi_flash_params *params = flash->priv; - unsigned long page_size; - u32 addr = offset; - size_t chunk_len; -@@ -211,7 +200,7 @@ static int dataflash_write_p2(struct spi - * the other is being programmed into main memory. - */ - -- page_size = (1 << asf->params->l2_page_size); -+ page_size = (1 << params->l2_page_size); - - ret = spi_claim_bus(flash->spi); - if (ret) { -@@ -263,7 +252,7 @@ out: - static int dataflash_write_at45(struct spi_flash *flash, - u32 offset, size_t len, const void *buf) - { -- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); -+ const struct atmel_spi_flash_params *params = flash->priv; - unsigned long page_addr; - unsigned long byte_addr; - unsigned long page_size; -@@ -279,7 +268,7 @@ static int dataflash_write_at45(struct s - * the other is being programmed into main memory. - */ - -- page_shift = asf->params->l2_page_size; -+ page_shift = params->l2_page_size; - page_size = (1 << page_shift) + (1 << (page_shift - 5)); - page_shift++; - page_addr = offset / page_size; -@@ -338,7 +327,7 @@ out: - */ - static int dataflash_erase_p2(struct spi_flash *flash, u32 offset, size_t len) - { -- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); -+ const struct atmel_spi_flash_params *params = flash->priv; - unsigned long page_size; - - size_t actual; -@@ -351,7 +340,7 @@ static int dataflash_erase_p2(struct spi - * when possible. - */ - -- page_size = (1 << asf->params->l2_page_size); -+ page_size = (1 << params->l2_page_size); - - if (offset % page_size || len % page_size) { - debug("SF: Erase offset/length not multiple of page size\n"); -@@ -397,7 +386,7 @@ out: - - static int dataflash_erase_at45(struct spi_flash *flash, u32 offset, size_t len) - { -- struct atmel_spi_flash *asf = to_atmel_spi_flash(flash); -+ const struct atmel_spi_flash_params *params = flash->priv; - unsigned long page_addr; - unsigned long page_size; - unsigned int page_shift; -@@ -411,7 +400,7 @@ static int dataflash_erase_at45(struct s - * when possible. - */ - -- page_shift = asf->params->l2_page_size; -+ page_shift = params->l2_page_size; - page_size = (1 << page_shift) + (1 << (page_shift - 5)); - page_shift++; - page_addr = offset / page_size; -@@ -458,12 +447,12 @@ out: - return ret; - } - --struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode) -+int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode) - { - const struct atmel_spi_flash_params *params; -+ struct spi_slave *spi = flash->spi; - unsigned page_size; - unsigned int family; -- struct atmel_spi_flash *asf; - unsigned int i; - int ret; - u8 status; -@@ -477,18 +466,11 @@ struct spi_flash *spi_flash_probe_atmel( - if (i == ARRAY_SIZE(atmel_spi_flash_table)) { - debug("SF: Unsupported DataFlash ID %02x\n", - idcode[1]); -- return NULL; -- } -- -- asf = malloc(sizeof(struct atmel_spi_flash)); -- if (!asf) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -+ return 0; - } - -- asf->params = params; -- asf->flash.spi = spi; -- asf->flash.name = params->name; -+ flash->priv = (void *)params; -+ flash->name = params->name; - - /* Assuming power-of-two page size initially. */ - page_size = 1 << params->l2_page_size; -@@ -503,48 +485,44 @@ struct spi_flash *spi_flash_probe_atmel( - */ - ret = spi_flash_cmd(spi, CMD_AT45_READ_STATUS, &status, 1); - if (ret) -- goto err; -+ return -1; - - debug("SF: AT45 status register: %02x\n", status); - - if (!(status & AT45_STATUS_P2_PAGE_SIZE)) { -- asf->flash.read = dataflash_read_fast_at45; -- asf->flash.write = dataflash_write_at45; -- asf->flash.erase = dataflash_erase_at45; -+ flash->read = dataflash_read_fast_at45; -+ flash->write = dataflash_write_at45; -+ flash->erase = dataflash_erase_at45; - page_size += 1 << (params->l2_page_size - 5); - } else { -- asf->flash.read = spi_flash_cmd_read_fast; -- asf->flash.write = dataflash_write_p2; -- asf->flash.erase = dataflash_erase_p2; -+ flash->read = spi_flash_cmd_read_fast; -+ flash->write = dataflash_write_p2; -+ flash->erase = dataflash_erase_p2; - } - -- asf->flash.page_size = page_size; -- asf->flash.sector_size = page_size; -+ flash->page_size = page_size; -+ flash->sector_size = page_size; - break; - - case DF_FAMILY_AT26F: - case DF_FAMILY_AT26DF: -- asf->flash.read = spi_flash_cmd_read_fast; -- asf->flash.write = spi_flash_cmd_write_multi; -- asf->flash.erase = spi_flash_cmd_erase; -- asf->flash.page_size = page_size; -- asf->flash.sector_size = 4096; -+ flash->read = spi_flash_cmd_read_fast; -+ flash->write = spi_flash_cmd_write_multi; -+ flash->erase = spi_flash_cmd_erase; -+ flash->page_size = page_size; -+ flash->sector_size = 4096; - /* clear SPRL# bit for locked flash */ -- spi_flash_cmd_write_status(&asf->flash, 0); -+ spi_flash_cmd_write_status(flash, 0); - break; - - default: - debug("SF: Unsupported DataFlash family %u\n", family); -- goto err; -+ return -1; - } - -- asf->flash.size = page_size * params->pages_per_block -+ flash->size = page_size * params->pages_per_block - * params->blocks_per_sector - * params->nr_sectors; - -- return &asf->flash; -- --err: -- free(asf); -- return NULL; -+ return 1; - } ---- a/drivers/mtd/spi/eon.c -+++ b/drivers/mtd/spi/eon.c -@@ -29,10 +29,9 @@ static const struct eon_spi_flash_params - }, - }; - --struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode) -+int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode) - { - const struct eon_spi_flash_params *params; -- struct spi_flash *flash; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { -@@ -43,16 +42,10 @@ struct spi_flash *spi_flash_probe_eon(st - - if (i == ARRAY_SIZE(eon_spi_flash_table)) { - debug("SF: Unsupported EON ID %02x\n", idcode[1]); -- return NULL; -+ return 0; - } - -- flash = malloc(sizeof(*flash)); -- if (!flash) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -- } -- -- flash->spi = spi; -+ flash->priv = (void *)params; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; -@@ -63,5 +56,5 @@ struct spi_flash *spi_flash_probe_eon(st - flash->size = 256 * 16 - * params->nr_sectors; - -- return flash; -+ return 1; - } ---- a/drivers/mtd/spi/macronix.c -+++ b/drivers/mtd/spi/macronix.c -@@ -79,10 +79,9 @@ static const struct macronix_spi_flash_p - }, - }; - --struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode) -+int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode) - { - const struct macronix_spi_flash_params *params; -- struct spi_flash *flash; - unsigned int i; - u16 id = idcode[2] | idcode[1] << 8; - -@@ -94,16 +93,10 @@ struct spi_flash *spi_flash_probe_macron - - if (i == ARRAY_SIZE(macronix_spi_flash_table)) { - debug("SF: Unsupported Macronix ID %04x\n", id); -- return NULL; -+ return 0; - } - -- flash = malloc(sizeof(*flash)); -- if (!flash) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -- } -- -- flash->spi = spi; -+ flash->priv = (void *)params; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; -@@ -116,5 +109,5 @@ struct spi_flash *spi_flash_probe_macron - /* Clear BP# bits for read-only flash */ - spi_flash_cmd_write_status(flash, 0); - -- return flash; -+ return 1; - } ---- a/drivers/mtd/spi/ramtron.c -+++ b/drivers/mtd/spi/ramtron.c -@@ -69,17 +69,6 @@ struct ramtron_spi_fram_params { - const char *name; /* name for display and/or matching */ - }; - --struct ramtron_spi_fram { -- struct spi_flash flash; -- const struct ramtron_spi_fram_params *params; --}; -- --static inline struct ramtron_spi_fram *to_ramtron_spi_fram(struct spi_flash -- *flash) --{ -- return container_of(flash, struct ramtron_spi_fram, flash); --} -- - /* - * table describing supported FRAM chips: - * chips without RDID command must have the values 0xff for id1 and id2 -@@ -155,18 +144,18 @@ static const struct ramtron_spi_fram_par - static int ramtron_common(struct spi_flash *flash, - u32 offset, size_t len, void *buf, u8 command) - { -- struct ramtron_spi_fram *sn = to_ramtron_spi_fram(flash); -+ const struct ramtron_spi_fram_params *params = flash->priv; - u8 cmd[4]; - int cmd_len; - int ret; - -- if (sn->params->addr_len == 3 && sn->params->merge_cmd == 0) { -+ if (params->addr_len == 3 && params->merge_cmd == 0) { - cmd[0] = command; - cmd[1] = offset >> 16; - cmd[2] = offset >> 8; - cmd[3] = offset; - cmd_len = 4; -- } else if (sn->params->addr_len == 2 && sn->params->merge_cmd == 0) { -+ } else if (params->addr_len == 2 && params->merge_cmd == 0) { - cmd[0] = command; - cmd[1] = offset >> 8; - cmd[2] = offset; -@@ -230,10 +219,9 @@ static int ramtron_erase(struct spi_flas - * nore: we are called here with idcode pointing to the first non-0x7f byte - * already! - */ --struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode) -+int spi_fram_probe_ramtron(struct spi_flash *flash, u8 *idcode) - { - const struct ramtron_spi_fram_params *params; -- struct ramtron_spi_fram *sn; - unsigned int i; - #ifdef CONFIG_SPI_FRAM_RAMTRON_NON_JEDEC - int ret; -@@ -259,11 +247,11 @@ struct spi_flash *spi_fram_probe_ramtron - */ - ret = spi_flash_cmd(spi, CMD_READ_STATUS, &sr, 1); - if (ret) -- return NULL; -+ return 0; - - /* Bits 5,4,0 are fixed 0 for all devices */ - if ((sr & 0x31) != 0x00) -- return NULL; -+ return 0; - /* now find the device */ - for (i = 0; i < ARRAY_SIZE(ramtron_spi_fram_table); i++) { - params = &ramtron_spi_fram_table[i]; -@@ -281,23 +269,16 @@ struct spi_flash *spi_fram_probe_ramtron - /* arriving here means no method has found a device we can handle */ - debug("SF/ramtron: unsupported device id0=%02x id1=%02x id2=%02x\n", - idcode[0], idcode[1], idcode[2]); -- return NULL; -+ return 0; - - found: -- sn = malloc(sizeof(*sn)); -- if (!sn) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -- } -+ flash->priv = (void *)params; -+ flash->name = params->name; - -- sn->params = params; -- sn->flash.spi = spi; -- sn->flash.name = params->name; -- -- sn->flash.write = ramtron_write; -- sn->flash.read = ramtron_read; -- sn->flash.erase = ramtron_erase; -- sn->flash.size = params->size; -+ flash->write = ramtron_write; -+ flash->read = ramtron_read; -+ flash->erase = ramtron_erase; -+ flash->size = params->size; - -- return &sn->flash; -+ return 1; - } ---- a/drivers/mtd/spi/spansion.c -+++ b/drivers/mtd/spi/spansion.c -@@ -105,10 +105,9 @@ static const struct spansion_spi_flash_p - }, - }; - --struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode) -+int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode) - { - const struct spansion_spi_flash_params *params; -- struct spi_flash *flash; - unsigned int i; - unsigned short jedec, ext_jedec; - -@@ -125,16 +124,10 @@ struct spi_flash *spi_flash_probe_spansi - - if (i == ARRAY_SIZE(spansion_spi_flash_table)) { - debug("SF: Unsupported SPANSION ID %04x %04x\n", jedec, ext_jedec); -- return NULL; -+ return 0; - } - -- flash = malloc(sizeof(*flash)); -- if (!flash) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -- } -- -- flash->spi = spi; -+ flash->priv = (void *)params; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; -@@ -144,5 +137,5 @@ struct spi_flash *spi_flash_probe_spansi - flash->sector_size = 256 * params->pages_per_sector; - flash->size = flash->sector_size * params->nr_sectors; - -- return flash; -+ return 1; - } ---- a/drivers/mtd/spi/spi_flash.c -+++ b/drivers/mtd/spi/spi_flash.c -@@ -296,7 +296,7 @@ int spi_flash_cmd_write_status(struct sp - static struct { - const u8 shift; - const u8 idcode; -- struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode); -+ int (*probe) (struct spi_flash *flash, u8 *idcode); - } flashes[] = { - /* Keep it sorted by define name */ - #ifdef CONFIG_SPI_FLASH_ATMEL -@@ -343,7 +343,7 @@ struct spi_flash *spi_flash_probe(unsign - unsigned int max_hz, unsigned int spi_mode) - { - struct spi_slave *spi; -- struct spi_flash *flash = NULL; -+ struct spi_flash *flash; - int ret, i, shift; - u8 idcode[IDCODE_LEN], *idp; - #ifdef CONFIG_NEEDS_MANUAL_RELOC -@@ -379,6 +379,15 @@ struct spi_flash *spi_flash_probe(unsign - print_buffer(0, idcode, 1, sizeof(idcode), 0); - #endif - -+ flash = malloc(sizeof(*flash)); -+ if (!flash) { -+ debug("SF: failed to alloc memory\n"); -+ goto err_malloc; -+ } -+ -+ memset(flash, 0, sizeof(*flash)); -+ flash->spi = spi; -+ - /* count the number of continuation bytes */ - for (shift = 0, idp = idcode; - shift < IDCODE_CONT_LEN && *idp == 0x7f; -@@ -389,12 +398,12 @@ struct spi_flash *spi_flash_probe(unsign - for (i = 0; i < ARRAY_SIZE(flashes); ++i) - if (flashes[i].shift == shift && flashes[i].idcode == *idp) { - /* we have a match, call probe */ -- flash = flashes[i].probe(spi, idp); -- if (flash) -+ ret = flashes[i].probe(flash, idp); -+ if (ret) - break; - } - -- if (!flash) { -+ if (ret <= 0) { - printf("SF: Unsupported manufacturer %02x\n", *idp); - goto err_manufacturer_probe; - } -@@ -408,6 +417,8 @@ struct spi_flash *spi_flash_probe(unsign - return flash; - - err_manufacturer_probe: -+ free(flash); -+err_malloc: - err_read_id: - spi_release_bus(spi); - err_claim_bus: ---- a/drivers/mtd/spi/spi_flash_internal.h -+++ b/drivers/mtd/spi/spi_flash_internal.h -@@ -98,11 +98,11 @@ int spi_flash_cmd_wait_ready(struct spi_ - int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len); - - /* Manufacturer-specific probe functions */ --struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); --struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); --struct spi_flash *spi_flash_probe_eon(struct spi_slave *spi, u8 *idcode); --struct spi_flash *spi_flash_probe_macronix(struct spi_slave *spi, u8 *idcode); --struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode); --struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); --struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); --struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode); -+int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode); -+int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode); -+int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode); -+int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode); -+int spi_flash_probe_sst(struct spi_flash *flash, u8 *idcode); -+int spi_flash_probe_stmicro(struct spi_flash *flash, u8 *idcode); -+int spi_flash_probe_winbond(struct spi_flash *flash, u8 *idcode); -+int spi_fram_probe_ramtron(struct spi_flash *flash, u8 *idcode); ---- a/drivers/mtd/spi/sst.c -+++ b/drivers/mtd/spi/sst.c -@@ -39,11 +39,6 @@ struct sst_spi_flash_params { - const char *name; - }; - --struct sst_spi_flash { -- struct spi_flash flash; -- const struct sst_spi_flash_params *params; --}; -- - static const struct sst_spi_flash_params sst_spi_flash_table[] = { - { - .idcode1 = 0x8d, -@@ -185,11 +180,9 @@ sst_write_wp(struct spi_flash *flash, u3 - return ret; - } - --struct spi_flash * --spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode) -+int spi_flash_probe_sst(struct spi_flash *flash, u8 *idcode) - { - const struct sst_spi_flash_params *params; -- struct sst_spi_flash *stm; - size_t i; - - for (i = 0; i < ARRAY_SIZE(sst_spi_flash_table); ++i) { -@@ -200,31 +193,24 @@ spi_flash_probe_sst(struct spi_slave *sp - - if (i == ARRAY_SIZE(sst_spi_flash_table)) { - debug("SF: Unsupported SST ID %02x\n", idcode[1]); -- return NULL; -- } -- -- stm = malloc(sizeof(*stm)); -- if (!stm) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -+ return 0; - } - -- stm->params = params; -- stm->flash.spi = spi; -- stm->flash.name = params->name; -+ flash->priv = (void *)params; -+ flash->name = params->name; - -- if (stm->params->flags & SST_FEAT_WP) -- stm->flash.write = sst_write_wp; -+ if (params->flags & SST_FEAT_WP) -+ flash->write = sst_write_wp; - else -- stm->flash.write = spi_flash_cmd_write_multi; -- stm->flash.erase = spi_flash_cmd_erase; -- stm->flash.read = spi_flash_cmd_read_fast; -- stm->flash.page_size = 256; -- stm->flash.sector_size = 4096; -- stm->flash.size = stm->flash.sector_size * params->nr_sectors; -+ flash->write = spi_flash_cmd_write_multi; -+ flash->erase = spi_flash_cmd_erase; -+ flash->read = spi_flash_cmd_read_fast; -+ flash->page_size = 256; -+ flash->sector_size = 4096; -+ flash->size = flash->sector_size * params->nr_sectors; - - /* Flash powers up read-only, so clear BP# bits */ -- spi_flash_cmd_write_status(&stm->flash, 0); -+ spi_flash_cmd_write_status(flash, 0); - -- return &stm->flash; -+ return 1; - } ---- a/drivers/mtd/spi/stmicro.c -+++ b/drivers/mtd/spi/stmicro.c -@@ -112,10 +112,10 @@ static const struct stmicro_spi_flash_pa - }, - }; - --struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) -+int spi_flash_probe_stmicro(struct spi_flash *flash, u8 * idcode) - { - const struct stmicro_spi_flash_params *params; -- struct spi_flash *flash; -+ struct spi_slave *spi = flash->spi; - unsigned int i; - u16 id; - -@@ -123,13 +123,13 @@ struct spi_flash *spi_flash_probe_stmicr - i = spi_flash_cmd(spi, CMD_M25PXX_RES, - idcode, 4); - if (i) -- return NULL; -+ return 0; - if ((idcode[3] & 0xf0) == 0x10) { - idcode[0] = 0x20; - idcode[1] = 0x20; - idcode[2] = idcode[3] + 1; - } else -- return NULL; -+ return 0; - } - - id = ((idcode[1] << 8) | idcode[2]); -@@ -143,16 +143,10 @@ struct spi_flash *spi_flash_probe_stmicr - - if (i == ARRAY_SIZE(stmicro_spi_flash_table)) { - debug("SF: Unsupported STMicro ID %04x\n", id); -- return NULL; -+ return 0; - } - -- flash = malloc(sizeof(*flash)); -- if (!flash) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -- } -- -- flash->spi = spi; -+ flash->priv = (void *)params; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; -@@ -162,5 +156,5 @@ struct spi_flash *spi_flash_probe_stmicr - flash->sector_size = 256 * params->pages_per_sector; - flash->size = flash->sector_size * params->nr_sectors; - -- return flash; -+ return 1; - } ---- a/drivers/mtd/spi/winbond.c -+++ b/drivers/mtd/spi/winbond.c -@@ -69,10 +69,9 @@ static const struct winbond_spi_flash_pa - }, - }; - --struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) -+int spi_flash_probe_winbond(struct spi_flash *flash, u8 *idcode) - { - const struct winbond_spi_flash_params *params; -- struct spi_flash *flash; - unsigned int i; - - for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { -@@ -84,16 +83,10 @@ struct spi_flash *spi_flash_probe_winbon - if (i == ARRAY_SIZE(winbond_spi_flash_table)) { - debug("SF: Unsupported Winbond ID %02x%02x\n", - idcode[1], idcode[2]); -- return NULL; -+ return 0; - } - -- flash = malloc(sizeof(*flash)); -- if (!flash) { -- debug("SF: Failed to allocate memory\n"); -- return NULL; -- } -- -- flash->spi = spi; -+ flash->priv = (void *)params; - flash->name = params->name; - - flash->write = spi_flash_cmd_write_multi; -@@ -103,5 +96,5 @@ struct spi_flash *spi_flash_probe_winbon - flash->sector_size = 4096; - flash->size = 4096 * 16 * params->nr_blocks; - -- return flash; -+ return 1; - } ---- a/include/spi_flash.h -+++ b/include/spi_flash.h -@@ -31,6 +31,7 @@ struct spi_flash { - struct spi_slave *spi; - - const char *name; -+ void *priv; - - /* Total flash size */ - u32 size; diff --git a/package/boot/uboot-lantiq/patches/0003-sf-move-malloc-of-spi_flash-to-spi_flash_probe.patch b/package/boot/uboot-lantiq/patches/0003-sf-move-malloc-of-spi_flash-to-spi_flash_probe.patch new file mode 100644 index 0000000..819eef8 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0003-sf-move-malloc-of-spi_flash-to-spi_flash_probe.patch @@ -0,0 +1,115 @@ +From 36b7400465fe2339f1c78274b3fd258ade3a4c00 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sat, 12 Oct 2013 21:30:07 +0200 +Subject: sf: move malloc of spi_flash to spi_flash_probe() + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index 04356f1..2bba10c 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -153,11 +153,10 @@ static const struct spi_flash_params spi_flash_params_table[] = { + */ + }; + +-static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, ++static int spi_flash_validate_params(struct spi_flash *flash, + u8 *idcode) + { + const struct spi_flash_params *params; +- struct spi_flash *flash; + int i; + u16 jedec = idcode[1] << 8 | idcode[2]; + u16 ext_jedec = idcode[3] << 8 | idcode[4]; +@@ -179,20 +178,12 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, + debug("SF: Unsupported flash IDs: "); + debug("manuf %02x, jedec %04x, ext_jedec %04x\n", + idcode[0], jedec, ext_jedec); +- return NULL; +- } +- +- flash = malloc(sizeof(*flash)); +- if (!flash) { +- debug("SF: Failed to allocate spi_flash\n"); +- return NULL; ++ return -1; + } +- memset(flash, '\0', sizeof(*flash)); + + /* Assign spi data */ +- flash->spi = spi; + flash->name = params->name; +- flash->memory_map = spi->memory_map; ++ flash->memory_map = flash->spi->memory_map; + + /* Assign spi_flash ops */ + flash->write = spi_flash_cmd_write_ops; +@@ -239,7 +230,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, + if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1, + &curr_bank, 1)) { + debug("SF: fail to read bank addr register\n"); +- return NULL; ++ return -1; + } + flash->bank_curr = curr_bank; + } else { +@@ -254,7 +245,7 @@ static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi, + spi_flash_cmd_write_status(flash, 0); + #endif + +- return flash; ++ return 0; + } + + #ifdef CONFIG_OF_CONTROL +@@ -289,15 +280,22 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode) + { + struct spi_slave *spi; +- struct spi_flash *flash = NULL; ++ struct spi_flash *flash; + u8 idcode[5]; + int ret; + ++ flash = malloc(sizeof(*flash)); ++ if (!flash) { ++ debug("SF: Failed to allocate spi_flash\n"); ++ return NULL; ++ } ++ memset(flash, 0, sizeof(*flash)); ++ + /* Setup spi_slave */ + spi = spi_setup_slave(bus, cs, max_hz, spi_mode); + if (!spi) { + debug("SF: Failed to set up slave\n"); +- return NULL; ++ goto err_setup; + } + + /* Claim spi bus */ +@@ -320,8 +318,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + #endif + + /* Validate params from spi_flash_params table */ +- flash = spi_flash_validate_params(spi, idcode); +- if (!flash) ++ flash->spi = spi; ++ ret = spi_flash_validate_params(flash, idcode); ++ if (ret) + goto err_read_id; + + #ifdef CONFIG_OF_CONTROL +@@ -355,6 +354,9 @@ err_read_id: + spi_release_bus(spi); + err_claim_bus: + spi_free_slave(spi); ++err_setup: ++ free(flash); ++ + return NULL; + } + +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0004-sf-add-malloc-free-probe-functions-dedicated-for-SPL.patch b/package/boot/uboot-lantiq/patches/0004-sf-add-malloc-free-probe-functions-dedicated-for-SPL.patch deleted file mode 100644 index 7a1ef3b..0000000 --- a/package/boot/uboot-lantiq/patches/0004-sf-add-malloc-free-probe-functions-dedicated-for-SPL.patch +++ /dev/null @@ -1,131 +0,0 @@ -From f9ab44c271fbd82a5702b6ba067fa90e33a30089 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 15:29:27 +0100 -Subject: sf: add malloc-free probe functions dedicated for SPL - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spi_flash.c -+++ b/drivers/mtd/spi/spi_flash.c -@@ -339,11 +339,11 @@ static struct { - DECLARE_GLOBAL_DATA_PTR; - #endif - --struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, -- unsigned int max_hz, unsigned int spi_mode) -+int spi_flash_probe_spl(struct spi_flash *flash, unsigned int bus, -+ unsigned int cs, unsigned int max_hz, -+ unsigned int spi_mode) - { - struct spi_slave *spi; -- struct spi_flash *flash; - int ret, i, shift; - u8 idcode[IDCODE_LEN], *idp; - #ifdef CONFIG_NEEDS_MANUAL_RELOC -@@ -359,8 +359,8 @@ struct spi_flash *spi_flash_probe(unsign - - spi = spi_setup_slave(bus, cs, max_hz, spi_mode); - if (!spi) { -- printf("SF: Failed to set up slave\n"); -- return NULL; -+ debug("SF: Failed to set up slave\n"); -+ return -1; - } - - ret = spi_claim_bus(spi); -@@ -379,13 +379,6 @@ struct spi_flash *spi_flash_probe(unsign - print_buffer(0, idcode, 1, sizeof(idcode), 0); - #endif - -- flash = malloc(sizeof(*flash)); -- if (!flash) { -- debug("SF: failed to alloc memory\n"); -- goto err_malloc; -- } -- -- memset(flash, 0, sizeof(*flash)); - flash->spi = spi; - - /* count the number of continuation bytes */ -@@ -404,30 +397,58 @@ struct spi_flash *spi_flash_probe(unsign - } - - if (ret <= 0) { -- printf("SF: Unsupported manufacturer %02x\n", *idp); -+ debug("SF: Unsupported manufacturer %02x\n", *idp); - goto err_manufacturer_probe; - } - -- printf("SF: Detected %s with page size ", flash->name); -- print_size(flash->sector_size, ", total "); -- print_size(flash->size, "\n"); -- - spi_release_bus(spi); - -- return flash; -+ return 0; - - err_manufacturer_probe: -- free(flash); --err_malloc: - err_read_id: - spi_release_bus(spi); - err_claim_bus: - spi_free_slave(spi); -+ -+ return ret; -+} -+ -+struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, -+ unsigned int max_hz, unsigned int spi_mode) -+{ -+ struct spi_flash *flash; -+ int ret; -+ -+ flash = malloc(sizeof(*flash)); -+ if (!flash) { -+ debug("SF: Failed to malloc spi_flash\n"); -+ return NULL; -+ } -+ memset(flash, 0, sizeof(*flash)); -+ -+ ret = spi_flash_probe_spl(flash, bus, cs, max_hz, spi_mode); -+ if (ret) -+ goto err_probe; -+ -+ printf("SF: %s, page size ", flash->name); -+ print_size(flash->sector_size, ", total "); -+ print_size(flash->size, "\n"); -+ -+ return flash; -+ -+err_probe: -+ free(flash); - return NULL; - } - --void spi_flash_free(struct spi_flash *flash) -+void spi_flash_free_spl(struct spi_flash *flash) - { - spi_free_slave(flash->spi); -+} -+ -+void spi_flash_free(struct spi_flash *flash) -+{ -+ spi_flash_free_spl(flash); - free(flash); - } ---- a/include/spi_flash.h -+++ b/include/spi_flash.h -@@ -52,6 +52,11 @@ struct spi_flash *spi_flash_probe(unsign - unsigned int max_hz, unsigned int spi_mode); - void spi_flash_free(struct spi_flash *flash); - -+int spi_flash_probe_spl(struct spi_flash *flash, unsigned int bus, -+ unsigned int cs, unsigned int max_hz, -+ unsigned int spi_mode); -+void spi_flash_free_spl(struct spi_flash *flash); -+ - static inline int spi_flash_read(struct spi_flash *flash, u32 offset, - size_t len, void *buf) - { diff --git a/package/boot/uboot-lantiq/patches/0004-sf-add-slim-probe-funtions-for-SPL.patch b/package/boot/uboot-lantiq/patches/0004-sf-add-slim-probe-funtions-for-SPL.patch new file mode 100644 index 0000000..d1768af --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0004-sf-add-slim-probe-funtions-for-SPL.patch @@ -0,0 +1,87 @@ +From da11da943487e2f724f25d409bcaa1f099637c0b Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 13 Oct 2013 14:56:45 +0200 +Subject: sf: add slim probe funtions for SPL + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index 2bba10c..380aa09 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -365,3 +365,58 @@ void spi_flash_free(struct spi_flash *flash) + spi_free_slave(flash->spi); + free(flash); + } ++ ++#ifdef CONFIG_SPI_SPL_SIMPLE ++int spl_spi_flash_probe(struct spi_flash *flash) ++{ ++ struct spi_slave *spi; ++ u8 idcode[5]; ++ int ret; ++ ++ /* Setup spi_slave */ ++ spi = spi_setup_slave(CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS, ++ CONFIG_SPL_SPI_MAX_HZ, CONFIG_SPL_SPI_MODE); ++ if (!spi) { ++ debug("SF: Failed to set up slave\n"); ++ return -1; ++ } ++ ++ /* Claim spi bus */ ++ ret = spi_claim_bus(spi); ++ if (ret) { ++ debug("SF: Failed to claim SPI bus: %d\n", ret); ++ goto err_claim_bus; ++ } ++ ++ /* Read the ID codes */ ++ ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode)); ++ if (ret) { ++ debug("SF: Failed to get idcodes\n"); ++ goto err_read_id; ++ } ++ ++ /* Validate params from spi_flash_params table */ ++ flash->spi = spi; ++ ret = spi_flash_validate_params(flash, idcode); ++ if (ret) ++ goto err_read_id; ++ ++ /* Release spi bus */ ++ spi_release_bus(spi); ++ ++ return 0; ++ ++err_read_id: ++ spi_release_bus(spi); ++err_claim_bus: ++ spi_free_slave(spi); ++ flash->spi = NULL; ++ ++ return ret; ++} ++ ++void spl_spi_flash_free(struct spi_flash *flash) ++{ ++ spi_free_slave(flash->spi); ++} ++#endif +diff --git a/include/spi_flash.h b/include/spi_flash.h +index 25ca8f1..411dd1b 100644 +--- a/include/spi_flash.h ++++ b/include/spi_flash.h +@@ -69,6 +69,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int spi_mode); + void spi_flash_free(struct spi_flash *flash); + ++int spl_spi_flash_probe(struct spi_flash *flash); ++void spl_spi_flash_free(struct spi_flash *flash); ++ + static inline int spi_flash_read(struct spi_flash *flash, u32 offset, + size_t len, void *buf) + { +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0005-sf-factor-out-the-flash-address-calculation.patch b/package/boot/uboot-lantiq/patches/0005-sf-factor-out-the-flash-address-calculation.patch deleted file mode 100644 index 356db59..0000000 --- a/package/boot/uboot-lantiq/patches/0005-sf-factor-out-the-flash-address-calculation.patch +++ /dev/null @@ -1,107 +0,0 @@ -From acb2721e1cd2e7488a7b08a4ed590177369a1689 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Tue, 6 Nov 2012 19:10:40 +0100 -Subject: sf: factor out the flash address calculation - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spi_flash.c -+++ b/drivers/mtd/spi/spi_flash.c -@@ -15,12 +15,22 @@ - - #include "spi_flash_internal.h" - --static void spi_flash_addr(u32 addr, u8 *cmd) -+static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd, u8 *cmd_len) - { - /* cmd[0] is actual command */ - cmd[1] = addr >> 16; - cmd[2] = addr >> 8; - cmd[3] = addr >> 0; -+ *cmd_len = 4; -+} -+ -+static void spi_flash_page_addr(struct spi_flash *flash, u32 page_addr, u32 byte_addr, u8 *cmd, u8 *cmd_len) -+{ -+ /* cmd[0] is actual command */ -+ cmd[1] = page_addr >> 8; -+ cmd[2] = page_addr >> 0; -+ cmd[3] = byte_addr; -+ *cmd_len = 4; - } - - static int spi_flash_read_write(struct spi_slave *spi, -@@ -71,7 +81,7 @@ int spi_flash_cmd_write_multi(struct spi - unsigned long page_addr, byte_addr, page_size; - size_t chunk_len, actual; - int ret; -- u8 cmd[4]; -+ u8 cmd[4], cmd_len; - - page_size = flash->page_size; - page_addr = offset / page_size; -@@ -87,9 +97,7 @@ int spi_flash_cmd_write_multi(struct spi - for (actual = 0; actual < len; actual += chunk_len) { - chunk_len = min(len - actual, page_size - byte_addr); - -- cmd[1] = page_addr >> 8; -- cmd[2] = page_addr; -- cmd[3] = byte_addr; -+ spi_flash_page_addr(flash, page_addr, byte_addr, cmd, &cmd_len); - - debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", - buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -@@ -100,7 +108,7 @@ int spi_flash_cmd_write_multi(struct spi - break; - } - -- ret = spi_flash_cmd_write(flash->spi, cmd, 4, -+ ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, - buf + actual, chunk_len); - if (ret < 0) { - debug("SF: write failed\n"); -@@ -138,13 +146,13 @@ int spi_flash_read_common(struct spi_fla - int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, - size_t len, void *data) - { -- u8 cmd[5]; -+ u8 cmd[5], cmd_len; - - cmd[0] = CMD_READ_ARRAY_FAST; -- spi_flash_addr(offset, cmd); -- cmd[4] = 0x00; -+ spi_flash_addr(flash, offset, cmd, &cmd_len); -+ cmd[cmd_len] = 0x00; - -- return spi_flash_read_common(flash, cmd, sizeof(cmd), data, len); -+ return spi_flash_read_common(flash, cmd, cmd_len + 1, data, len); - } - - int spi_flash_cmd_poll_bit(struct spi_flash *flash, unsigned long timeout, -@@ -194,7 +202,7 @@ int spi_flash_cmd_erase(struct spi_flash - { - u32 start, end, erase_size; - int ret; -- u8 cmd[4]; -+ u8 cmd[4], cmd_len; - - erase_size = flash->sector_size; - if (offset % erase_size || len % erase_size) { -@@ -216,7 +224,7 @@ int spi_flash_cmd_erase(struct spi_flash - end = start + len; - - while (offset < end) { -- spi_flash_addr(offset, cmd); -+ spi_flash_addr(flash, offset, cmd, &cmd_len); - offset += erase_size; - - debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], -@@ -226,7 +234,7 @@ int spi_flash_cmd_erase(struct spi_flash - if (ret) - goto out; - -- ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), NULL, 0); -+ ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len, NULL, 0); - if (ret) - goto out; - diff --git a/package/boot/uboot-lantiq/patches/0005-sf-make-calculatiom-of-address-bytes-completely-conf.patch b/package/boot/uboot-lantiq/patches/0005-sf-make-calculatiom-of-address-bytes-completely-conf.patch new file mode 100644 index 0000000..f17aa32 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0005-sf-make-calculatiom-of-address-bytes-completely-conf.patch @@ -0,0 +1,143 @@ +From 6fb5f86b094756d94de8abe7425e3d290ff22dd2 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 13 Oct 2013 15:09:28 +0200 +Subject: sf: make calculatiom of address bytes completely configurable + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c +index d34747b..207adf5 100644 +--- a/drivers/mtd/spi/sf_ops.c ++++ b/drivers/mtd/spi/sf_ops.c +@@ -15,12 +15,17 @@ + + #include "sf_internal.h" + +-static void spi_flash_addr(u32 addr, u8 *cmd) ++static void spi_flash_addr(const struct spi_flash *flash, u32 addr, u8 *cmd) + { + /* cmd[0] is actual command */ +- cmd[1] = addr >> 16; +- cmd[2] = addr >> 8; +- cmd[3] = addr >> 0; ++ cmd[1] = addr >> (flash->addr_width * 8 - 8); ++ cmd[2] = addr >> (flash->addr_width * 8 - 16); ++ cmd[3] = addr >> (flash->addr_width * 8 - 24); ++} ++ ++static int spi_flash_cmdsz(const struct spi_flash *flash) ++{ ++ return 1 + flash->addr_width; + } + + int spi_flash_cmd_write_status(struct spi_flash *flash, u8 sr) +@@ -158,7 +163,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, + int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + { + u32 erase_size; +- u8 cmd[4]; ++ u8 cmd[4], cmd_len; + int ret = -1; + + erase_size = flash->erase_size; +@@ -180,12 +185,13 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + if (ret < 0) + goto done; + #endif +- spi_flash_addr(offset, cmd); ++ spi_flash_addr(flash, offset, cmd); ++ cmd_len = spi_flash_cmdsz(flash); + + debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], + cmd[2], cmd[3], offset); + +- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0); ++ ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0); + if (ret < 0) { + debug("SF: erase failed\n"); + goto done; +@@ -206,7 +212,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + { + unsigned long byte_addr, page_size; + size_t chunk_len, actual; +- u8 cmd[4]; ++ u8 cmd[4], cmd_len; + int ret = -1; + + ret = spi_claim_bus(flash->spi); +@@ -230,12 +236,13 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + if (flash->spi->max_write_size) + chunk_len = min(chunk_len, flash->spi->max_write_size); + +- spi_flash_addr(offset, cmd); ++ spi_flash_addr(flash, offset, cmd); ++ cmd_len = spi_flash_cmdsz(flash); + + debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + +- ret = spi_flash_write_common(flash, cmd, sizeof(cmd), ++ ret = spi_flash_write_common(flash, cmd, cmd_len, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: write failed\n"); +@@ -269,7 +276,7 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + size_t len, void *data) + { +- u8 cmd[5], bank_sel = 0; ++ u8 cmd[5], cmd_len, bank_sel = 0; + u32 remain_len, read_len; + int ret = -1; + +@@ -288,7 +295,6 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + } + + cmd[0] = CMD_READ_ARRAY_FAST; +- cmd[4] = 0x00; + + while (len) { + #ifdef CONFIG_SPI_FLASH_BAR +@@ -306,9 +312,11 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + else + read_len = remain_len; + +- spi_flash_addr(offset, cmd); ++ spi_flash_addr(flash, offset, cmd); ++ cmd_len = spi_flash_cmdsz(flash); ++ cmd[cmd_len] = 0x00; + +- ret = spi_flash_read_common(flash, cmd, sizeof(cmd), ++ ret = spi_flash_read_common(flash, cmd, cmd_len + 1, + data, read_len); + if (ret < 0) { + debug("SF: read failed\n"); +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index 380aa09..84289db 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -218,6 +218,9 @@ static int spi_flash_validate_params(struct spi_flash *flash, + flash->poll_cmd = CMD_FLAG_STATUS; + #endif + ++ /* Configure default 3-byte addressing */ ++ flash->addr_width = 3; ++ + /* Configure the BAR - discover bank cmds and read current bank */ + #ifdef CONFIG_SPI_FLASH_BAR + u8 curr_bank = 0; +diff --git a/include/spi_flash.h b/include/spi_flash.h +index 411dd1b..cc9398b 100644 +--- a/include/spi_flash.h ++++ b/include/spi_flash.h +@@ -57,6 +57,7 @@ struct spi_flash { + #endif + u8 poll_cmd; + u8 erase_cmd; ++ u8 addr_width; + + void *memory_map; + int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf); +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0006-sf-add-generic-support-for-4-byte-address-mode.patch b/package/boot/uboot-lantiq/patches/0006-sf-add-generic-support-for-4-byte-address-mode.patch deleted file mode 100644 index 1623b15..0000000 --- a/package/boot/uboot-lantiq/patches/0006-sf-add-generic-support-for-4-byte-address-mode.patch +++ /dev/null @@ -1,161 +0,0 @@ -From fb9ed0ef6f0ba6b6535c64dcfcf45c161723e56f Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Tue, 6 Nov 2012 19:31:38 +0100 -Subject: sf: add generic support for 4-byte address mode - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spi_flash.c -+++ b/drivers/mtd/spi/spi_flash.c -@@ -18,19 +18,35 @@ - static void spi_flash_addr(struct spi_flash *flash, u32 addr, u8 *cmd, u8 *cmd_len) - { - /* cmd[0] is actual command */ -- cmd[1] = addr >> 16; -- cmd[2] = addr >> 8; -- cmd[3] = addr >> 0; -- *cmd_len = 4; -+ if (spi_flash_use_4byte_mode(flash)) { -+ cmd[1] = addr >> 24; -+ cmd[2] = addr >> 16; -+ cmd[3] = addr >> 8; -+ cmd[4] = addr >> 0; -+ *cmd_len = 5; -+ } else { -+ cmd[1] = addr >> 16; -+ cmd[2] = addr >> 8; -+ cmd[3] = addr >> 0; -+ *cmd_len = 4; -+ } - } - - static void spi_flash_page_addr(struct spi_flash *flash, u32 page_addr, u32 byte_addr, u8 *cmd, u8 *cmd_len) - { - /* cmd[0] is actual command */ -- cmd[1] = page_addr >> 8; -- cmd[2] = page_addr >> 0; -- cmd[3] = byte_addr; -- *cmd_len = 4; -+ if (spi_flash_use_4byte_mode(flash)) { -+ cmd[1] = page_addr >> 16; -+ cmd[2] = page_addr >> 8; -+ cmd[3] = page_addr >> 0; -+ cmd[4] = byte_addr; -+ *cmd_len = 5; -+ } else { -+ cmd[1] = page_addr >> 8; -+ cmd[2] = page_addr >> 0; -+ cmd[3] = byte_addr; -+ *cmd_len = 4; -+ } - } - - static int spi_flash_read_write(struct spi_slave *spi, -@@ -81,7 +97,7 @@ int spi_flash_cmd_write_multi(struct spi - unsigned long page_addr, byte_addr, page_size; - size_t chunk_len, actual; - int ret; -- u8 cmd[4], cmd_len; -+ u8 cmd[5], cmd_len; - - page_size = flash->page_size; - page_addr = offset / page_size; -@@ -99,8 +115,8 @@ int spi_flash_cmd_write_multi(struct spi - - spi_flash_page_addr(flash, page_addr, byte_addr, cmd, &cmd_len); - -- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", -- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); -+ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\n", -+ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len); - - ret = spi_flash_cmd_write_enable(flash); - if (ret < 0) { -@@ -146,7 +162,7 @@ int spi_flash_read_common(struct spi_fla - int spi_flash_cmd_read_fast(struct spi_flash *flash, u32 offset, - size_t len, void *data) - { -- u8 cmd[5], cmd_len; -+ u8 cmd[6], cmd_len; - - cmd[0] = CMD_READ_ARRAY_FAST; - spi_flash_addr(flash, offset, cmd, &cmd_len); -@@ -202,7 +218,7 @@ int spi_flash_cmd_erase(struct spi_flash - { - u32 start, end, erase_size; - int ret; -- u8 cmd[4], cmd_len; -+ u8 cmd[5], cmd_len; - - erase_size = flash->sector_size; - if (offset % erase_size || len % erase_size) { -@@ -227,8 +243,8 @@ int spi_flash_cmd_erase(struct spi_flash - spi_flash_addr(flash, offset, cmd, &cmd_len); - offset += erase_size; - -- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], -- cmd[2], cmd[3], offset); -+ debug("SF: erase %2x %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], -+ cmd[2], cmd[3], cmd[4], offset); - - ret = spi_flash_cmd_write_enable(flash); - if (ret) -@@ -409,6 +425,12 @@ int spi_flash_probe_spl(struct spi_flash - goto err_manufacturer_probe; - } - -+ ret = spi_flash_set_4byte_mode(flash); -+ if (ret) { -+ debug("SF: Failed to enable 4 byte mode: %d\n", ret); -+ goto err_manufacturer_probe; -+ } -+ - spi_release_bus(spi); - - return 0; ---- a/drivers/mtd/spi/spi_flash_internal.h -+++ b/drivers/mtd/spi/spi_flash_internal.h -@@ -97,6 +97,31 @@ int spi_flash_cmd_wait_ready(struct spi_ - /* Erase sectors. */ - int spi_flash_cmd_erase(struct spi_flash *flash, u32 offset, size_t len); - -+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE -+static inline int spi_flash_use_4byte_mode(struct spi_flash *flash) -+{ -+ return NULL != flash->set_4byte_mode; -+} -+ -+static inline int spi_flash_set_4byte_mode(struct spi_flash *flash) -+{ -+ if (spi_flash_use_4byte_mode(flash)) -+ return flash->set_4byte_mode(flash); -+ -+ return 0; -+} -+#else -+static inline int spi_flash_use_4byte_mode(struct spi_flash *flash) -+{ -+ return 0; -+} -+ -+static inline int spi_flash_set_4byte_mode(struct spi_flash *flash) -+{ -+ return 0; -+} -+#endif -+ - /* Manufacturer-specific probe functions */ - int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode); - int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode); ---- a/include/spi_flash.h -+++ b/include/spi_flash.h -@@ -46,6 +46,9 @@ struct spi_flash { - size_t len, const void *buf); - int (*erase)(struct spi_flash *flash, u32 offset, - size_t len); -+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE -+ int (*set_4byte_mode)(struct spi_flash *flash); -+#endif - }; - - struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, diff --git a/package/boot/uboot-lantiq/patches/0006-sf-add-support-for-4-byte-addressing.patch b/package/boot/uboot-lantiq/patches/0006-sf-add-support-for-4-byte-addressing.patch new file mode 100644 index 0000000..f386eee --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0006-sf-add-support-for-4-byte-addressing.patch @@ -0,0 +1,169 @@ +From 3af3addee645bd81537be1ddee49969f8dfc64ee Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 13 Oct 2013 15:24:56 +0200 +Subject: sf: add support for 4-byte addressing + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h +index 732ddf8..c5e8eb1 100644 +--- a/drivers/mtd/spi/sf_internal.h ++++ b/drivers/mtd/spi/sf_internal.h +@@ -38,12 +38,14 @@ + #define CMD_READ_ID 0x9f + + /* Bank addr access commands */ +-#ifdef CONFIG_SPI_FLASH_BAR +-# define CMD_BANKADDR_BRWR 0x17 +-# define CMD_BANKADDR_BRRD 0x16 +-# define CMD_EXTNADDR_WREAR 0xC5 +-# define CMD_EXTNADDR_RDEAR 0xC8 +-#endif ++#define CMD_BANKADDR_BRWR 0x17 ++#define CMD_BANKADDR_BRRD 0x16 ++#define CMD_EXTNADDR_WREAR 0xC5 ++#define CMD_EXTNADDR_RDEAR 0xC8 ++ ++/* Macronix style 4-byte addressing */ ++#define CMD_EN4B 0xb7 ++#define CMD_EX4B 0xe9 + + /* Common status */ + #define STATUS_WIP 0x01 +diff --git a/drivers/mtd/spi/sf_ops.c b/drivers/mtd/spi/sf_ops.c +index 207adf5..1d072f8 100644 +--- a/drivers/mtd/spi/sf_ops.c ++++ b/drivers/mtd/spi/sf_ops.c +@@ -21,6 +21,7 @@ static void spi_flash_addr(const struct spi_flash *flash, u32 addr, u8 *cmd) + cmd[1] = addr >> (flash->addr_width * 8 - 8); + cmd[2] = addr >> (flash->addr_width * 8 - 16); + cmd[3] = addr >> (flash->addr_width * 8 - 24); ++ cmd[4] = addr >> (flash->addr_width * 8 - 32); + } + + static int spi_flash_cmdsz(const struct spi_flash *flash) +@@ -163,7 +164,7 @@ int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd, + int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + { + u32 erase_size; +- u8 cmd[4], cmd_len; ++ u8 cmd[5], cmd_len; + int ret = -1; + + erase_size = flash->erase_size; +@@ -188,8 +189,8 @@ int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len) + spi_flash_addr(flash, offset, cmd); + cmd_len = spi_flash_cmdsz(flash); + +- debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], +- cmd[2], cmd[3], offset); ++ debug("SF: erase %2x %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1], ++ cmd[2], cmd[3], cmd[4], offset); + + ret = spi_flash_write_common(flash, cmd, cmd_len, NULL, 0); + if (ret < 0) { +@@ -212,7 +213,7 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + { + unsigned long byte_addr, page_size; + size_t chunk_len, actual; +- u8 cmd[4], cmd_len; ++ u8 cmd[5], cmd_len; + int ret = -1; + + ret = spi_claim_bus(flash->spi); +@@ -239,8 +240,8 @@ int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset, + spi_flash_addr(flash, offset, cmd); + cmd_len = spi_flash_cmdsz(flash); + +- debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n", +- buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); ++ debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x%02x } chunk_len = %zu\n", ++ buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], cmd[4], chunk_len); + + ret = spi_flash_write_common(flash, cmd, cmd_len, + buf + actual, chunk_len); +@@ -276,9 +277,13 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, + int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + size_t len, void *data) + { +- u8 cmd[5], cmd_len, bank_sel = 0; +- u32 remain_len, read_len; ++ u8 cmd[6], cmd_len; ++ u32 read_len; + int ret = -1; ++#ifdef CONFIG_SPI_FLASH_BAR ++ u8 bank_sel = 0; ++ u32 remain_len; ++#endif + + ret = spi_claim_bus(flash->spi); + if (ret) { +@@ -305,12 +310,15 @@ int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset, + debug("SF: fail to set bank%d\n", bank_sel); + goto done; + } +-#endif ++ + remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset; + if (len < remain_len) + read_len = len; + else + read_len = remain_len; ++#else ++ read_len = len; ++#endif + + spi_flash_addr(flash, offset, cmd); + cmd_len = spi_flash_cmdsz(flash); +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index 84289db..ac44287 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -153,6 +153,25 @@ static const struct spi_flash_params spi_flash_params_table[] = { + */ + }; + ++int spi_flash_4byte_set(struct spi_flash *flash, u8 idcode0, int enable) ++{ ++ u8 cmd, bankaddr; ++ ++ switch (idcode0) { ++ case 0xc2: ++ case 0xef: ++ case 0x1c: ++ /* Macronix style */ ++ cmd = enable ? CMD_EN4B : CMD_EX4B; ++ return spi_flash_cmd(flash->spi, cmd, NULL, 0); ++ default: ++ /* Spansion style */ ++ cmd = CMD_BANKADDR_BRWR; ++ bankaddr = enable << 7; ++ return spi_flash_cmd_write(flash->spi, &cmd, 1, &bankaddr, 1); ++ } ++} ++ + static int spi_flash_validate_params(struct spi_flash *flash, + u8 *idcode) + { +@@ -218,8 +237,18 @@ static int spi_flash_validate_params(struct spi_flash *flash, + flash->poll_cmd = CMD_FLAG_STATUS; + #endif + ++#ifndef CONFIG_SPI_FLASH_BAR ++ /* enable 4-byte addressing if the device exceeds 16MiB */ ++ if (flash->size > SPI_FLASH_16MB_BOUN) { ++ flash->addr_width = 4; ++ spi_flash_4byte_set(flash, idcode[0], 1); ++ } else { ++ flash->addr_width = 3; ++ } ++#else + /* Configure default 3-byte addressing */ + flash->addr_width = 3; ++#endif + + /* Configure the BAR - discover bank cmds and read current bank */ + #ifdef CONFIG_SPI_FLASH_BAR +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0007-sf-add-support-for-EN25QH256.patch b/package/boot/uboot-lantiq/patches/0007-sf-add-support-for-EN25QH256.patch new file mode 100644 index 0000000..561bd7b --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0007-sf-add-support-for-EN25QH256.patch @@ -0,0 +1,22 @@ +From d5aa0d4117a439803a3d074d2745372036d2a1eb Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 13 Oct 2013 15:35:34 +0200 +Subject: sf: add support for EN25QH256 + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index ac44287..7e87021 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -53,6 +53,7 @@ static const struct spi_flash_params spi_flash_params_table[] = { + {"EN25Q64", 0x1c3017, 0x0, 64 * 1024, 128, SECT_4K}, + {"EN25Q128B", 0x1c3018, 0x0, 64 * 1024, 256, 0}, + {"EN25S64", 0x1c3817, 0x0, 64 * 1024, 128, 0}, ++ {"EN25QH256", 0x1c7019, 0x0, 64 * 1024, 512, 0}, + #endif + #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ + {"GD25Q64B", 0xc84017, 0x0, 64 * 1024, 128, SECT_4K}, +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0007-sf-eon-use-16-bit-ID-for-comparison.patch b/package/boot/uboot-lantiq/patches/0007-sf-eon-use-16-bit-ID-for-comparison.patch deleted file mode 100644 index 6836674..0000000 --- a/package/boot/uboot-lantiq/patches/0007-sf-eon-use-16-bit-ID-for-comparison.patch +++ /dev/null @@ -1,45 +0,0 @@ -From d32f45357f0475a2f810752eeb9412fe692e1c0a Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 14:09:21 +0100 -Subject: sf: eon: use 16 bit ID for comparison - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/eon.c -+++ b/drivers/mtd/spi/eon.c -@@ -11,19 +11,19 @@ - #include "spi_flash_internal.h" - - struct eon_spi_flash_params { -- u8 idcode1; -+ u16 idcode; - u16 nr_sectors; - const char *name; - }; - - static const struct eon_spi_flash_params eon_spi_flash_table[] = { - { -- .idcode1 = 0x16, -+ .idcode = 0x3016, - .nr_sectors = 1024, - .name = "EN25Q32B", - }, - { -- .idcode1 = 0x18, -+ .idcode = 0x3018, - .nr_sectors = 4096, - .name = "EN25Q128", - }, -@@ -33,10 +33,11 @@ int spi_flash_probe_eon(struct spi_flash - { - const struct eon_spi_flash_params *params; - unsigned int i; -+ u16 id = idcode[2] | idcode[1] << 8; - - for (i = 0; i < ARRAY_SIZE(eon_spi_flash_table); ++i) { - params = &eon_spi_flash_table[i]; -- if (params->idcode1 == idcode[2]) -+ if (params->idcode == id) - break; - } - diff --git a/package/boot/uboot-lantiq/patches/0008-sf-eon-add-support-for-4-byte-address-mode.patch b/package/boot/uboot-lantiq/patches/0008-sf-eon-add-support-for-4-byte-address-mode.patch deleted file mode 100644 index c037a86..0000000 --- a/package/boot/uboot-lantiq/patches/0008-sf-eon-add-support-for-4-byte-address-mode.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 37254e3284f61ea495f73a78b7c8efae983781e2 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 14:10:07 +0100 -Subject: sf: eon: add support for 4-byte address mode - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/eon.c -+++ b/drivers/mtd/spi/eon.c -@@ -10,6 +10,8 @@ - - #include "spi_flash_internal.h" - -+#define EN25XX_EN4B 0xb7 /* Enter 4-byte mode */ -+ - struct eon_spi_flash_params { - u16 idcode; - u16 nr_sectors; -@@ -29,6 +31,13 @@ static const struct eon_spi_flash_params - }, - }; - -+static __maybe_unused int eon_set_4byte_mode(struct spi_flash *flash) -+{ -+ struct spi_slave *spi = flash->spi; -+ -+ return spi_flash_cmd(spi, EN25XX_EN4B, NULL, 0); -+} -+ - int spi_flash_probe_eon(struct spi_flash *flash, u8 *idcode) - { - const struct eon_spi_flash_params *params; -@@ -57,5 +66,10 @@ int spi_flash_probe_eon(struct spi_flash - flash->size = 256 * 16 - * params->nr_sectors; - -+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE -+ if (flash->size > (1 << 24)) -+ flash->set_4byte_mode = eon_set_4byte_mode; -+#endif -+ - return 1; - } diff --git a/package/boot/uboot-lantiq/patches/0008-sf-fix-sector-layout-of-S25FL256S_256K-and-S25FL512S.patch b/package/boot/uboot-lantiq/patches/0008-sf-fix-sector-layout-of-S25FL256S_256K-and-S25FL512S.patch new file mode 100644 index 0000000..f313044 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0008-sf-fix-sector-layout-of-S25FL256S_256K-and-S25FL512S.patch @@ -0,0 +1,26 @@ +From 5a6d8045190c887c7f65e65fb1bfc8854774c458 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 13 Oct 2013 15:40:07 +0200 +Subject: sf: fix sector layout of S25FL256S_256K and S25FL512S_256K + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c +index 7e87021..1fc224e 100644 +--- a/drivers/mtd/spi/sf_probe.c ++++ b/drivers/mtd/spi/sf_probe.c +@@ -80,9 +80,9 @@ static const struct spi_flash_params spi_flash_params_table[] = { + {"S25FL032P", 0x010215, 0x4d00, 64 * 1024, 64, 0}, + {"S25FL064P", 0x010216, 0x4d00, 64 * 1024, 128, 0}, + {"S25FL128S_64K", 0x012018, 0x4d01, 64 * 1024, 256, 0}, +- {"S25FL256S_256K", 0x010219, 0x4d00, 64 * 1024, 512, 0}, ++ {"S25FL256S_256K", 0x010219, 0x4d00, 256 * 1024, 128, 0}, + {"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, 0}, +- {"S25FL512S_256K", 0x010220, 0x4d00, 64 * 1024, 1024, 0}, ++ {"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, 0}, + {"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, 0}, + #endif + #ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0019-net-switchlib-add-framework-for-ethernet-switch-driv.patch b/package/boot/uboot-lantiq/patches/0009-net-switchlib-add-framework-for-ethernet-switch-driv.patch index a215d1a..e25df31 100644 --- a/package/boot/uboot-lantiq/patches/0019-net-switchlib-add-framework-for-ethernet-switch-driv.patch +++ b/package/boot/uboot-lantiq/patches/0009-net-switchlib-add-framework-for-ethernet-switch-driv.patch @@ -1,4 +1,4 @@ -From d8b1597130d228bc7e2bafd0c8d097529018c833 Mon Sep 17 00:00:00 2001 +From 0dff8c753c8929a478357abb38db0d1c1a60ec94 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Date: Wed, 29 Aug 2012 22:08:15 +0200 Subject: net: switchlib: add framework for ethernet switch drivers @@ -10,9 +10,11 @@ setup code for switch devices across different boards. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> +diff --git a/Makefile b/Makefile +index dc04179..6ee9a3c 100644 --- a/Makefile +++ b/Makefile -@@ -291,6 +291,7 @@ LIBS-y += drivers/mtd/ubi/libubi.o +@@ -280,6 +280,7 @@ LIBS-y += drivers/mtd/ubi/libubi.o LIBS-y += drivers/mtd/spi/libspi_flash.o LIBS-y += drivers/net/libnet.o LIBS-y += drivers/net/phy/libphy.o @@ -20,15 +22,17 @@ Cc: Joe Hershberger <joe.hershberger@gmail.com> LIBS-y += drivers/pci/libpci.o LIBS-y += drivers/pcmcia/libpcmcia.o LIBS-y += drivers/power/libpower.o \ +diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile +new file mode 100644 +index 0000000..31719d8 --- /dev/null +++ b/drivers/net/switch/Makefile -@@ -0,0 +1,31 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,30 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -54,14 +58,16 @@ Cc: Joe Hershberger <joe.hershberger@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c +new file mode 100644 +index 0000000..0e1d6b7 --- /dev/null +++ b/drivers/net/switch/switch.c -@@ -0,0 +1,63 @@ +@@ -0,0 +1,62 @@ +/* -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -120,14 +126,17 @@ Cc: Joe Hershberger <joe.hershberger@gmail.com> + + return NULL; +} +diff --git a/include/switch.h b/include/switch.h +new file mode 100644 +index 0000000..4a7ae63 --- /dev/null +++ b/include/switch.h -@@ -0,0 +1,95 @@ +@@ -0,0 +1,102 @@ +/* + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + */ + +#ifndef __SWITCH_H @@ -203,7 +212,14 @@ Cc: Joe Hershberger <joe.hershberger@gmail.com> + * Probe the available switch chips and connect the found one + * with the given MII bus + */ ++#ifdef CONFIG_SWITCH_MULTI +extern struct switch_device *switch_connect(struct mii_dev *bus); ++#else ++static inline struct switch_device *switch_connect(struct mii_dev *bus) ++{ ++ return NULL; ++} ++#endif + +/* + * Setup the given switch device @@ -218,9 +234,11 @@ Cc: Joe Hershberger <joe.hershberger@gmail.com> + +#endif /* __SWITCH_H */ + +diff --git a/net/eth.c b/net/eth.c +index c96e767..03ecc1c 100644 --- a/net/eth.c +++ b/net/eth.c -@@ -26,6 +26,7 @@ +@@ -10,6 +10,7 @@ #include <net.h> #include <miiphy.h> #include <phy.h> @@ -228,7 +246,7 @@ Cc: Joe Hershberger <joe.hershberger@gmail.com> void eth_parse_enetaddr(const char *addr, uchar *enetaddr) { -@@ -303,6 +304,8 @@ int eth_initialize(bd_t *bis) +@@ -287,6 +288,8 @@ int eth_initialize(bd_t *bis) phy_init(); #endif @@ -237,3 +255,6 @@ Cc: Joe Hershberger <joe.hershberger@gmail.com> eth_env_init(bis); /* +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0009-sf-eon-add-support-for-EN25QH256.patch b/package/boot/uboot-lantiq/patches/0009-sf-eon-add-support-for-EN25QH256.patch deleted file mode 100644 index 18f5823..0000000 --- a/package/boot/uboot-lantiq/patches/0009-sf-eon-add-support-for-EN25QH256.patch +++ /dev/null @@ -1,21 +0,0 @@ -From e510be1145796cd44cf5800e187a94ad7c19e764 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 14:10:34 +0100 -Subject: sf: eon: add support for EN25QH256 - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/eon.c -+++ b/drivers/mtd/spi/eon.c -@@ -29,6 +29,11 @@ static const struct eon_spi_flash_params - .nr_sectors = 4096, - .name = "EN25Q128", - }, -+ { -+ .idcode = 0x7019, -+ .nr_sectors = 8192, -+ .name = "EN25QH256", -+ }, - }; - - static __maybe_unused int eon_set_4byte_mode(struct spi_flash *flash) diff --git a/package/boot/uboot-lantiq/patches/0020-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch b/package/boot/uboot-lantiq/patches/0010-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch index c017e0f..8e7803a 100644 --- a/package/boot/uboot-lantiq/patches/0020-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch +++ b/package/boot/uboot-lantiq/patches/0010-net-switchlib-add-driver-for-Lantiq-PSB697X-switch-f.patch @@ -1,13 +1,15 @@ -From b8c666eda693906488637c414db9db35b6760e4a Mon Sep 17 00:00:00 2001 +From e2c59cedebf72e4a002134a2932f722b508a5448 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Date: Wed, 29 Aug 2012 22:08:15 +0200 Subject: net: switchlib: add driver for Lantiq PSB697X switch family Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile +index 31719d8..a426774 100644 --- a/drivers/net/switch/Makefile +++ b/drivers/net/switch/Makefile -@@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk +@@ -10,6 +10,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libswitch.o COBJS-$(CONFIG_SWITCH_MULTI) += switch.o @@ -15,14 +17,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) +diff --git a/drivers/net/switch/psb697x.c b/drivers/net/switch/psb697x.c +new file mode 100644 +index 0000000..cb6c391 --- /dev/null +++ b/drivers/net/switch/psb697x.c -@@ -0,0 +1,119 @@ +@@ -0,0 +1,118 @@ +/* -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -137,9 +141,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + switch_driver_register(&psb697x_drv); +} +diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c +index 0e1d6b7..3d02610 100644 --- a/drivers/net/switch/switch.c +++ b/drivers/net/switch/switch.c -@@ -18,6 +18,10 @@ void switch_init(void) +@@ -17,6 +17,10 @@ void switch_init(void) INIT_LIST_HEAD(&switch_drivers); INIT_LIST_HEAD(&switch_devices); @@ -150,9 +156,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> board_switch_init(); } +diff --git a/include/switch.h b/include/switch.h +index 4a7ae63..fd3cdbd 100644 --- a/include/switch.h +++ b/include/switch.h -@@ -90,6 +90,7 @@ static inline void switch_setup(struct s +@@ -97,6 +97,7 @@ static inline void switch_setup(struct switch_device *dev) } /* Init functions for supported Switch drivers */ @@ -160,3 +168,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> #endif /* __SWITCH_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0010-sf-spansion-fix-device-IDs-and-sector-architecture-f.patch b/package/boot/uboot-lantiq/patches/0010-sf-spansion-fix-device-IDs-and-sector-architecture-f.patch deleted file mode 100644 index af8c7a1..0000000 --- a/package/boot/uboot-lantiq/patches/0010-sf-spansion-fix-device-IDs-and-sector-architecture-f.patch +++ /dev/null @@ -1,30 +0,0 @@ -From 81a8e9e192d53ce8b5cafd47190d6c6826519d09 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 14:58:59 +0100 -Subject: sf: spansion: fix device IDs and sector architecture for S25FL256S - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spansion.c -+++ b/drivers/mtd/spi/spansion.c -@@ -97,11 +97,18 @@ static const struct spansion_spi_flash_p - .name = "S25FL129P_64K", - }, - { -- .idcode1 = 0x2019, -+ .idcode1 = 0x0219, - .idcode2 = 0x4d01, - .pages_per_sector = 256, - .nr_sectors = 512, -- .name = "S25FL256S", -+ .name = "S25FL256S_64K", -+ }, -+ { -+ .idcode1 = 0x0219, -+ .idcode2 = 0x4d00, -+ .pages_per_sector = 1024, -+ .nr_sectors = 128, -+ .name = "S25FL256S_256K", - }, - }; - diff --git a/package/boot/uboot-lantiq/patches/0021-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch b/package/boot/uboot-lantiq/patches/0011-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch index 342fa46..a30da0b 100644 --- a/package/boot/uboot-lantiq/patches/0021-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch +++ b/package/boot/uboot-lantiq/patches/0011-net-switchlib-add-driver-for-Lantiq-ADM6996I-switch-.patch @@ -1,13 +1,15 @@ -From fcbbb1beb2ae862f5c703c5719ed0e155cbbf82f Mon Sep 17 00:00:00 2001 +From c291443dc97dadcf0c6afd04688a7d9f79a221b5 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Date: Wed, 29 Aug 2012 22:08:16 +0200 Subject: net: switchlib: add driver for Lantiq ADM6996I switch family Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile +index a426774..6b7eeb9 100644 --- a/drivers/net/switch/Makefile +++ b/drivers/net/switch/Makefile -@@ -12,6 +12,7 @@ LIB := $(obj)libswitch.o +@@ -11,6 +11,7 @@ LIB := $(obj)libswitch.o COBJS-$(CONFIG_SWITCH_MULTI) += switch.o COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o @@ -15,14 +17,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) +diff --git a/drivers/net/switch/adm6996i.c b/drivers/net/switch/adm6996i.c +new file mode 100644 +index 0000000..46fcdc9 --- /dev/null +++ b/drivers/net/switch/adm6996i.c -@@ -0,0 +1,116 @@ +@@ -0,0 +1,115 @@ +/* -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -134,9 +138,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + switch_driver_register(&adm6996i_drv); +} +diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c +index 3d02610..ea3fe9c 100644 --- a/drivers/net/switch/switch.c +++ b/drivers/net/switch/switch.c -@@ -21,6 +21,9 @@ void switch_init(void) +@@ -20,6 +20,9 @@ void switch_init(void) #if defined(CONFIG_SWITCH_PSB697X) switch_psb697x_init(); #endif @@ -146,9 +152,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> board_switch_init(); } +diff --git a/include/switch.h b/include/switch.h +index fd3cdbd..4b46df0 100644 --- a/include/switch.h +++ b/include/switch.h -@@ -91,6 +91,7 @@ static inline void switch_setup(struct s +@@ -98,6 +98,7 @@ static inline void switch_setup(struct switch_device *dev) /* Init functions for supported Switch drivers */ extern void switch_psb697x_init(void); @@ -156,3 +164,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> #endif /* __SWITCH_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0011-sf-spansion-add-support-for-4-byte-address-mode.patch b/package/boot/uboot-lantiq/patches/0011-sf-spansion-add-support-for-4-byte-address-mode.patch deleted file mode 100644 index 9471d47..0000000 --- a/package/boot/uboot-lantiq/patches/0011-sf-spansion-add-support-for-4-byte-address-mode.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 0add8e5c60961d2b99174610df8d3d9d6d192b74 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 14:16:11 +0100 -Subject: sf: spansion: add support for 4-byte address mode - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spansion.c -+++ b/drivers/mtd/spi/spansion.c -@@ -31,6 +31,10 @@ - - #include "spi_flash_internal.h" - -+#define S25FLXX_BRRD 0x16 /* Read Bank Register */ -+#define S25FLXX_BRWR 0x17 /* Write Bank Register */ -+#define S25FLXX_BAR_EXTADD (1 << 7) /* Extended address enable */ -+ - struct spansion_spi_flash_params { - u16 idcode1; - u16 idcode2; -@@ -112,6 +116,23 @@ static const struct spansion_spi_flash_p - }, - }; - -+static __maybe_unused int spansion_set_4byte_mode(struct spi_flash *flash) -+{ -+ struct spi_slave *spi = flash->spi; -+ u8 bar, cmd; -+ int err; -+ -+ cmd = S25FLXX_BRRD; -+ err = spi_flash_cmd(spi, cmd, &bar, 1); -+ if (err) -+ return err; -+ -+ bar |= S25FLXX_BAR_EXTADD; -+ cmd = S25FLXX_BRWR; -+ -+ return spi_flash_cmd_write(spi, &cmd, 1, &bar, 1); -+} -+ - int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode) - { - const struct spansion_spi_flash_params *params; -@@ -144,5 +165,10 @@ int spi_flash_probe_spansion(struct spi_ - flash->sector_size = 256 * params->pages_per_sector; - flash->size = flash->sector_size * params->nr_sectors; - -+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE -+ if (flash->size > (1 << 24)) -+ flash->set_4byte_mode = spansion_set_4byte_mode; -+#endif -+ - return 1; - } diff --git a/package/boot/uboot-lantiq/patches/0022-net-switchlib-add-driver-for-Atheros-AR8216.patch b/package/boot/uboot-lantiq/patches/0012-net-switchlib-add-driver-for-Atheros-AR8216.patch index 127c0d8..c270b88 100644 --- a/package/boot/uboot-lantiq/patches/0022-net-switchlib-add-driver-for-Atheros-AR8216.patch +++ b/package/boot/uboot-lantiq/patches/0012-net-switchlib-add-driver-for-Atheros-AR8216.patch @@ -1,14 +1,16 @@ -From 16b8c52f80f20e07866e397ff52ff9658766437b Mon Sep 17 00:00:00 2001 -From: Luka Perkov <luka@openwrt.org> +From 1a1d61a2faf0390033a3766559ce0e758e15894e Mon Sep 17 00:00:00 2001 +From: Luka Perkov <openwrt@lukaperkov.net> Date: Wed, 29 Aug 2012 22:08:16 +0200 Subject: net: switchlib: add driver for Atheros AR8216 -Signed-off-by: Luka Perkov <luka@openwrt.org> +Signed-off-by: Luka Perkov <openwrt@lukaperkov.net> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile +index 6b7eeb9..7400897 100644 --- a/drivers/net/switch/Makefile +++ b/drivers/net/switch/Makefile -@@ -13,6 +13,7 @@ LIB := $(obj)libswitch.o +@@ -12,6 +12,7 @@ LIB := $(obj)libswitch.o COBJS-$(CONFIG_SWITCH_MULTI) += switch.o COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o @@ -16,14 +18,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) +diff --git a/drivers/net/switch/ar8216.c b/drivers/net/switch/ar8216.c +new file mode 100644 +index 0000000..f1348f0 --- /dev/null +++ b/drivers/net/switch/ar8216.c -@@ -0,0 +1,115 @@ +@@ -0,0 +1,114 @@ +/* + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> + * -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -134,9 +138,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + switch_driver_register(&ar8216_drv); +} +diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c +index ea3fe9c..3e34a7f 100644 --- a/drivers/net/switch/switch.c +++ b/drivers/net/switch/switch.c -@@ -24,6 +24,9 @@ void switch_init(void) +@@ -23,6 +23,9 @@ void switch_init(void) #if defined(CONFIG_SWITCH_ADM6996I) switch_adm6996i_init(); #endif @@ -146,9 +152,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> board_switch_init(); } +diff --git a/include/switch.h b/include/switch.h +index 4b46df0..ae7b123 100644 --- a/include/switch.h +++ b/include/switch.h -@@ -92,6 +92,7 @@ static inline void switch_setup(struct s +@@ -99,6 +99,7 @@ static inline void switch_setup(struct switch_device *dev) /* Init functions for supported Switch drivers */ extern void switch_psb697x_init(void); extern void switch_adm6996i_init(void); @@ -156,3 +164,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> #endif /* __SWITCH_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0012-sf-spansion-add-support-for-S25FL512S.patch b/package/boot/uboot-lantiq/patches/0012-sf-spansion-add-support-for-S25FL512S.patch deleted file mode 100644 index 5f415a9..0000000 --- a/package/boot/uboot-lantiq/patches/0012-sf-spansion-add-support-for-S25FL512S.patch +++ /dev/null @@ -1,23 +0,0 @@ -From bff335ac524843bc90163c3b231091a5016f8670 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 15:07:54 +0100 -Subject: sf: spansion: add support for S25FL512S - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spansion.c -+++ b/drivers/mtd/spi/spansion.c -@@ -114,6 +114,13 @@ static const struct spansion_spi_flash_p - .nr_sectors = 128, - .name = "S25FL256S_256K", - }, -+ { -+ .idcode1 = 0x0220, -+ .idcode2 = 0x4d00, -+ .pages_per_sector = 1024, -+ .nr_sectors = 256, -+ .name = "S25FL512S_256K", -+ }, - }; - - static __maybe_unused int spansion_set_4byte_mode(struct spi_flash *flash) diff --git a/package/boot/uboot-lantiq/patches/0013-net-switchlib-add-driver-for-REALTEK-RTL8306.patch b/package/boot/uboot-lantiq/patches/0013-net-switchlib-add-driver-for-REALTEK-RTL8306.patch new file mode 100644 index 0000000..e6bb374 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0013-net-switchlib-add-driver-for-REALTEK-RTL8306.patch @@ -0,0 +1,387 @@ +From 42cb399df978a33539b95d668b3f973d927cb902 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 17 Dec 2012 23:37:57 +0100 +Subject: net: switchlib: add driver for REALTEK RTL8306 + +Signed-off-by: Oliver Muth <dr.o.muth@gmx.de> +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/drivers/net/switch/Makefile b/drivers/net/switch/Makefile +index 7400897..08c6972 100644 +--- a/drivers/net/switch/Makefile ++++ b/drivers/net/switch/Makefile +@@ -13,6 +13,7 @@ COBJS-$(CONFIG_SWITCH_MULTI) += switch.o + COBJS-$(CONFIG_SWITCH_PSB697X) += psb697x.o + COBJS-$(CONFIG_SWITCH_ADM6996I) += adm6996i.o + COBJS-$(CONFIG_SWITCH_AR8216) += ar8216.o ++COBJS-$(CONFIG_SWITCH_RTL8306) += rtl8306.o + + COBJS := $(COBJS-y) + SRCS := $(COBJS:.o=.c) +diff --git a/drivers/net/switch/rtl8306.c b/drivers/net/switch/rtl8306.c +new file mode 100644 +index 0000000..7a6a917 +--- /dev/null ++++ b/drivers/net/switch/rtl8306.c +@@ -0,0 +1,332 @@ ++/* ++ * Based on OpenWRT linux driver ++ * ++ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#define DEBUG ++#include <common.h> ++#include <malloc.h> ++#include <switch.h> ++#include <miiphy.h> ++ ++#define RTL8306_REG_PAGE 16 ++#define RTL8306_REG_PAGE_LO (1 << 15) ++#define RTL8306_REG_PAGE_HI (1 << 1) /* inverted */ ++#define RTL8306_CHIPID 0x5988 ++ ++#define RTL8306_NUM_VLANS 16 ++#define RTL8306_NUM_PORTS 6 ++#define RTL8306_PORT_CPU 5 ++#define RTL8306_NUM_PAGES 4 ++#define RTL8306_NUM_REGS 32 ++ ++enum { ++ RTL_TYPE_S, ++ RTL_TYPE_SD, ++ RTL_TYPE_SDM, ++}; ++ ++struct rtl_reg { ++ int page; ++ int phy; ++ int reg; ++ int bits; ++ int shift; ++ int inverted; ++}; ++ ++enum rtl_regidx { ++ RTL_REG_CHIPID, ++ RTL_REG_CHIPVER, ++ RTL_REG_CHIPTYPE, ++ RTL_REG_CPUPORT, ++ ++ RTL_REG_EN_CPUPORT, ++ RTL_REG_EN_TAG_OUT, ++ RTL_REG_EN_TAG_CLR, ++ RTL_REG_EN_TAG_IN, ++ RTL_REG_TRAP_CPU, ++ RTL_REG_TRUNK_PORTSEL, ++ RTL_REG_EN_TRUNK, ++ RTL_REG_RESET, ++ RTL_REG_PHY_RESET, ++ RTL_REG_CPU_LINKUP, ++ ++ RTL_REG_VLAN_ENABLE, ++ RTL_REG_VLAN_FILTER, ++ RTL_REG_VLAN_TAG_ONLY, ++ RTL_REG_VLAN_TAG_AWARE, ++#define RTL_VLAN_ENUM(id) \ ++ RTL_REG_VLAN##id##_VID, \ ++ RTL_REG_VLAN##id##_PORTMASK ++ RTL_VLAN_ENUM(0), ++ RTL_VLAN_ENUM(1), ++ RTL_VLAN_ENUM(2), ++ RTL_VLAN_ENUM(3), ++ RTL_VLAN_ENUM(4), ++ RTL_VLAN_ENUM(5), ++ RTL_VLAN_ENUM(6), ++ RTL_VLAN_ENUM(7), ++ RTL_VLAN_ENUM(8), ++ RTL_VLAN_ENUM(9), ++ RTL_VLAN_ENUM(10), ++ RTL_VLAN_ENUM(11), ++ RTL_VLAN_ENUM(12), ++ RTL_VLAN_ENUM(13), ++ RTL_VLAN_ENUM(14), ++ RTL_VLAN_ENUM(15), ++#define RTL_PORT_ENUM(id) \ ++ RTL_REG_PORT##id##_PVID, \ ++ RTL_REG_PORT##id##_NULL_VID_REPLACE, \ ++ RTL_REG_PORT##id##_NON_PVID_DISCARD, \ ++ RTL_REG_PORT##id##_VID_INSERT, \ ++ RTL_REG_PORT##id##_TAG_INSERT, \ ++ RTL_REG_PORT##id##_LINK, \ ++ RTL_REG_PORT##id##_SPEED, \ ++ RTL_REG_PORT##id##_NWAY, \ ++ RTL_REG_PORT##id##_NRESTART, \ ++ RTL_REG_PORT##id##_DUPLEX, \ ++ RTL_REG_PORT##id##_RXEN, \ ++ RTL_REG_PORT##id##_TXEN, \ ++ RTL_REG_PORT##id##_LRNEN ++ RTL_PORT_ENUM(0), ++ RTL_PORT_ENUM(1), ++ RTL_PORT_ENUM(2), ++ RTL_PORT_ENUM(3), ++ RTL_PORT_ENUM(4), ++ RTL_PORT_ENUM(5), ++}; ++ ++static const struct rtl_reg rtl_regs[] = { ++ [RTL_REG_CHIPID] = { 0, 4, 30, 16, 0, 0 }, ++ [RTL_REG_CHIPVER] = { 0, 4, 31, 8, 0, 0 }, ++ [RTL_REG_CHIPTYPE] = { 0, 4, 31, 2, 8, 0 }, ++ ++ /* CPU port number */ ++ [RTL_REG_CPUPORT] = { 2, 4, 21, 3, 0, 0 }, ++ /* Enable CPU port function */ ++ [RTL_REG_EN_CPUPORT] = { 3, 2, 21, 1, 15, 1 }, ++ /* Enable CPU port tag insertion */ ++ [RTL_REG_EN_TAG_OUT] = { 3, 2, 21, 1, 12, 0 }, ++ /* Enable CPU port tag removal */ ++ [RTL_REG_EN_TAG_CLR] = { 3, 2, 21, 1, 11, 0 }, ++ /* Enable CPU port tag checking */ ++ [RTL_REG_EN_TAG_IN] = { 0, 4, 21, 1, 7, 0 }, ++ [RTL_REG_EN_TRUNK] = { 0, 0, 19, 1, 11, 1 }, ++ [RTL_REG_TRUNK_PORTSEL] = { 0, 0, 16, 1, 6, 1 }, ++ [RTL_REG_RESET] = { 0, 0, 16, 1, 12, 0 }, ++ [RTL_REG_PHY_RESET] = { 0, 0, 0, 1, 15, 0 }, ++ [RTL_REG_CPU_LINKUP] = { 0, 6, 22, 1, 15, 0 }, ++ [RTL_REG_TRAP_CPU] = { 3, 2, 22, 1, 6, 0 }, ++ ++ [RTL_REG_VLAN_TAG_ONLY] = { 0, 0, 16, 1, 8, 1 }, ++ [RTL_REG_VLAN_FILTER] = { 0, 0, 16, 1, 9, 1 }, ++ [RTL_REG_VLAN_TAG_AWARE] = { 0, 0, 16, 1, 10, 1 }, ++ [RTL_REG_VLAN_ENABLE] = { 0, 0, 18, 1, 8, 1 }, ++ ++#define RTL_VLAN_REGS(id, phy, page, regofs) \ ++ [RTL_REG_VLAN##id##_VID] = { page, phy, 25 + regofs, 12, 0, 0 }, \ ++ [RTL_REG_VLAN##id##_PORTMASK] = { page, phy, 24 + regofs, 6, 0, 0 } ++ RTL_VLAN_REGS( 0, 0, 0, 0), ++ RTL_VLAN_REGS( 1, 1, 0, 0), ++ RTL_VLAN_REGS( 2, 2, 0, 0), ++ RTL_VLAN_REGS( 3, 3, 0, 0), ++ RTL_VLAN_REGS( 4, 4, 0, 0), ++ RTL_VLAN_REGS( 5, 0, 1, 2), ++ RTL_VLAN_REGS( 6, 1, 1, 2), ++ RTL_VLAN_REGS( 7, 2, 1, 2), ++ RTL_VLAN_REGS( 8, 3, 1, 2), ++ RTL_VLAN_REGS( 9, 4, 1, 2), ++ RTL_VLAN_REGS(10, 0, 1, 4), ++ RTL_VLAN_REGS(11, 1, 1, 4), ++ RTL_VLAN_REGS(12, 2, 1, 4), ++ RTL_VLAN_REGS(13, 3, 1, 4), ++ RTL_VLAN_REGS(14, 4, 1, 4), ++ RTL_VLAN_REGS(15, 0, 1, 6), ++ ++#define REG_PORT_SETTING(port, phy) \ ++ [RTL_REG_PORT##port##_SPEED] = { 0, phy, 0, 1, 13, 0 }, \ ++ [RTL_REG_PORT##port##_NWAY] = { 0, phy, 0, 1, 12, 0 }, \ ++ [RTL_REG_PORT##port##_NRESTART] = { 0, phy, 0, 1, 9, 0 }, \ ++ [RTL_REG_PORT##port##_DUPLEX] = { 0, phy, 0, 1, 8, 0 }, \ ++ [RTL_REG_PORT##port##_TXEN] = { 0, phy, 24, 1, 11, 0 }, \ ++ [RTL_REG_PORT##port##_RXEN] = { 0, phy, 24, 1, 10, 0 }, \ ++ [RTL_REG_PORT##port##_LRNEN] = { 0, phy, 24, 1, 9, 0 }, \ ++ [RTL_REG_PORT##port##_LINK] = { 0, phy, 1, 1, 2, 0 }, \ ++ [RTL_REG_PORT##port##_NULL_VID_REPLACE] = { 0, phy, 22, 1, 12, 0 }, \ ++ [RTL_REG_PORT##port##_NON_PVID_DISCARD] = { 0, phy, 22, 1, 11, 0 }, \ ++ [RTL_REG_PORT##port##_VID_INSERT] = { 0, phy, 22, 2, 9, 0 }, \ ++ [RTL_REG_PORT##port##_TAG_INSERT] = { 0, phy, 22, 2, 0, 0 } ++ ++ REG_PORT_SETTING(0, 0), ++ REG_PORT_SETTING(1, 1), ++ REG_PORT_SETTING(2, 2), ++ REG_PORT_SETTING(3, 3), ++ REG_PORT_SETTING(4, 4), ++ REG_PORT_SETTING(5, 6), ++ ++#define REG_PORT_PVID(phy, page, regofs) \ ++ { page, phy, 24 + regofs, 4, 12, 0 } ++ [RTL_REG_PORT0_PVID] = REG_PORT_PVID(0, 0, 0), ++ [RTL_REG_PORT1_PVID] = REG_PORT_PVID(1, 0, 0), ++ [RTL_REG_PORT2_PVID] = REG_PORT_PVID(2, 0, 0), ++ [RTL_REG_PORT3_PVID] = REG_PORT_PVID(3, 0, 0), ++ [RTL_REG_PORT4_PVID] = REG_PORT_PVID(4, 0, 0), ++ [RTL_REG_PORT5_PVID] = REG_PORT_PVID(0, 1, 2), ++}; ++ ++static void rtl_set_page(struct mii_dev *bus, unsigned int page) ++{ ++ u16 pgsel; ++ ++ BUG_ON(page > RTL8306_NUM_PAGES); ++ ++ pgsel = bus->read(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE); ++ pgsel &= ~(RTL8306_REG_PAGE_LO | RTL8306_REG_PAGE_HI); ++ ++ if (page & (1 << 0)) ++ pgsel |= RTL8306_REG_PAGE_LO; ++ ++ if (!(page & (1 << 1))) /* bit is inverted */ ++ pgsel |= RTL8306_REG_PAGE_HI; ++ ++ bus->write(bus, 0, MDIO_DEVAD_NONE, RTL8306_REG_PAGE, pgsel); ++ ++} ++ ++static __maybe_unused int rtl_w16(struct mii_dev *bus, unsigned int page, unsigned int phy, ++ unsigned int reg, u16 val) ++{ ++ rtl_set_page(bus, page); ++ ++ bus->write(bus, phy, MDIO_DEVAD_NONE, reg, val); ++ bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */ ++ ++ return 0; ++} ++ ++static int rtl_r16(struct mii_dev *bus, unsigned int page, unsigned int phy, ++ unsigned int reg) ++{ ++ rtl_set_page(bus, page); ++ ++ return bus->read(bus, phy, MDIO_DEVAD_NONE, reg); ++} ++ ++static u16 rtl_rmw(struct mii_dev *bus, unsigned int page, unsigned int phy, ++ unsigned int reg, u16 mask, u16 val) ++{ ++ u16 r; ++ ++ rtl_set_page(bus, page); ++ ++ r = bus->read(bus, phy, MDIO_DEVAD_NONE, reg); ++ r &= ~mask; ++ r |= val; ++ bus->write(bus, phy, MDIO_DEVAD_NONE, reg, r); ++ ++ return bus->read(bus, phy, MDIO_DEVAD_NONE, reg); /* flush */ ++} ++ ++static int rtl_get(struct mii_dev *bus, enum rtl_regidx s) ++{ ++ const struct rtl_reg *r = &rtl_regs[s]; ++ u16 val; ++ ++ BUG_ON(s >= ARRAY_SIZE(rtl_regs)); ++ ++ if (r->bits == 0) /* unimplemented */ ++ return 0; ++ ++ val = rtl_r16(bus, r->page, r->phy, r->reg); ++ ++ if (r->shift > 0) ++ val >>= r->shift; ++ ++ if (r->inverted) ++ val = ~val; ++ ++ val &= (1 << r->bits) - 1; ++ ++ return val; ++} ++ ++static __maybe_unused int rtl_set(struct mii_dev *bus, enum rtl_regidx s, unsigned int val) ++{ ++ const struct rtl_reg *r = &rtl_regs[s]; ++ u16 mask = 0xffff; ++ ++ BUG_ON(s >= ARRAY_SIZE(rtl_regs)); ++ ++ if (r->bits == 0) /* unimplemented */ ++ return 0; ++ ++ if (r->shift > 0) ++ val <<= r->shift; ++ ++ if (r->inverted) ++ val = ~val; ++ ++ if (r->bits != 16) { ++ mask = (1 << r->bits) - 1; ++ mask <<= r->shift; ++ } ++ ++ val &= mask; ++ ++ return rtl_rmw(bus, r->page, r->phy, r->reg, mask, val); ++} ++ ++static int rtl8306_probe(struct switch_device *dev) ++{ ++ struct mii_dev *bus = dev->bus; ++ unsigned int chipid, chipver, chiptype; ++ ++ chipid = rtl_get(bus, RTL_REG_CHIPID); ++ chipver = rtl_get(bus, RTL_REG_CHIPVER); ++ chiptype = rtl_get(bus, RTL_REG_CHIPTYPE); ++ ++ debug("%s: chipid %x, chipver %x, chiptype %x\n", ++ __func__, chipid, chipver, chiptype); ++ ++ if (chipid == RTL8306_CHIPID) ++ return 0; ++ ++ return 1; ++} ++ ++static void rtl8306_setup(struct switch_device *dev) ++{ ++ struct mii_dev *bus = dev->bus; ++ ++ /* initialize cpu port settings */ ++ rtl_set(bus, RTL_REG_CPUPORT, dev->cpu_port); ++ rtl_set(bus, RTL_REG_EN_CPUPORT, 1); ++ ++ /* enable phy 5 link status */ ++ rtl_set(bus, RTL_REG_CPU_LINKUP, 1); ++// rtl_set(bus, RTL_REG_PORT5_TXEN, 1); ++// rtl_set(bus, RTL_REG_PORT5_RXEN, 1); ++// rtl_set(bus, RTL_REG_PORT5_LRNEN, 1); ++#ifdef DEBUG ++ debug("%s: CPU link up: %i\n", ++ __func__, rtl_get(bus, RTL_REG_PORT5_LINK)); ++#endif ++ ++} ++ ++static struct switch_driver rtl8306_drv = { ++ .name = "rtl8306", ++}; ++ ++void switch_rtl8306_init(void) ++{ ++ /* For archs with manual relocation */ ++ rtl8306_drv.probe = rtl8306_probe; ++ rtl8306_drv.setup = rtl8306_setup; ++ ++ switch_driver_register(&rtl8306_drv); ++} +diff --git a/drivers/net/switch/switch.c b/drivers/net/switch/switch.c +index 3e34a7f..2e1c668 100644 +--- a/drivers/net/switch/switch.c ++++ b/drivers/net/switch/switch.c +@@ -26,6 +26,9 @@ void switch_init(void) + #if defined(CONFIG_SWITCH_AR8216) + switch_ar8216_init(); + #endif ++#if defined(CONFIG_SWITCH_RTL8306) ++ switch_rtl8306_init(); ++#endif + + board_switch_init(); + } +diff --git a/include/switch.h b/include/switch.h +index ae7b123..927b1d2 100644 +--- a/include/switch.h ++++ b/include/switch.h +@@ -100,6 +100,7 @@ static inline void switch_setup(struct switch_device *dev) + extern void switch_psb697x_init(void); + extern void switch_adm6996i_init(void); + extern void switch_ar8216_init(void); ++extern void switch_rtl8306_init(void); + + #endif /* __SWITCH_H */ + +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0013-sf-macronix-add-support-for-4-byte-address-mode.patch b/package/boot/uboot-lantiq/patches/0013-sf-macronix-add-support-for-4-byte-address-mode.patch deleted file mode 100644 index 70015c9..0000000 --- a/package/boot/uboot-lantiq/patches/0013-sf-macronix-add-support-for-4-byte-address-mode.patch +++ /dev/null @@ -1,44 +0,0 @@ -From 207662a9270cc542709fbab0d25fbc361b39748c Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 15:13:49 +0100 -Subject: sf: macronix: add support for 4-byte address mode - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/macronix.c -+++ b/drivers/mtd/spi/macronix.c -@@ -35,6 +35,8 @@ - - #include "spi_flash_internal.h" - -+#define MX25XX_EN4B 0xb7 /* Enter 4-byte mode */ -+ - struct macronix_spi_flash_params { - u16 idcode; - u16 nr_blocks; -@@ -79,6 +81,13 @@ static const struct macronix_spi_flash_p - }, - }; - -+static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash) -+{ -+ struct spi_slave *spi = flash->spi; -+ -+ return spi_flash_cmd(spi, MX25XX_EN4B, NULL, 0); -+} -+ - int spi_flash_probe_macronix(struct spi_flash *flash, u8 *idcode) - { - const struct macronix_spi_flash_params *params; -@@ -106,6 +115,11 @@ int spi_flash_probe_macronix(struct spi_ - flash->sector_size = 256 * 16 * 16; - flash->size = flash->sector_size * params->nr_blocks; - -+#ifdef CONFIG_SPI_FLASH_4BYTE_MODE -+ if (flash->size > (1 << 24)) -+ flash->set_4byte_mode = macronix_set_4byte_mode; -+#endif -+ - /* Clear BP# bits for read-only flash */ - spi_flash_cmd_write_status(flash, 0); - diff --git a/package/boot/uboot-lantiq/patches/0023-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch index 2582c16..6f3be69 100644 --- a/package/boot/uboot-lantiq/patches/0023-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch +++ b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch @@ -1,16 +1,19 @@ -From ed2effe0839929d00f05ec0e1e16fb467f324e1b Mon Sep 17 00:00:00 2001 +From 11553b0de8992ded6240d034bd49f561d17bea53 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Thu, 20 Dec 2012 19:05:54 +0100 +Date: Thu, 13 Jun 2013 01:18:02 +0200 Subject: MIPS: add support for Lantiq XWAY SoCs +Signed-off-by: Luka Perkov <luka@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/.gitignore b/.gitignore +index a39bd54..7abdc37 100644 --- a/.gitignore +++ b/.gitignore -@@ -44,6 +44,13 @@ +@@ -49,6 +49,13 @@ /u-boot.sb + /u-boot.bd /u-boot.geany - /include/u-boot.lst +/u-boot.bin.lzma +/u-boot.bin.lzo +/u-boot.ltq.lzma.norspl @@ -21,9 +24,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> # # Generated files +diff --git a/Makefile b/Makefile +index 6ee9a3c..73ec67d 100644 --- a/Makefile +++ b/Makefile -@@ -441,6 +441,12 @@ $(obj)u-boot.bin: $(obj)u-boot +@@ -435,6 +435,12 @@ $(obj)u-boot.bin: $(obj)u-boot $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ $(BOARD_SIZE_CHECK) @@ -36,7 +41,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> $(obj)u-boot.ldr: $(obj)u-boot $(CREATE_LDR_ENV) $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS) -@@ -460,13 +466,23 @@ ifndef CONFIG_SYS_UBOOT_START +@@ -454,13 +460,23 @@ ifndef CONFIG_SYS_UBOOT_START CONFIG_SYS_UBOOT_START := 0 endif @@ -60,11 +65,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +$(obj)u-boot.lzo.img: $(obj)u-boot.bin.lzo + $(call GEN_UBOOT_IMAGE,lzo) - $(obj)u-boot.imx: $(obj)u-boot.bin - $(obj)tools/mkimage -n $(CONFIG_IMX_CONFIG) -T imximage \ -@@ -549,6 +565,27 @@ endif - $(obj)u-boot-img.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img - cat $(obj)spl/u-boot-spl.bin $(obj)u-boot.img > $@ + $(obj)u-boot.imx: $(obj)u-boot.bin depend + $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx +@@ -571,6 +587,27 @@ $(obj)u-boot-img-spl-at-end.bin: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img + conv=notrunc 2>/dev/null + cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@ +$(obj)u-boot.ltq.sfspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \ @@ -90,9 +95,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ifeq ($(CONFIG_SANDBOX),y) GEN_UBOOT = \ cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \ +diff --git a/README b/README +index 09662a4..1acceff 100644 --- a/README +++ b/README -@@ -460,6 +460,11 @@ The following options need to be configu +@@ -468,6 +468,11 @@ The following options need to be configured: CONF_CM_CACHABLE_CUW CONF_CM_CACHABLE_ACCELERATED @@ -104,23 +111,31 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> CONFIG_SYS_XWAY_EBU_BOOTCFG Special option for Lantiq XWAY SoCs for booting from NOR flash. +diff --git a/arch/mips/config.mk b/arch/mips/config.mk +index c3f81b5..84b6e59 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk -@@ -61,7 +61,10 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__M +@@ -45,9 +45,13 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS) +PF_ABICALLS ?= -mabicalls +PF_PIC ?= -fpic ++PF_PIE ?= -pie + +PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC) $(ENDIANNESS) PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS) PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +-LDFLAGS_FINAL += --gc-sections -pie ++LDFLAGS_FINAL += --gc-sections $(PF_PIE) + OBJCFLAGS += --remove-section=.dynsym +diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S +index 12f656c..8620a9d 100644 --- a/arch/mips/cpu/mips32/cache.S +++ b/arch/mips/cpu/mips32/cache.S -@@ -45,7 +45,11 @@ +@@ -29,7 +29,11 @@ */ #define MIPS_MAX_CACHE_SIZE 0x10000 @@ -132,7 +147,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> .macro cache_op op addr .set push -@@ -81,7 +85,11 @@ +@@ -65,7 +69,11 @@ */ LEAF(mips_init_icache) blez a1, 9f @@ -144,7 +159,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> /* clear tag to invalidate */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 -@@ -106,7 +114,11 @@ LEAF(mips_init_icache) +@@ -90,7 +98,11 @@ LEAF(mips_init_icache) */ LEAF(mips_init_dcache) blez a1, 9f @@ -156,15 +171,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> /* clear all tags */ PTR_LI t0, INDEX_BASE PTR_ADDU t1, t0, a1 +diff --git a/arch/mips/cpu/mips32/danube/Makefile b/arch/mips/cpu/mips32/danube/Makefile +new file mode 100644 +index 0000000..98f5f73 --- /dev/null +++ b/arch/mips/cpu/mips32/danube/Makefile -@@ -0,0 +1,33 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,31 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -192,15 +208,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/arch/mips/cpu/mips32/danube/cgu.c b/arch/mips/cpu/mips32/danube/cgu.c +new file mode 100644 +index 0000000..4fd110a --- /dev/null +++ b/arch/mips/cpu/mips32/danube/cgu.c -@@ -0,0 +1,118 @@ +@@ -0,0 +1,117 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -313,15 +331,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return clk; +} +diff --git a/arch/mips/cpu/mips32/danube/cgu_init.S b/arch/mips/cpu/mips32/danube/cgu_init.S +new file mode 100644 +index 0000000..e0922f1 --- /dev/null +++ b/arch/mips/cpu/mips32/danube/cgu_init.S -@@ -0,0 +1,143 @@ +@@ -0,0 +1,142 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> @@ -459,14 +479,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + jr ra + + END(ltq_cgu_init) +diff --git a/arch/mips/cpu/mips32/danube/chipid.c b/arch/mips/cpu/mips32/danube/chipid.c +new file mode 100644 +index 0000000..02d9554 --- /dev/null +++ b/arch/mips/cpu/mips32/danube/chipid.c -@@ -0,0 +1,60 @@ +@@ -0,0 +1,59 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -522,14 +544,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return ""; +} +diff --git a/arch/mips/cpu/mips32/danube/config.mk b/arch/mips/cpu/mips32/danube/config.mk +new file mode 100644 +index 0000000..cee376f --- /dev/null +++ b/arch/mips/cpu/mips32/danube/config.mk -@@ -0,0 +1,27 @@ +@@ -0,0 +1,25 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com +# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# SPDX-License-Identifier: GPL-2.0+ +# + +PF_CPPFLAGS_DANUBE := $(call cc-option,-mtune=24kec,) @@ -538,6 +562,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +ifdef CONFIG_SPL_BUILD +PF_ABICALLS := -mno-abicalls +PF_PIC := -fno-pic ++PF_PIE := +USE_PRIVATE_LIBGCC := yes +endif + @@ -550,25 +575,59 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl +endif +endif -+ -+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot.lds +diff --git a/arch/mips/cpu/mips32/danube/ebu.c b/arch/mips/cpu/mips32/danube/ebu.c +new file mode 100644 +index 0000000..902f6a7 --- /dev/null +++ b/arch/mips/cpu/mips32/danube/ebu.c -@@ -0,0 +1,51 @@ +@@ -0,0 +1,105 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/soc.h> +#include <asm/lantiq/io.h> + -+#define LTQ_EBU_CON_0_RST_VAL 0x8001F7FF ++#define EBU_ADDRSEL_MASK(mask) ((mask & 0xf) << 4) ++#define EBU_ADDRSEL_REGEN (1 << 0) ++ ++#define EBU_CON_WRDIS (1 << 31) ++#define EBU_CON_AGEN_DEMUX (0x0 << 24) ++#define EBU_CON_AGEN_MUX (0x2 << 24) ++#define EBU_CON_SETUP (1 << 22) ++#define EBU_CON_WAIT_DIS (0x0 << 20) ++#define EBU_CON_WAIT_ASYNC (0x1 << 20) ++#define EBU_CON_WAIT_SYNC (0x2 << 20) ++#define EBU_CON_WINV (1 << 19) ++#define EBU_CON_PW_8BIT (0x0 << 16) ++#define EBU_CON_PW_16BIT (0x1 << 16) ++#define EBU_CON_ALEC(cycles) ((cycles & 0x3) << 14) ++#define EBU_CON_BCGEN_CS (0x0 << 12) ++#define EBU_CON_BCGEN_INTEL (0x1 << 12) ++#define EBU_CON_BCGEN_MOTOROLA (0x2 << 12) ++#define EBU_CON_WAITWRC(cycles) ((cycles & 0x7) << 8) ++#define EBU_CON_WAITRDC(cycles) ((cycles & 0x3) << 6) ++#define EBU_CON_HOLDC(cycles) ((cycles & 0x3) << 4) ++#define EBU_CON_RECOVC(cycles) ((cycles & 0x3) << 2) ++#define EBU_CON_CMULT_1 0x0 ++#define EBU_CON_CMULT_4 0x1 ++#define EBU_CON_CMULT_8 0x2 ++#define EBU_CON_CMULT_16 0x3 ++ ++#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) ++#define ebu_region0_enable 1 ++#else ++#define ebu_region0_enable 0 ++#endif + -+#define LTQ_EBU_CON_WRDIS (1 << 31) ++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) ++#define ebu_region1_enable 1 ++#else ++#define ebu_region1_enable 0 ++#endif + +struct ltq_ebu_regs { + u32 clc; @@ -587,33 +646,56 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +void ltq_ebu_init(void) +{ -+ /* -+ * Map EBU region 0 to range 0x10000000-0x13ffffff and enable -+ * region control. This supports up to 32 MiB NOR flash in -+ * bank 0. -+ */ -+ ltq_writel(<q_ebu_regs->addr_sel_0, 0x10000011); ++ if (ebu_region0_enable) { ++ /* ++ * Map EBU region 0 to range 0x10000000-0x13ffffff and enable ++ * region control. This supports up to 32 MiB NOR flash in ++ * bank 0. ++ */ ++ ltq_writel(<q_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE | ++ EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN); + -+ /* -+ * Restore reset value to fix modifications by internal BootROM. -+ * Also disable write protection. -+ */ -+ ltq_writel(<q_ebu_regs->con_0, -+ LTQ_EBU_CON_0_RST_VAL & ~LTQ_EBU_CON_WRDIS); ++ ltq_writel(<q_ebu_regs->con_0, EBU_CON_AGEN_DEMUX | ++ EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT | ++ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL | ++ EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) | ++ EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) | ++ EBU_CON_CMULT_16); ++ } else ++ ltq_clrbits(<q_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN); ++ ++ if (ebu_region1_enable) { ++ /* ++ * Map EBU region 1 to range 0x14000000-0x13ffffff and enable ++ * region control. This supports NAND flash in bank 1. ++ */ ++ ltq_writel(<q_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE | ++ EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN); ++ ++ ltq_writel(<q_ebu_regs->con_1, EBU_CON_AGEN_DEMUX | ++ EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT | ++ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL | ++ EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) | ++ EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) | ++ EBU_CON_CMULT_4); ++ } else ++ ltq_clrbits(<q_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN); +} + +void *flash_swap_addr(unsigned long addr) +{ + return (void *)(addr ^ 2); +} +diff --git a/arch/mips/cpu/mips32/danube/mem.c b/arch/mips/cpu/mips32/danube/mem.c +new file mode 100644 +index 0000000..be1922c --- /dev/null +++ b/arch/mips/cpu/mips32/danube/mem.c -@@ -0,0 +1,31 @@ +@@ -0,0 +1,30 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -640,15 +722,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return (1 << (row + col)) * 4 * 2; +} +diff --git a/arch/mips/cpu/mips32/danube/mem_init.S b/arch/mips/cpu/mips32/danube/mem_init.S +new file mode 100644 +index 0000000..47a35e1 --- /dev/null +++ b/arch/mips/cpu/mips32/danube/mem_init.S -@@ -0,0 +1,115 @@ +@@ -0,0 +1,114 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> @@ -758,14 +842,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + jr ra + + END(ltq_mem_init) +diff --git a/arch/mips/cpu/mips32/danube/pmu.c b/arch/mips/cpu/mips32/danube/pmu.c +new file mode 100644 +index 0000000..7dd8aea --- /dev/null +++ b/arch/mips/cpu/mips32/danube/pmu.c -@@ -0,0 +1,118 @@ +@@ -0,0 +1,117 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -879,14 +965,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + ltq_clrsetbits(<q_pmu_regs->pwdcr, clr, set); +} +diff --git a/arch/mips/cpu/mips32/danube/rcu.c b/arch/mips/cpu/mips32/danube/rcu.c +new file mode 100644 +index 0000000..906491a --- /dev/null +++ b/arch/mips/cpu/mips32/danube/rcu.c -@@ -0,0 +1,126 @@ +@@ -0,0 +1,125 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -1008,87 +1096,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + return BOOT_UNKNOWN; + } +} ---- /dev/null -+++ b/arch/mips/cpu/mips32/danube/u-boot.lds -@@ -0,0 +1,69 @@ -+/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * -+ * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ */ -+ -+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") -+OUTPUT_ARCH(mips) -+ENTRY(_start) -+SECTIONS -+{ -+ . = 0x00000000; -+ -+ . = ALIGN(4); -+ .text : { -+ *(.text*) -+ } -+ -+ . = ALIGN(4); -+ .rodata : { -+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -+ } -+ -+ . = ALIGN(4); -+ .data : { -+ *(.data*) -+ } -+ -+ . = ALIGN(4); -+ .sdata : { -+ *(.sdata*) -+ } -+ -+ . = .; -+ _gp = ALIGN(16) + 0x7ff0; -+ -+ .got : { -+ __got_start = .; -+ *(.got) -+ __got_end = .; -+ } -+ -+ num_got_entries = (__got_end - __got_start) >> 2; -+ -+#ifndef CONFIG_SPL_BUILD -+ . = ALIGN(4); -+ .u_boot_list : { -+ #include <u-boot.lst> -+ } -+#endif -+ -+ . = ALIGN(4); -+ __image_copy_end = .; -+ uboot_end_data = .; -+ -+ .bss (NOLOAD) : { -+ __bss_start = .; -+ *(.bss*) -+ *(.sbss*) -+ . = ALIGN(4); -+ __bss_end = .; -+ } -+ -+ . = ALIGN(4); -+ __end = .; -+ uboot_end = .; -+} +diff --git a/arch/mips/cpu/mips32/lantiq-common/Makefile b/arch/mips/cpu/mips32/lantiq-common/Makefile +new file mode 100644 +index 0000000..260d67c --- /dev/null +++ b/arch/mips/cpu/mips32/lantiq-common/Makefile -@@ -0,0 +1,36 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,34 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -1119,14 +1136,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/arch/mips/cpu/mips32/lantiq-common/cpu.c b/arch/mips/cpu/mips32/lantiq-common/cpu.c +new file mode 100644 +index 0000000..4a7acdf --- /dev/null +++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c -@@ -0,0 +1,60 @@ +@@ -0,0 +1,59 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -1182,14 +1201,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + ltq_reset_activate(LTQ_RESET_CORE); +} +diff --git a/arch/mips/cpu/mips32/lantiq-common/lowlevel_init.S b/arch/mips/cpu/mips32/lantiq-common/lowlevel_init.S +new file mode 100644 +index 0000000..ad03b04 --- /dev/null +++ b/arch/mips/cpu/mips32/lantiq-common/lowlevel_init.S -@@ -0,0 +1,21 @@ +@@ -0,0 +1,20 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/asm.h> @@ -1206,27 +1227,31 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + jr t8 + END(lowlevel_init) +diff --git a/arch/mips/cpu/mips32/lantiq-common/pmu.c b/arch/mips/cpu/mips32/lantiq-common/pmu.c +new file mode 100644 +index 0000000..8f0dac1 --- /dev/null +++ b/arch/mips/cpu/mips32/lantiq-common/pmu.c -@@ -0,0 +1,10 @@ +@@ -0,0 +1,9 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/lantiq/pm.h> + +diff --git a/arch/mips/cpu/mips32/lantiq-common/spl.c b/arch/mips/cpu/mips32/lantiq-common/spl.c +new file mode 100644 +index 0000000..489a82b --- /dev/null +++ b/arch/mips/cpu/mips32/lantiq-common/spl.c -@@ -0,0 +1,385 @@ +@@ -0,0 +1,403 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -1249,6 +1274,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +#else +#define spl_has_console 0 ++#define spl_has_debug 0 +#endif + +#define spl_debug(fmt, args...) \ @@ -1292,13 +1318,12 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +struct spl_image { + ulong data_addr; + ulong entry_addr; -+ size_t data_size; -+ size_t entry_size; ++ ulong data_size; ++ ulong entry_size; ++ ulong data_crc; + u8 comp; +}; + -+extern ulong __image_copy_end; -+ +DECLARE_GLOBAL_DATA_PTR; + +/* Emulated malloc area needed for LZMA allocator in BSS */ @@ -1352,25 +1377,42 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +static int spl_parse_image(const image_header_t *hdr, struct spl_image *spl) +{ -+ u32 magic; -+ + spl_puts("SPL: checking U-Boot image\n"); + -+ magic = image_get_magic(hdr); -+ if (magic != IH_MAGIC) ++ if (!image_check_magic(hdr)) { ++ spl_puts("SPL: invalid magic\n"); + return -1; ++ } ++ ++ if (!image_check_hcrc(hdr)) { ++ spl_puts("SPL: invalid header CRC\n"); ++ return -1; ++ } + + spl->data_addr += image_get_header_size(); + spl->entry_addr = image_get_load(hdr); + spl->data_size = image_get_data_size(hdr); ++ spl->data_crc = image_get_dcrc(hdr); + spl->comp = image_get_comp(hdr); + -+ spl_debug("SPL: data %08lx, size %zu, entry %08lx, comp %u\n", ++ spl_debug("SPL: data %08lx, size %lu, entry %08lx, comp %u\n", + spl->data_addr, spl->data_size, spl->entry_addr, spl->comp); + + return 0; +} + ++static int spl_check_data(const struct spl_image *spl, ulong loadaddr) ++{ ++ ulong dcrc = crc32(0, (unsigned char *)loadaddr, spl->data_size); ++ ++ if (dcrc != spl->data_crc) { ++ spl_puts("SPL: invalid data CRC\n"); ++ return 0; ++ } ++ ++ return 1; ++} ++ +static void *spl_lzma_alloc(void *p, size_t size) +{ + u8 *ret; @@ -1462,7 +1504,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +static int spl_load_spi_flash(struct spl_image *spl) +{ -+ struct spi_flash sf; ++ struct spi_flash sf = { 0 }; + image_header_t hdr; + int ret; + unsigned long loadaddr; @@ -1476,13 +1518,12 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + * - 64 byte U-Boot mkimage header + * - U-Boot binary + */ -+ spl->data_addr = (ulong) &__image_copy_end - CONFIG_SPL_TEXT_BASE + 24; ++ spl->data_addr = image_copy_end() - CONFIG_SPL_TEXT_BASE + 24; + + spl_puts("SPL: probing SPI flash\n"); + + spi_init(); -+ ret = spi_flash_probe_spl(&sf, CONFIG_SPL_SPI_BUS, CONFIG_SPL_SPI_CS, -+ CONFIG_SPL_SPI_MAX_HZ, CONFIG_SPL_SPI_MODE); ++ ret = spl_spi_flash_probe(&sf); + if (ret) + return ret; + @@ -1508,6 +1549,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + ret = spi_flash_read(&sf, spl->data_addr, spl->data_size, + (void *) loadaddr); + ++ if (!spl_check_data(spl, loadaddr)) ++ return -1; ++ + if (spl_is_compressed(spl)) + ret = spl_uncompress(spl, loadaddr); + @@ -1526,8 +1570,8 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + * - 64 byte U-Boot mkimage header + * - U-Boot binary + */ -+ spl->data_addr = (ulong) &__image_copy_end; -+ hdr = (const image_header_t *) &__image_copy_end; ++ spl->data_addr = image_copy_end(); ++ hdr = (const image_header_t *) image_copy_end(); + + spl_debug("SPL: checking image header at address %p\n", hdr); + @@ -1607,15 +1651,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + for (;;) + ; +} +diff --git a/arch/mips/cpu/mips32/lantiq-common/start.S b/arch/mips/cpu/mips32/lantiq-common/start.S +new file mode 100644 +index 0000000..481d739 --- /dev/null +++ b/arch/mips/cpu/mips32/lantiq-common/start.S -@@ -0,0 +1,144 @@ +@@ -0,0 +1,143 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2003 Wolfgang Denk, wd@denx.de -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> @@ -1754,14 +1800,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + la t9, spl_lantiq_init + jr t9 + nop +diff --git a/arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds b/arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds +new file mode 100644 +index 0000000..97c8fa8 --- /dev/null +++ b/arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds -@@ -0,0 +1,49 @@ +@@ -0,0 +1,48 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \ @@ -1806,229 +1854,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + __end = .; + uboot_end = .; +} +diff --git a/arch/mips/cpu/mips32/start.S b/arch/mips/cpu/mips32/start.S +index 70ad198..091a4e2 100644 --- a/arch/mips/cpu/mips32/start.S +++ b/arch/mips/cpu/mips32/start.S -@@ -55,166 +55,63 @@ - #endif - .endm - --#define RVECENT(f,n) \ -- b f; nop --#define XVECENT(f,bev) \ -- b f ; \ -- li k0,bev -- -- .set noreorder -- -- .globl _start -- .text --_start: -- RVECENT(reset,0) # U-boot entry point -- RVECENT(reset,1) # software reboot --#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG - /* - * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to - * access external NOR flashes. If the board boots from NOR flash the - * internal BootROM does a blind read at address 0xB0000010 to read the - * initial configuration for that EBU in order to access the flash - * device with correct parameters. This config option is board-specific. -+ * Default to 0 if this option is not set. - */ -- .word CONFIG_SYS_XWAY_EBU_BOOTCFG -- .word 0x00000000 -+ .macro lantiq_soc_bootcfg -+ .set push -+ .set noreorder -+ .org 0x10 -+#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG -+ .word CONFIG_SYS_XWAY_EBU_BOOTCFG - #else -- RVECENT(romReserved,2) -+ .word 0 - #endif -- RVECENT(romReserved,3) -- RVECENT(romReserved,4) -- RVECENT(romReserved,5) -- RVECENT(romReserved,6) -- RVECENT(romReserved,7) -- RVECENT(romReserved,8) -- RVECENT(romReserved,9) -- RVECENT(romReserved,10) -- RVECENT(romReserved,11) -- RVECENT(romReserved,12) -- RVECENT(romReserved,13) -- RVECENT(romReserved,14) -- RVECENT(romReserved,15) -- RVECENT(romReserved,16) -- RVECENT(romReserved,17) -- RVECENT(romReserved,18) -- RVECENT(romReserved,19) -- RVECENT(romReserved,20) -- RVECENT(romReserved,21) -- RVECENT(romReserved,22) -- RVECENT(romReserved,23) -- RVECENT(romReserved,24) -- RVECENT(romReserved,25) -- RVECENT(romReserved,26) -- RVECENT(romReserved,27) -- RVECENT(romReserved,28) -- RVECENT(romReserved,29) -- RVECENT(romReserved,30) -- RVECENT(romReserved,31) -- RVECENT(romReserved,32) -- RVECENT(romReserved,33) -- RVECENT(romReserved,34) -- RVECENT(romReserved,35) -- RVECENT(romReserved,36) -- RVECENT(romReserved,37) -- RVECENT(romReserved,38) -- RVECENT(romReserved,39) -- RVECENT(romReserved,40) -- RVECENT(romReserved,41) -- RVECENT(romReserved,42) -- RVECENT(romReserved,43) -- RVECENT(romReserved,44) -- RVECENT(romReserved,45) -- RVECENT(romReserved,46) -- RVECENT(romReserved,47) -- RVECENT(romReserved,48) -- RVECENT(romReserved,49) -- RVECENT(romReserved,50) -- RVECENT(romReserved,51) -- RVECENT(romReserved,52) -- RVECENT(romReserved,53) -- RVECENT(romReserved,54) -- RVECENT(romReserved,55) -- RVECENT(romReserved,56) -- RVECENT(romReserved,57) -- RVECENT(romReserved,58) -- RVECENT(romReserved,59) -- RVECENT(romReserved,60) -- RVECENT(romReserved,61) -- RVECENT(romReserved,62) -- RVECENT(romReserved,63) -- XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector -- RVECENT(romReserved,65) -- RVECENT(romReserved,66) -- RVECENT(romReserved,67) -- RVECENT(romReserved,68) -- RVECENT(romReserved,69) -- RVECENT(romReserved,70) -- RVECENT(romReserved,71) -- RVECENT(romReserved,72) -- RVECENT(romReserved,73) -- RVECENT(romReserved,74) -- RVECENT(romReserved,75) -- RVECENT(romReserved,76) -- RVECENT(romReserved,77) -- RVECENT(romReserved,78) -- RVECENT(romReserved,79) -- XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector -- RVECENT(romReserved,81) -- RVECENT(romReserved,82) -- RVECENT(romReserved,83) -- RVECENT(romReserved,84) -- RVECENT(romReserved,85) -- RVECENT(romReserved,86) -- RVECENT(romReserved,87) -- RVECENT(romReserved,88) -- RVECENT(romReserved,89) -- RVECENT(romReserved,90) -- RVECENT(romReserved,91) -- RVECENT(romReserved,92) -- RVECENT(romReserved,93) -- RVECENT(romReserved,94) -- RVECENT(romReserved,95) -- XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector -- RVECENT(romReserved,97) -- RVECENT(romReserved,98) -- RVECENT(romReserved,99) -- RVECENT(romReserved,100) -- RVECENT(romReserved,101) -- RVECENT(romReserved,102) -- RVECENT(romReserved,103) -- RVECENT(romReserved,104) -- RVECENT(romReserved,105) -- RVECENT(romReserved,106) -- RVECENT(romReserved,107) -- RVECENT(romReserved,108) -- RVECENT(romReserved,109) -- RVECENT(romReserved,110) -- RVECENT(romReserved,111) -- XVECENT(romExcHandle,0x380) # bfc00380: R4000 general vector -- RVECENT(romReserved,113) -- RVECENT(romReserved,114) -- RVECENT(romReserved,115) -- RVECENT(romReserved,116) -- RVECENT(romReserved,116) -- RVECENT(romReserved,118) -- RVECENT(romReserved,119) -- RVECENT(romReserved,120) -- RVECENT(romReserved,121) -- RVECENT(romReserved,122) -- RVECENT(romReserved,123) -- RVECENT(romReserved,124) -- RVECENT(romReserved,125) -- RVECENT(romReserved,126) -- RVECENT(romReserved,127) -+ .word 0 -+ .set pop -+ .endm -+ -+ .macro reset_vector branch -+ .set push -+ .set noreorder -+ b \branch -+ nop -+ .set pop -+ .endm -+ -+ .macro exception_vector offset branch -+ .set push -+ .set noreorder -+ .org \offset -+ b \branch -+ li k0, \offset -+ .set pop -+ .endm -+ -+ .set noreorder -+ -+ .globl _start -+ .text -+_start: -+ reset_vector reset # U-boot entry point -+ reset_vector reset # software reboot -+ -+ lantiq_soc_bootcfg # Lantiq SoC Boot config word -+ -+ exception_vector 0x200, halt # TLB miss -+ exception_vector 0x280, halt # XTLB miss -+ exception_vector 0x300, halt # Cache error -+ exception_vector 0x380, halt # General -+ exception_vector 0x400, halt # Interrupt, CauseIV -+ exception_vector 0x480, ejtag_exception # EJTAG debug - -- /* -- * We hope there are no more reserved vectors! -- * 128 * 8 == 1024 == 0x400 -- * so this is address R_VEC+0x400 == 0xbfc00400 -- */ - .align 4 - reset: -- - /* Clear watch registers */ - mtc0 zero, CP0_WATCHLO - mtc0 zero, CP0_WATCHHI -@@ -222,13 +119,15 @@ reset: - /* WP(Watch Pending), SW0/1 should be cleared */ - mtc0 zero, CP0_CAUSE - -+#if 0 - setup_c0_status_reset -+#endif - - /* Init Timer */ +@@ -105,7 +105,7 @@ reset: mtc0 zero, CP0_COUNT mtc0 zero, CP0_COMPARE @@ -2037,41 +1867,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> /* CONFIG0 register */ li t0, CONF_CM_UNCACHED mtc0 t0, CP0_CONFIG -@@ -323,6 +222,8 @@ relocate_code: - jalr t9 - nop - -+ sync -+ - /* Jump to where we've relocated ourselves */ - addi t0, s2, in_ram - _start - jr t0 -@@ -378,8 +279,12 @@ in_ram: - .end relocate_code - - /* Exception handlers */ --romReserved: -- b romReserved -+ejtag_exception: -+ /* Set DEPC to halt and exit debug mode */ -+ la k1, halt -+ mtc0 k1, CP0_DEPC -+ deret -+ nop - --romExcHandle: -- b romExcHandle -+halt: -+ b halt +diff --git a/arch/mips/cpu/mips32/vrx200/Makefile b/arch/mips/cpu/mips32/vrx200/Makefile +new file mode 100644 +index 0000000..714dc69 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/Makefile -@@ -0,0 +1,34 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,32 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -2100,15 +1905,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/arch/mips/cpu/mips32/vrx200/cgu.c b/arch/mips/cpu/mips32/vrx200/cgu.c +new file mode 100644 +index 0000000..799c902 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/cgu.c -@@ -0,0 +1,209 @@ +@@ -0,0 +1,208 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -2312,15 +2119,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + ltq_cgu_pll1_init(); +} +diff --git a/arch/mips/cpu/mips32/vrx200/cgu_init.S b/arch/mips/cpu/mips32/vrx200/cgu_init.S +new file mode 100644 +index 0000000..190ef89 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/cgu_init.S -@@ -0,0 +1,120 @@ +@@ -0,0 +1,119 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> @@ -2435,14 +2244,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + nop + + END(ltq_cgu_init) +diff --git a/arch/mips/cpu/mips32/vrx200/chipid.c b/arch/mips/cpu/mips32/vrx200/chipid.c +new file mode 100644 +index 0000000..f916e87 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/chipid.c -@@ -0,0 +1,63 @@ +@@ -0,0 +1,62 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -2501,14 +2312,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return ""; +} +diff --git a/arch/mips/cpu/mips32/vrx200/config.mk b/arch/mips/cpu/mips32/vrx200/config.mk +new file mode 100644 +index 0000000..442156a --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/config.mk -@@ -0,0 +1,32 @@ +@@ -0,0 +1,30 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com +# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# SPDX-License-Identifier: GPL-2.0+ +# + +PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,) @@ -2517,6 +2330,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +ifdef CONFIG_SPL_BUILD +PF_ABICALLS := -mno-abicalls +PF_PIC := -fno-pic ++PF_PIE := +USE_PRIVATE_LIBGCC := yes +endif + @@ -2534,17 +2348,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl +endif +endif -+ -+LDSCRIPT := $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot.lds +diff --git a/arch/mips/cpu/mips32/vrx200/dcdc.c b/arch/mips/cpu/mips32/vrx200/dcdc.c +new file mode 100644 +index 0000000..11ca0d7 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/dcdc.c -@@ -0,0 +1,107 @@ +@@ -0,0 +1,106 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -2646,14 +2460,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + __udelay(1000); + } +} +diff --git a/arch/mips/cpu/mips32/vrx200/ebu.c b/arch/mips/cpu/mips32/vrx200/ebu.c +new file mode 100644 +index 0000000..4ab3cf1 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/ebu.c -@@ -0,0 +1,112 @@ +@@ -0,0 +1,111 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -2761,14 +2577,32 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + return (void *)(addr ^ 2); +} +diff --git a/arch/mips/cpu/mips32/vrx200/fw_phy11g_a1x.blob b/arch/mips/cpu/mips32/vrx200/fw_phy11g_a1x.blob +new file mode 100644 +index 0000000..cdf3d30 +Binary files /dev/null and b/arch/mips/cpu/mips32/vrx200/fw_phy11g_a1x.blob differ +diff --git a/arch/mips/cpu/mips32/vrx200/fw_phy11g_a2x.blob b/arch/mips/cpu/mips32/vrx200/fw_phy11g_a2x.blob +new file mode 100644 +index 0000000..1559081 +Binary files /dev/null and b/arch/mips/cpu/mips32/vrx200/fw_phy11g_a2x.blob differ +diff --git a/arch/mips/cpu/mips32/vrx200/fw_phy22f_a1x.blob b/arch/mips/cpu/mips32/vrx200/fw_phy22f_a1x.blob +new file mode 100644 +index 0000000..02b88a0 +Binary files /dev/null and b/arch/mips/cpu/mips32/vrx200/fw_phy22f_a1x.blob differ +diff --git a/arch/mips/cpu/mips32/vrx200/fw_phy22f_a2x.blob b/arch/mips/cpu/mips32/vrx200/fw_phy22f_a2x.blob +new file mode 100644 +index 0000000..eeab2ab +Binary files /dev/null and b/arch/mips/cpu/mips32/vrx200/fw_phy22f_a2x.blob differ +diff --git a/arch/mips/cpu/mips32/vrx200/gphy.c b/arch/mips/cpu/mips32/vrx200/gphy.c +new file mode 100644 +index 0000000..269ca5d --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/gphy.c -@@ -0,0 +1,59 @@ +@@ -0,0 +1,58 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -2823,45 +2657,49 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + ltq_gphy_copy(&__ltq_fw_phy22f_a2x_start, &__ltq_fw_phy22f_a2x_end, + addr); +} +diff --git a/arch/mips/cpu/mips32/vrx200/gphy_fw.S b/arch/mips/cpu/mips32/vrx200/gphy_fw.S +new file mode 100644 +index 0000000..3a0417a --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/gphy_fw.S -@@ -0,0 +1,28 @@ +@@ -0,0 +1,27 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/asm.h> + + .section .rodata.__ltq_fw_phy11g_a1x +EXPORT(__ltq_fw_phy11g_a1x_start) -+ .incbin "fw_phy11g_a1x.bin" ++ .incbin "fw_phy11g_a1x.blob" +EXPORT(__ltq_fw_phy11g_a1x_end) + + .section .rodata.__ltq_fw_phy11g_a2x +EXPORT(__ltq_fw_phy11g_a2x_start) -+ .incbin "fw_phy11g_a2x.bin" ++ .incbin "fw_phy11g_a2x.blob" +EXPORT(__ltq_fw_phy11g_a2x_end) + + .section .rodata.__ltq_fw_phy22f_a1x +EXPORT(__ltq_fw_phy22f_a1x_start) -+ .incbin "fw_phy22f_a1x.bin" ++ .incbin "fw_phy22f_a1x.blob" +EXPORT(__ltq_fw_phy22f_a1x_end) + + .section .rodata.__ltq_fw_phy22f_a2x +EXPORT(__ltq_fw_phy22f_a2x_start) -+ .incbin "fw_phy22f_a2x.bin" ++ .incbin "fw_phy22f_a2x.blob" +EXPORT(__ltq_fw_phy22f_a2x_end) +diff --git a/arch/mips/cpu/mips32/vrx200/mem.c b/arch/mips/cpu/mips32/vrx200/mem.c +new file mode 100644 +index 0000000..c3e14ab --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/mem.c -@@ -0,0 +1,58 @@ +@@ -0,0 +1,57 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -2915,15 +2753,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return size; +} +diff --git a/arch/mips/cpu/mips32/vrx200/mem_init.S b/arch/mips/cpu/mips32/vrx200/mem_init.S +new file mode 100644 +index 0000000..a296845 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/mem_init.S -@@ -0,0 +1,234 @@ +@@ -0,0 +1,233 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> @@ -3152,14 +2992,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + jr ra + + END(ltq_mem_init) +diff --git a/arch/mips/cpu/mips32/vrx200/pmu.c b/arch/mips/cpu/mips32/vrx200/pmu.c +new file mode 100644 +index 0000000..a144473 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/pmu.c -@@ -0,0 +1,131 @@ +@@ -0,0 +1,130 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -3286,14 +3128,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + ltq_clrsetbits(<q_pmu_regs->pwdcr, clr, set); +} +diff --git a/arch/mips/cpu/mips32/vrx200/rcu.c b/arch/mips/cpu/mips32/vrx200/rcu.c +new file mode 100644 +index 0000000..763f287 --- /dev/null +++ b/arch/mips/cpu/mips32/vrx200/rcu.c -@@ -0,0 +1,195 @@ +@@ -0,0 +1,194 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -3484,87 +3328,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + /* Start GPHY by releasing reset */ + ltq_clrbits(<q_rcu_regs->req, module); +} ---- /dev/null -+++ b/arch/mips/cpu/mips32/vrx200/u-boot.lds -@@ -0,0 +1,69 @@ -+/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * -+ * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ */ -+ -+OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips") -+OUTPUT_ARCH(mips) -+ENTRY(_start) -+SECTIONS -+{ -+ . = 0x00000000; -+ -+ . = ALIGN(4); -+ .text : { -+ *(.text*) -+ } -+ -+ . = ALIGN(4); -+ .rodata : { -+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) -+ } -+ -+ . = ALIGN(4); -+ .data : { -+ *(.data*) -+ } -+ -+ . = ALIGN(4); -+ .sdata : { -+ *(.sdata*) -+ } -+ -+ . = .; -+ _gp = ALIGN(16) + 0x7ff0; -+ -+ .got : { -+ __got_start = .; -+ *(.got) -+ __got_end = .; -+ } -+ -+ num_got_entries = (__got_end - __got_start) >> 2; -+ -+#ifndef CONFIG_SPL_BUILD -+ . = ALIGN(4); -+ .u_boot_list : { -+ #include <u-boot.lst> -+ } -+#endif -+ -+ . = ALIGN(4); -+ __image_copy_end = .; -+ uboot_end_data = .; -+ -+ .bss (NOLOAD) : { -+ __bss_start = .; -+ *(.bss*) -+ *(.sbss*) -+ . = ALIGN(4); -+ __bss_end = .; -+ } -+ -+ . = ALIGN(4); -+ __end = .; -+ uboot_end = .; -+} +diff --git a/arch/mips/include/asm/arch-danube/config.h b/arch/mips/include/asm/arch-danube/config.h +new file mode 100644 +index 0000000..d84f66f --- /dev/null +++ b/arch/mips/include/asm/arch-danube/config.h -@@ -0,0 +1,156 @@ +@@ -0,0 +1,163 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + * + * Common board configuration for Lantiq XWAY Danube family + * @@ -3621,7 +3395,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_SYS_INIT_SP_OFFSET 0x4000 + +/* SRAM */ -+#define CONFIG_SYS_SRAM_BASE 0xBE180000 ++#define CONFIG_SYS_SRAM_BASE 0xBE1A0000 +#define CONFIG_SYS_SRAM_SIZE 0x10000 + +/* ASC/UART driver and console */ @@ -3659,6 +3433,14 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_CMD_SPI +#endif + ++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) ++#define CONFIG_NAND_LANTIQ ++#define CONFIG_SYS_MAX_NAND_DEVICE 1 ++#define CONFIG_SYS_NAND_BASE 0xB4000000 ++ ++#define CONFIG_CMD_NAND ++#endif ++ +#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) +#define CONFIG_LANTIQ_DMA +#define CONFIG_LANTIQ_DANUBE_ETOP @@ -3715,14 +3497,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#endif /* __DANUBE_CONFIG_H__ */ +diff --git a/arch/mips/include/asm/arch-danube/gpio.h b/arch/mips/include/asm/arch-danube/gpio.h +new file mode 100644 +index 0000000..70eb086 --- /dev/null +++ b/arch/mips/include/asm/arch-danube/gpio.h -@@ -0,0 +1,13 @@ +@@ -0,0 +1,12 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DANUBE_GPIO_H__ @@ -3731,15 +3515,36 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#include <asm/lantiq/gpio.h> + +#endif /* __DANUBE_GPIO_H__ */ +diff --git a/arch/mips/include/asm/arch-danube/nand.h b/arch/mips/include/asm/arch-danube/nand.h +new file mode 100644 +index 0000000..c7a573a --- /dev/null -+++ b/arch/mips/include/asm/arch-danube/soc.h -@@ -0,0 +1,40 @@ ++++ b/arch/mips/include/asm/arch-danube/nand.h +@@ -0,0 +1,13 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __DANUBE_NAND_H__ ++#define __DANUBE_NAND_H__ ++ ++struct nand_chip; ++int ltq_nand_init(struct nand_chip *nand); ++ ++#endif /* __DANUBE_NAND_H__ */ +diff --git a/arch/mips/include/asm/arch-danube/soc.h b/arch/mips/include/asm/arch-danube/soc.h +new file mode 100644 +index 0000000..47ef62a +--- /dev/null ++++ b/arch/mips/include/asm/arch-danube/soc.h +@@ -0,0 +1,38 @@ ++/* + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DANUBE_SOC_H__ @@ -3754,9 +3559,8 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +#define LTQ_EBU_BASE 0x1E105300 +#define LTQ_EBU_REGION0_BASE 0x10000000 -+#define LTQ_EBU_REGION0_SIZE (64 * 1024 * 1024) +#define LTQ_EBU_REGION1_BASE 0x14000000 -+#define LTQ_EBU_REGION1_SIZE (32 * 1024 * 1024) ++#define LTQ_EBU_NAND_BASE (LTQ_EBU_BASE + 0xB0) + +#define LTQ_PPE_BASE 0x1E180000 +#define LTQ_PPE_ETOP_BASE (LTQ_PPE_BASE + 0x11800) @@ -3774,15 +3578,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define LTQ_MC_DDR_DC_OFFSET(x) (x * 0x10) + +#endif /* __DANUBE_SOC_H__ */ +diff --git a/arch/mips/include/asm/arch-vrx200/config.h b/arch/mips/include/asm/arch-vrx200/config.h +new file mode 100644 +index 0000000..88ef256 --- /dev/null +++ b/arch/mips/include/asm/arch-vrx200/config.h -@@ -0,0 +1,185 @@ +@@ -0,0 +1,184 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + * + * Common board configuration for Lantiq XWAY VRX200 family + * @@ -3795,13 +3601,13 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + * CONFIG_LTQ_SUPPORT_NOR_FLASH + * - support a parallel NOR flash via the CFI interface in flash bank 0 + * ++ * CONFIG_LTQ_SUPPORT_ETHERNET ++ * - support the VRX200 internal switch ++ * + * CONFIG_LTQ_SUPPORT_SPI_FLASH + * - support the VRX200 SPI interface and serial flash drivers + * - specific SPI flash drivers must be configured separately + * -+ * CONFIG_LTQ_SUPPORT_ETHERNET -+ * - support the VRX200 internal switch -+ * + * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH + * - build a preloader that runs in the internal SRAM and loads + * the U-Boot from SPI flash into RAM @@ -3962,14 +3768,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE + +#endif /* __VRX200_CONFIG_H__ */ +diff --git a/arch/mips/include/asm/arch-vrx200/gphy.h b/arch/mips/include/asm/arch-vrx200/gphy.h +new file mode 100644 +index 0000000..6cdb268 --- /dev/null +++ b/arch/mips/include/asm/arch-vrx200/gphy.h -@@ -0,0 +1,66 @@ +@@ -0,0 +1,65 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VRX200_GPHY_H__ @@ -4031,14 +3839,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +extern void ltq_rcu_gphy_boot(unsigned int id, ulong addr); + +#endif /* __VRX200_GPHY_H__ */ +diff --git a/arch/mips/include/asm/arch-vrx200/gpio.h b/arch/mips/include/asm/arch-vrx200/gpio.h +new file mode 100644 +index 0000000..b8d7676 --- /dev/null +++ b/arch/mips/include/asm/arch-vrx200/gpio.h -@@ -0,0 +1,13 @@ +@@ -0,0 +1,12 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VRX200_GPIO_H__ @@ -4047,14 +3857,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#include <asm/lantiq/gpio.h> + +#endif /* __VRX200_GPIO_H__ */ +diff --git a/arch/mips/include/asm/arch-vrx200/nand.h b/arch/mips/include/asm/arch-vrx200/nand.h +new file mode 100644 +index 0000000..231b68f --- /dev/null +++ b/arch/mips/include/asm/arch-vrx200/nand.h -@@ -0,0 +1,14 @@ +@@ -0,0 +1,13 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VRX200_NAND_H__ @@ -4064,15 +3876,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +int ltq_nand_init(struct nand_chip *nand); + +#endif /* __VRX200_NAND_H__ */ +diff --git a/arch/mips/include/asm/arch-vrx200/soc.h b/arch/mips/include/asm/arch-vrx200/soc.h +new file mode 100644 +index 0000000..fae5906 --- /dev/null +++ b/arch/mips/include/asm/arch-vrx200/soc.h -@@ -0,0 +1,46 @@ +@@ -0,0 +1,45 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __VRX200_SOC_H__ @@ -4113,29 +3927,20 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define LTQ_MC_DDR_CCR_OFFSET(x) (x * 0x10) + +#endif /* __VRX200_SOC_H__ */ +diff --git a/arch/mips/include/asm/arch-vrx200/switch.h b/arch/mips/include/asm/arch-vrx200/switch.h +new file mode 100644 +index 0000000..e505099 --- /dev/null +++ b/arch/mips/include/asm/arch-vrx200/switch.h -@@ -0,0 +1,514 @@ +@@ -0,0 +1,502 @@ +/* -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> ++ * SPDX-License-Identifier: GPL-2.0+ + */ + -+#ifndef __VR9_SWITCH_H__ -+#define __VR9_SWITCH_H__ ++#ifndef __VRX200_SWITCH_H__ ++#define __VRX200_SWITCH_H__ + +/* Switch core registers */ +struct vr9_switch_core_regs { @@ -4629,7 +4434,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MDIO_CTRL_PHYAD_MASK (0x1f << MDIO_CTRL_PHYAD_SHIFT) +#define MDIO_CTRL_REGAD_MASK 0x1f + -+#endif ++#endif /* __VRX200_SWITCH_H__ */ +diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h +index 933ccb1..dd0ffb6 100644 --- a/arch/mips/include/asm/asm.h +++ b/arch/mips/include/asm/asm.h @@ -53,6 +53,7 @@ @@ -4650,24 +4457,28 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> symbol: .frame sp, framesize, rpc /* +diff --git a/arch/mips/include/asm/gpio.h b/arch/mips/include/asm/gpio.h +new file mode 100644 +index 0000000..9be58b8 --- /dev/null +++ b/arch/mips/include/asm/gpio.h -@@ -0,0 +1,7 @@ +@@ -0,0 +1,6 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/gpio.h> +#include <asm-generic/gpio.h> +diff --git a/arch/mips/include/asm/lantiq/chipid.h b/arch/mips/include/asm/lantiq/chipid.h +new file mode 100644 +index 0000000..c9921b0 --- /dev/null +++ b/arch/mips/include/asm/lantiq/chipid.h -@@ -0,0 +1,74 @@ +@@ -0,0 +1,73 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_CHIPID_H__ @@ -4737,17 +4548,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#endif + +#endif /* __LANTIQ_CHIPID_H__ */ +diff --git a/arch/mips/include/asm/lantiq/clk.h b/arch/mips/include/asm/lantiq/clk.h +new file mode 100644 +index 0000000..e13f000 --- /dev/null +++ b/arch/mips/include/asm/lantiq/clk.h -@@ -0,0 +1,33 @@ +@@ -0,0 +1,30 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com -+ * -+ * Based on Lantiq port in Linux kernel ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_CLK_H__ @@ -4773,15 +4584,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +extern unsigned long ltq_get_io_region_clock(void); + +#endif /* __LANTIQ_CLK_H__ */ +diff --git a/arch/mips/include/asm/lantiq/config.h b/arch/mips/include/asm/lantiq/config.h +new file mode 100644 +index 0000000..feac30d --- /dev/null +++ b/arch/mips/include/asm/lantiq/config.h -@@ -0,0 +1,166 @@ +@@ -0,0 +1,164 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_CONFIG_H__ @@ -4816,6 +4629,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_SPL +#define CONFIG_SPL_SPI_SUPPORT +#define CONFIG_SPL_SPI_FLASH_SUPPORT ++#define CONFIG_SPI_SPL_SIMPLE +#endif + +#if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL) @@ -4855,11 +4669,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVEENV -+#define CONFIG_CMD_LOADS +#define CONFIG_CMD_LOADB + +/* Other U-Boot settings */ -+#define CONFIG_UBOOT_VERSION +#define CONFIG_TIMESTAMP + +/* Default environment */ @@ -4942,14 +4754,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + CONFIG_ENV_LOAD_UBOOT_SF + +#endif /* __LANTIQ_CONFIG_H__ */ +diff --git a/arch/mips/include/asm/lantiq/cpu.h b/arch/mips/include/asm/lantiq/cpu.h +new file mode 100644 +index 0000000..b3a504e --- /dev/null +++ b/arch/mips/include/asm/lantiq/cpu.h -@@ -0,0 +1,35 @@ +@@ -0,0 +1,34 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_CPU_H__ @@ -4980,14 +4794,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +void ltq_dcdc_init(unsigned int dig_ref); + +#endif /* __LANTIQ_CPU_H__ */ +diff --git a/arch/mips/include/asm/lantiq/dma.h b/arch/mips/include/asm/lantiq/dma.h +new file mode 100644 +index 0000000..15a29c9 --- /dev/null +++ b/arch/mips/include/asm/lantiq/dma.h -@@ -0,0 +1,95 @@ +@@ -0,0 +1,94 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_DMA_H__ @@ -5078,14 +4894,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + unsigned long timeout); + +#endif /* __LANTIQ_DMA_H__ */ +diff --git a/arch/mips/include/asm/lantiq/eth.h b/arch/mips/include/asm/lantiq/eth.h +new file mode 100644 +index 0000000..d09e9cf --- /dev/null +++ b/arch/mips/include/asm/lantiq/eth.h -@@ -0,0 +1,36 @@ +@@ -0,0 +1,35 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_ETH_H__ @@ -5117,14 +4935,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +extern int ltq_eth_initialize(const struct ltq_eth_board_config *board_config); + +#endif /* __LANTIQ_ETH_H__ */ +diff --git a/arch/mips/include/asm/lantiq/gpio.h b/arch/mips/include/asm/lantiq/gpio.h +new file mode 100644 +index 0000000..66e227f --- /dev/null +++ b/arch/mips/include/asm/lantiq/gpio.h -@@ -0,0 +1,51 @@ +@@ -0,0 +1,50 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_GPIO_H__ @@ -5171,15 +4991,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#include <asm-generic/gpio.h> + +#endif /* __LANTIQ_GPIO_H__ */ +diff --git a/arch/mips/include/asm/lantiq/io.h b/arch/mips/include/asm/lantiq/io.h +new file mode 100644 +index 0000000..5ac7696 --- /dev/null +++ b/arch/mips/include/asm/lantiq/io.h -@@ -0,0 +1,38 @@ +@@ -0,0 +1,37 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 John Crispin <blogic@openwrt.org> -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_IO_H__ @@ -5212,14 +5034,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +} + +#endif /* __LANTIQ_IO_H__ */ +diff --git a/arch/mips/include/asm/lantiq/pm.h b/arch/mips/include/asm/lantiq/pm.h +new file mode 100644 +index 0000000..9db7117 --- /dev/null +++ b/arch/mips/include/asm/lantiq/pm.h -@@ -0,0 +1,22 @@ +@@ -0,0 +1,21 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_PM_H__ @@ -5237,14 +5061,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +int ltq_pm_disable(enum ltq_pm_modules module); + +#endif /* __LANTIQ_PM_H__ */ +diff --git a/arch/mips/include/asm/lantiq/reset.h b/arch/mips/include/asm/lantiq/reset.h +new file mode 100644 +index 0000000..0dbc994 --- /dev/null +++ b/arch/mips/include/asm/lantiq/reset.h -@@ -0,0 +1,38 @@ +@@ -0,0 +1,37 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __LANTIQ_RESET_H__ @@ -5278,6 +5104,8 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +} + +#endif /* __LANTIQ_RESET_H__ */ +diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h +index be7e5c6..b3bc255 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -46,7 +46,10 @@ @@ -5342,16 +5170,20 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> * Bits in the coprocessor 0 config register. */ /* Generic bits. */ +diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h +index 9f3cce9..30fb469 100644 --- a/arch/mips/include/asm/u-boot-mips.h +++ b/arch/mips/include/asm/u-boot-mips.h -@@ -9,3 +9,4 @@ extern ulong uboot_end_data; - extern ulong uboot_end; +@@ -23,3 +23,4 @@ static inline unsigned long image_copy_end(void) + } extern int incaip_set_cpuclk(void); +extern int arch_cpu_init(void); +diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c +index 9e6ba15..daa0182 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c -@@ -50,6 +50,16 @@ static char *failed = "*** failed ***\n" +@@ -33,6 +33,16 @@ static char *failed = "*** failed ***\n"; */ const unsigned long mips_io_port_base = -1; @@ -5368,7 +5200,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> int __board_early_init_f(void) { /* -@@ -123,6 +133,7 @@ static int init_baudrate(void) +@@ -106,6 +116,7 @@ static int init_baudrate(void) typedef int (init_fnc_t)(void); init_fnc_t *init_sequence[] = { @@ -5376,15 +5208,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> board_early_init_f, timer_init, env_init, /* initialize environment */ +diff --git a/board/lantiq/easy50712/Makefile b/board/lantiq/easy50712/Makefile +new file mode 100644 +index 0000000..3a547c2 --- /dev/null +++ b/board/lantiq/easy50712/Makefile -@@ -0,0 +1,29 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,27 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -5408,26 +5241,30 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/board/lantiq/easy50712/config.mk b/board/lantiq/easy50712/config.mk +new file mode 100644 +index 0000000..9d8953b --- /dev/null +++ b/board/lantiq/easy50712/config.mk -@@ -0,0 +1,8 @@ +@@ -0,0 +1,7 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com +# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/lantiq/easy50712/ddr_settings.h b/board/lantiq/easy50712/ddr_settings.h +new file mode 100644 +index 0000000..36a4118 --- /dev/null +++ b/board/lantiq/easy50712/ddr_settings.h -@@ -0,0 +1,55 @@ +@@ -0,0 +1,54 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MC_DC00_VALUE 0x1B1B @@ -5477,15 +5314,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +#define MC_DC46_VALUE 0x0 +diff --git a/board/lantiq/easy50712/easy50712.c b/board/lantiq/easy50712/easy50712.c +new file mode 100644 +index 0000000..4f6a237 --- /dev/null +++ b/board/lantiq/easy50712/easy50712.c -@@ -0,0 +1,106 @@ +@@ -0,0 +1,112 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -5501,6 +5340,13 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + /* SPI/CS output (low-active) for serial flash */ + gpio_direction_output(22, 1); + ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ + /* enable CLK_OUT2 for external switch */ + gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); +} @@ -5586,15 +5432,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + break; + } +} +diff --git a/board/lantiq/easy80920/Makefile b/board/lantiq/easy80920/Makefile +new file mode 100644 +index 0000000..3a547c2 --- /dev/null +++ b/board/lantiq/easy80920/Makefile -@@ -0,0 +1,29 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,27 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -5618,26 +5465,30 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/board/lantiq/easy80920/config.mk b/board/lantiq/easy80920/config.mk +new file mode 100644 +index 0000000..9d8953b --- /dev/null +++ b/board/lantiq/easy80920/config.mk -@@ -0,0 +1,8 @@ +@@ -0,0 +1,7 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com +# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/lantiq/easy80920/ddr_settings.h b/board/lantiq/easy80920/ddr_settings.h +new file mode 100644 +index 0000000..671d1c1 --- /dev/null +++ b/board/lantiq/easy80920/ddr_settings.h -@@ -0,0 +1,70 @@ +@@ -0,0 +1,69 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MC_CCR00_VALUE 0x101 @@ -5702,14 +5553,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MC_CCR59_VALUE 0x7800301 +#define MC_CCR60_VALUE 0x7800301 +#define MC_CCR61_VALUE 0x4 +diff --git a/board/lantiq/easy80920/easy80920.c b/board/lantiq/easy80920/easy80920.c +new file mode 100644 +index 0000000..d9a4f81 --- /dev/null +++ b/board/lantiq/easy80920/easy80920.c -@@ -0,0 +1,139 @@ +@@ -0,0 +1,138 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -5844,29 +5697,33 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + break; + } +} +diff --git a/boards.cfg b/boards.cfg +index aa2ee64..f090726 100644 --- a/boards.cfg +++ b/boards.cfg -@@ -444,10 +444,17 @@ dbau1500 mips - dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550 - dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN - pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000 -+easy50712_nor mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_NOR -+easy50712_norspl mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_NORSPL -+easy50712_ram mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_RAM - incaip mips mips32 incaip - incaip - incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 - incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 - incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 -+easy80920_nor mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NOR -+easy80920_norspl mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NORSPL -+easy80920_ram mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_RAM -+easy80920_sfspl mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_SFSPL - qi_lb60 mips xburst qi_lb60 qi - adp-ag101 nds32 n1213 adp-ag101 AndesTech ag101 - adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101 +@@ -502,10 +502,17 @@ Active mips mips32 au1x00 - dbau1x00 + Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - ++Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> ++Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - + Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - + Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com> +diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile +index a6132e2..5a4bcef 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile -@@ -28,6 +28,7 @@ LIB := $(obj)libdma.o +@@ -12,6 +12,7 @@ LIB := $(obj)libdma.o COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o @@ -5874,14 +5731,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o COBJS := $(COBJS-y) +diff --git a/drivers/dma/lantiq_dma.c b/drivers/dma/lantiq_dma.c +new file mode 100644 +index 0000000..a78212a --- /dev/null +++ b/drivers/dma/lantiq_dma.c -@@ -0,0 +1,388 @@ +@@ -0,0 +1,387 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011-2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -6265,9 +6124,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return 0; +} +diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile +index 71ddb00..5fb505b 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile -@@ -28,6 +28,7 @@ LIB := $(obj)libgpio.o +@@ -12,6 +12,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o @@ -6275,14 +6136,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o +diff --git a/drivers/gpio/lantiq_gpio.c b/drivers/gpio/lantiq_gpio.c +new file mode 100644 +index 0000000..374a668 --- /dev/null +++ b/drivers/gpio/lantiq_gpio.c -@@ -0,0 +1,330 @@ +@@ -0,0 +1,329 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -6608,9 +6471,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return 0; +} +diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c +index a389cd1..fa4fae7 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c -@@ -177,6 +177,18 @@ u64 flash_read64(void *addr)__attribute_ +@@ -161,6 +161,18 @@ u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); #define flash_read64 __flash_read64 #endif @@ -6629,7 +6494,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> /*----------------------------------------------------------------------- */ #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE) -@@ -212,7 +224,7 @@ flash_map (flash_info_t * info, flash_se +@@ -196,7 +208,7 @@ flash_map (flash_info_t * info, flash_sect_t sect, uint offset) { unsigned int byte_offset = offset * info->portwidth; @@ -6638,9 +6503,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> } static inline void flash_unmap(flash_info_t *info, flash_sect_t sect, +diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile +index 366dee6..e9adaaa 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile -@@ -67,6 +67,7 @@ COBJS-$(CONFIG_NAND_JZ4740) += jz4740_na +@@ -53,6 +53,7 @@ COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o @@ -6648,14 +6515,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o +diff --git a/drivers/mtd/nand/lantiq_nand.c b/drivers/mtd/nand/lantiq_nand.c +new file mode 100644 +index 0000000..85f8f68 --- /dev/null +++ b/drivers/mtd/nand/lantiq_nand.c -@@ -0,0 +1,127 @@ +@@ -0,0 +1,126 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -6778,25 +6647,29 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + return ltq_nand_init(chip); +} +diff --git a/drivers/net/Makefile b/drivers/net/Makefile +index 18fd54f..bbc2c92 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile -@@ -51,6 +51,8 @@ COBJS-$(CONFIG_GRETH) += greth.o - COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o +@@ -37,6 +37,8 @@ COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o + COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o COBJS-$(CONFIG_LAN91C96) += lan91c96.o +COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o +COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o +diff --git a/drivers/net/lantiq_danube_etop.c b/drivers/net/lantiq_danube_etop.c +new file mode 100644 +index 0000000..7453882 --- /dev/null +++ b/drivers/net/lantiq_danube_etop.c -@@ -0,0 +1,411 @@ +@@ -0,0 +1,410 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -7203,15 +7076,17 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return 0; +} +diff --git a/drivers/net/lantiq_vrx200_switch.c b/drivers/net/lantiq_vrx200_switch.c +new file mode 100644 +index 0000000..174427d --- /dev/null +++ b/drivers/net/lantiq_vrx200_switch.c -@@ -0,0 +1,676 @@ +@@ -0,0 +1,675 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010-2011 Lantiq Deutschland GmbH -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define DEBUG @@ -7456,7 +7331,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + return packet + LTQ_ETH_IP_ALIGN; +} + -+static int ltq_eth_init(struct eth_device *dev, bd_t * bis) ++static int ltq_eth_init(struct eth_device *dev, bd_t *bis) +{ + struct ltq_eth_priv *priv = dev->priv; + struct ltq_dma_device *dma_dev = &priv->dma_dev; @@ -7882,24 +7757,28 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return 0; +} +diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile +index fe762e9..9eb08b8 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile -@@ -34,6 +34,7 @@ COBJS-$(CONFIG_PHYLIB_10G) += generic_10 - COBJS-$(CONFIG_PHY_ATHEROS) += atheros.o - COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o +@@ -20,6 +20,7 @@ COBJS-$(CONFIG_PHY_BROADCOM) += broadcom.o COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o + COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o + COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o +COBJS-$(CONFIG_PHY_LANTIQ) += lantiq.o COBJS-$(CONFIG_PHY_LXT) += lxt.o COBJS-$(CONFIG_PHY_MARVELL) += marvell.o COBJS-$(CONFIG_PHY_MICREL) += micrel.o +diff --git a/drivers/net/phy/lantiq.c b/drivers/net/phy/lantiq.c +new file mode 100644 +index 0000000..572c8c3 --- /dev/null +++ b/drivers/net/phy/lantiq.c -@@ -0,0 +1,239 @@ +@@ -0,0 +1,238 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define DEBUG @@ -8134,18 +8013,23 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return 0; +} +diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c +index 62925bb..dfbe108 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c -@@ -32,6 +32,8 @@ +@@ -16,9 +16,10 @@ + #include <command.h> + #include <miiphy.h> #include <phy.h> - #include <errno.h> +-#include <errno.h> + #include <linux/err.h> +DECLARE_GLOBAL_DATA_PTR; + /* Generic PHY support and helper functions */ /** -@@ -420,6 +422,16 @@ static LIST_HEAD(phy_drivers); +@@ -440,6 +441,16 @@ static LIST_HEAD(phy_drivers); int phy_init(void) { @@ -8162,9 +8046,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> #ifdef CONFIG_PHY_ATHEROS phy_atheros_init(); #endif -@@ -429,6 +441,9 @@ int phy_init(void) - #ifdef CONFIG_PHY_DAVICOM - phy_davicom_init(); +@@ -455,6 +466,9 @@ int phy_init(void) + #ifdef CONFIG_PHY_ICPLUS + phy_icplus_init(); #endif +#ifdef CONFIG_PHY_LANTIQ + phy_lantiq_init(); @@ -8172,9 +8056,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> #ifdef CONFIG_PHY_LXT phy_lxt_init(); #endif +diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile +index e1fd7a5..3247b82 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile -@@ -42,6 +42,7 @@ COBJS-$(CONFIG_SYS_NS16550_SERIAL) += se +@@ -24,6 +24,7 @@ COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o @@ -8182,15 +8068,37 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o COBJS-$(CONFIG_MXC_UART) += serial_mxc.o COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o +diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c +index df2b84a..b955f30 100644 +--- a/drivers/serial/serial.c ++++ b/drivers/serial/serial.c +@@ -160,6 +160,7 @@ serial_initfunc(sa1100_serial_initialize); + serial_initfunc(sh_serial_initialize); + serial_initfunc(arm_dcc_initialize); + serial_initfunc(mxs_auart_initialize); ++serial_initfunc(ltq_serial_initialize); + + /** + * serial_register() - Register serial driver with serial driver core +@@ -253,6 +254,7 @@ void serial_initialize(void) + sh_serial_initialize(); + arm_dcc_initialize(); + mxs_auart_initialize(); ++ ltq_serial_initialize(); + + serial_assign(default_serial_console()->name); + } +diff --git a/drivers/serial/serial_lantiq.c b/drivers/serial/serial_lantiq.c +new file mode 100644 +index 0000000..07b2f9d --- /dev/null +++ b/drivers/serial/serial_lantiq.c -@@ -0,0 +1,264 @@ +@@ -0,0 +1,263 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -8430,7 +8338,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +} + +static struct serial_device ltq_serial_drv = { -+ .name = "ixp_serial", ++ .name = "ltq_serial", + .start = ltq_serial_init, + .stop = NULL, + .setbrg = ltq_serial_setbrg, @@ -8440,7 +8348,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + .tstc = ltq_serial_tstc, +}; + -+void ixp_serial_initialize(void) ++void ltq_serial_initialize(void) +{ + serial_register(<q_serial_drv); +} @@ -8449,24 +8357,28 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + return <q_serial_drv; +} +diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile +index e5941b0..f831ea1 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile -@@ -36,6 +36,7 @@ COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o - COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o +@@ -25,6 +25,7 @@ COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o + COBJS-$(CONFIG_ICH_SPI) += ich.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o +COBJS-$(CONFIG_LANTIQ_SPI) += lantiq_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o +diff --git a/drivers/spi/lantiq_spi.c b/drivers/spi/lantiq_spi.c +new file mode 100644 +index 0000000..b327878 --- /dev/null +++ b/drivers/spi/lantiq_spi.c -@@ -0,0 +1,476 @@ +@@ -0,0 +1,666 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -8492,6 +8404,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define LTQ_SPI_CON_ENBV (1 << 22) +#define LTQ_SPI_CON_BM_SHIFT 16 +#define LTQ_SPI_CON_BM_MASK (0x1F << LTQ_SPI_CON_BM_SHIFT) ++#define LTQ_SPI_CON_IDLE (1 << 23) ++#define LTQ_SPI_CON_RUEN (1 << 12) ++#define LTQ_SPI_CON_AEN (1 << 10) ++#define LTQ_SPI_CON_REN (1 << 9) ++#define LTQ_SPI_CON_TEN (1 << 8) +#define LTQ_SPI_CON_LB (1 << 7) +#define LTQ_SPI_CON_PO (1 << 6) +#define LTQ_SPI_CON_PH (1 << 5) @@ -8507,6 +8424,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define LTQ_SPI_WHBSTATE_CLRMS (1 << 2) +#define LTQ_SPI_WHBSTATE_SETEN (1 << 1) +#define LTQ_SPI_WHBSTATE_CLREN 1 ++#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50 + +#define LTQ_SPI_TXFCON_TXFLU (1 << 1) +#define LTQ_SPI_TXFCON_TXFEN 1 @@ -8526,55 +8444,60 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define LTQ_SPI_GPIO_CLK 18 + +struct ltq_spi_regs { -+ u32 clc; /* Clock control */ -+ u32 pisel; /* Port input select */ -+ u32 id; /* Identification */ -+ u32 rsvd0; -+ u32 con; /* Control */ -+ u32 stat; /* Status */ -+ u32 whbstate; /* Write HW modified state */ -+ u32 rsvd1; -+ u32 tb; /* Transmit buffer */ -+ u32 rb; /* Receive buffer */ -+ u32 rsvd2[2]; -+ u32 rxfcon; /* Recevie FIFO control */ -+ u32 txfcon; /* Transmit FIFO control */ -+ u32 fstat; /* FIFO status */ -+ u32 rsvd3; -+ u32 brt; /* Baudrate timer */ -+ u32 brstat; /* Baudrate timer status */ -+ u32 rsvd4[6]; -+ u32 sfcon; /* Serial frame control */ -+ u32 sfstat; /* Serial frame status */ -+ u32 rsvd5[2]; -+ u32 gpocon; /* General purpose output control */ -+ u32 gpostat; /* General purpose output status */ -+ u32 fgpo; /* Force general purpose output */ -+ u32 rsvd6; -+ u32 rxreq; /* Receive request */ -+ u32 rxcnt; /* Receive count */ -+ u32 rsvd7[25]; -+ u32 dmacon; /* DMA control */ ++ __be32 clc; /* Clock control */ ++ __be32 pisel; /* Port input select */ ++ __be32 id; /* Identification */ ++ __be32 rsvd0; ++ __be32 con; /* Control */ ++ __be32 stat; /* Status */ ++ __be32 whbstate; /* Write HW modified state */ ++ __be32 rsvd1; ++ __be32 tb; /* Transmit buffer */ ++ __be32 rb; /* Receive buffer */ ++ __be32 rsvd2[2]; ++ __be32 rxfcon; /* Recevie FIFO control */ ++ __be32 txfcon; /* Transmit FIFO control */ ++ __be32 fstat; /* FIFO status */ ++ __be32 rsvd3; ++ __be32 brt; /* Baudrate timer */ ++ __be32 brstat; /* Baudrate timer status */ ++ __be32 rsvd4[6]; ++ __be32 sfcon; /* Serial frame control */ ++ __be32 sfstat; /* Serial frame status */ ++ __be32 rsvd5[2]; ++ __be32 gpocon; /* General purpose output control */ ++ __be32 gpostat; /* General purpose output status */ ++ __be32 fgpo; /* Force general purpose output */ ++ __be32 rsvd6; ++ __be32 rxreq; /* Receive request */ ++ __be32 rxcnt; /* Receive count */ ++ __be32 rsvd7[25]; ++ __be32 dmacon; /* DMA control */ ++ __be32 rsvd8; ++ __be32 irnen; /* Interrupt node enable */ ++ __be32 irnicr; /* Interrupt node interrupt capture */ ++ __be32 irncr; /* Interrupt node control */ +}; + -+struct ltq_spi_slave { ++struct ltq_spi_drv_data { ++ struct ltq_spi_regs __iomem *regs; ++ + struct spi_slave slave; + unsigned int max_hz; + unsigned int mode; -+ unsigned int len; -+ unsigned int brt; -+ unsigned int tx_cnt; -+ unsigned int rx_cnt; ++ unsigned int tx_todo; ++ unsigned int rx_todo; + unsigned int rx_req; ++ unsigned int bits_per_word; ++ unsigned int speed_hz; + const u8 *tx; + u8 *rx; -+ u8 txfs; -+ u8 rxfs; ++ int status; +}; + -+static inline struct ltq_spi_slave *to_ltq_spi_slave(struct spi_slave *slave) ++static struct ltq_spi_drv_data *to_ltq_spi_slave(struct spi_slave *slave) +{ -+ return container_of(slave, struct ltq_spi_slave, slave); ++ return container_of(slave, struct ltq_spi_drv_data, slave); +} + +#ifdef CONFIG_SPL_BUILD @@ -8583,306 +8506,475 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + * Neither we have to support multiple SPI slaves. Thus we put the + * SPI slave context in BSS for SPL builds. + */ -+static struct ltq_spi_slave ltq_spi_slave; ++static struct ltq_spi_drv_data ltq_spi_slave; + -+static inline struct ltq_spi_slave *ltq_spi_slave_alloc(void) ++static struct ltq_spi_drv_data *ltq_spi_slave_alloc(unsigned int bus, ++ unsigned int cs) +{ ++ ltq_spi_slave.slave.bus = bus; ++ ltq_spi_slave.slave.cs = cs; ++ + return <q_spi_slave; +} + -+static inline void ltq_spi_slave_free(struct spi_slave *slave) ++static void ltq_spi_slave_free(struct spi_slave *slave) +{ +} +#else -+static inline struct ltq_spi_slave *ltq_spi_slave_alloc(void) ++static struct ltq_spi_drv_data *ltq_spi_slave_alloc(unsigned int bus, ++ unsigned int cs) +{ -+ return malloc(sizeof(struct ltq_spi_slave)); ++ return spi_alloc_slave(struct ltq_spi_drv_data, bus, cs); +} + -+static inline void ltq_spi_slave_free(struct spi_slave *slave) ++static void ltq_spi_slave_free(struct spi_slave *slave) +{ -+ struct ltq_spi_slave *sl; ++ struct ltq_spi_drv_data *drv; + + if (slave) { -+ sl = to_ltq_spi_slave(slave); -+ free(sl); ++ drv = to_ltq_spi_slave(slave); ++ free(drv); + } +} +#endif + -+static struct ltq_spi_regs *ltq_spi_regs = -+ (struct ltq_spi_regs *) CKSEG1ADDR(LTQ_SPI_BASE); ++static unsigned int tx_fifo_size(struct ltq_spi_drv_data *drv) ++{ ++ u32 id = ltq_readl(&drv->regs->id); + -+void spi_init(void) ++ return (id & LTQ_SPI_ID_TXFS_MASK) >> LTQ_SPI_ID_TXFS_SHIFT; ++} ++ ++static unsigned int rx_fifo_size(struct ltq_spi_drv_data *drv) ++{ ++ u32 id = ltq_readl(&drv->regs->id); ++ ++ return (id & LTQ_SPI_ID_RXFS_MASK) >> LTQ_SPI_ID_RXFS_SHIFT; ++} ++ ++static unsigned int tx_fifo_level(struct ltq_spi_drv_data *drv) ++{ ++ u32 fstat = ltq_readl(&drv->regs->fstat); ++ ++ return (fstat & LTQ_SPI_FSTAT_TXFFL_MASK) >> LTQ_SPI_FSTAT_TXFFL_SHIFT; ++} ++ ++static unsigned int rx_fifo_level(struct ltq_spi_drv_data *drv) ++{ ++ u32 fstat = ltq_readl(&drv->regs->fstat); ++ ++ return fstat & LTQ_SPI_FSTAT_RXFFL_MASK; ++} ++ ++static unsigned int tx_fifo_free(struct ltq_spi_drv_data *drv) +{ -+ /* Power up SPI subsystem */ ++ return tx_fifo_size(drv) - tx_fifo_level(drv); ++} ++ ++static void hw_power_on(struct ltq_spi_drv_data *drv) ++{ ++ u32 clc; ++ ++ /* Power-up mdule */ + ltq_pm_enable(LTQ_PM_SPI); + -+ /* Enable module and set clock divider to 1 */ -+ ltq_writel(<q_spi_regs->clc, 1 << LTQ_SPI_CLC_RMC_SHIFT); ++ /* ++ * Set clock divider for run mode to 1 to ++ * run at same frequency as FPI bus ++ */ ++ clc = (1 << LTQ_SPI_CLC_RMC_SHIFT); ++ ltq_writel(&drv->regs->clc, clc); ++} + -+ /* SPI/DIN input */ -+ gpio_set_altfunc(16, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); -+ /* SPI/DOUT output */ -+ gpio_set_altfunc(17, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); -+ /* SPI/CLK output */ -+ gpio_set_altfunc(18, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++static void hw_reset_fifos(struct ltq_spi_drv_data *drv) ++{ ++ u32 val; ++ ++ val = LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; ++ ltq_writel(&drv->regs->txfcon, val); ++ ++ val = LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; ++ ltq_writel(&drv->regs->rxfcon, val); +} + -+static inline u32 ltq_spi_calc_br(unsigned int max_hz) ++static int hw_is_busy(struct ltq_spi_drv_data *drv) +{ -+ u32 speed_hz, spi_hz; -+ u16 brt; ++ u32 stat = ltq_readl(&drv->regs->stat); + -+ /* SPI module clock is same as FPI bus clock */ -+ spi_hz = ltq_get_bus_clock(); ++ return stat & LTQ_SPI_STAT_BSY; ++} ++ ++static void hw_enter_config_mode(struct ltq_spi_drv_data *drv) ++{ ++ ltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_CLREN); ++} ++ ++static void hw_enter_active_mode(struct ltq_spi_drv_data *drv) ++{ ++ ltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_SETEN); ++} ++ ++static void hw_setup_speed_hz(struct ltq_spi_drv_data *drv, ++ unsigned int max_speed_hz) ++{ ++ unsigned int spi_hz, speed_hz, brt; + + /* ++ * SPI module clock is derived from FPI bus clock dependent on ++ * divider value in CLC.RMS which is always set to 1. ++ * + * f_SPI + * baudrate = -------------- + * 2 * (BR + 1) + */ -+ spi_hz /= 2; ++ spi_hz = ltq_get_bus_clock() / 2; + ++ /* TODO: optimize baudrate calculation */ + for (brt = 0; brt < 0xFFFF; brt++) { + speed_hz = spi_hz / (brt + 1); -+ if (speed_hz <= max_hz) ++ if (speed_hz <= max_speed_hz) + break; + } + -+ return brt; ++ ltq_writel(&drv->regs->brt, brt); +} + -+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, -+ unsigned int max_hz, unsigned int mode) ++static void hw_setup_bits_per_word(struct ltq_spi_drv_data *drv, ++ unsigned int bits_per_word) +{ -+ u32 id; -+ struct ltq_spi_slave *sl; -+ -+ if (!spi_cs_is_valid(bus, cs)) -+ return NULL; -+ -+ sl = ltq_spi_slave_alloc(); -+ if (!sl) -+ return NULL; ++ u32 bm; + -+ /* Read HW capabilities */ -+ id = ltq_readl(<q_spi_regs->id); -+ sl->txfs = (id & LTQ_SPI_ID_TXFS_MASK) >> LTQ_SPI_ID_TXFS_SHIFT; -+ sl->rxfs = (id & LTQ_SPI_ID_RXFS_MASK) >> LTQ_SPI_ID_RXFS_SHIFT; ++ /* CON.BM value = bits_per_word - 1 */ ++ bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT; + -+ sl->slave.bus = bus; -+ sl->slave.cs = cs; -+ sl->max_hz = max_hz; -+ sl->mode = mode; -+ -+ sl->brt = ltq_spi_calc_br(max_hz); -+ -+ return &sl->slave; ++ ltq_clrsetbits(&drv->regs->con, LTQ_SPI_CON_BM_MASK, bm); +} + -+void spi_free_slave(struct spi_slave *slave) ++static void hw_setup_clock_mode(struct ltq_spi_drv_data *drv, unsigned int mode) +{ -+ ltq_spi_slave_free(slave); -+} -+ -+static int ltq_spi_wait_ready(struct ltq_spi_slave *sl) -+{ -+ u32 stat; -+ const unsigned long timeout = 20000; -+ unsigned long timebase; ++ u32 con_set = 0, con_clr = 0; + -+ timebase = get_timer(0); ++ /* ++ * SPI mode mapping in CON register: ++ * Mode CPOL CPHA CON.PO CON.PH ++ * 0 0 0 0 1 ++ * 1 0 1 0 0 ++ * 2 1 0 1 1 ++ * 3 1 1 1 0 ++ */ ++ if (mode & SPI_CPHA) ++ con_clr |= LTQ_SPI_CON_PH; ++ else ++ con_set |= LTQ_SPI_CON_PH; + -+ do { -+ WATCHDOG_RESET(); ++ if (mode & SPI_CPOL) ++ con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; ++ else ++ con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE; + -+ stat = ltq_readl(<q_spi_regs->stat); ++ /* Set heading control */ ++ if (mode & SPI_LSB_FIRST) ++ con_clr |= LTQ_SPI_CON_HB; ++ else ++ con_set |= LTQ_SPI_CON_HB; + -+ if (!(stat & LTQ_SPI_STAT_BSY)) -+ return 0; -+ } while (get_timer(timebase) < timeout); ++ /* Set loopback mode */ ++ if (mode & SPI_LOOP) ++ con_set |= LTQ_SPI_CON_LB; ++ else ++ con_clr |= LTQ_SPI_CON_LB; + -+ return 1; ++ ltq_clrsetbits(&drv->regs->con, con_clr, con_set); +} + -+int spi_claim_bus(struct spi_slave *slave) ++static void hw_set_rxtx(struct ltq_spi_drv_data *drv) +{ -+ struct ltq_spi_slave *sl = to_ltq_spi_slave(slave); + u32 con; -+ int ret; + -+ /* Put module in configuration mode */ -+ ltq_setbits(<q_spi_regs->whbstate, LTQ_SPI_WHBSTATE_CLREN); ++ /* Configure transmitter and receiver */ ++ con = ltq_readl(&drv->regs->con); ++ if (drv->tx) ++ con &= ~LTQ_SPI_CON_TXOFF; ++ else ++ con |= LTQ_SPI_CON_TXOFF; + -+ /* Enable and flush RX and TX FIFOs */ -+ ltq_setbits(<q_spi_regs->txfcon, -+ LTQ_SPI_TXFCON_TXFLU | LTQ_SPI_TXFCON_TXFEN); -+ ltq_setbits(<q_spi_regs->rxfcon, -+ LTQ_SPI_RXFCON_RXFLU | LTQ_SPI_RXFCON_RXFEN); ++ if (drv->rx) ++ con &= ~LTQ_SPI_CON_RXOFF; ++ else ++ con |= LTQ_SPI_CON_RXOFF; + -+ ret = ltq_spi_wait_ready(sl); -+ if (ret) -+ return ret; ++ ltq_writel(&drv->regs->con, con); ++} + -+ /* Set baudrate */ -+ ltq_writel(<q_spi_regs->brt, sl->brt); ++static void hw_init(struct ltq_spi_drv_data *drv) ++{ ++ hw_power_on(drv); + -+ /* -+ * Disable byte valid control (ENBV = 0) and -+ * set data width to 8 bit (BM = 7) -+ */ -+ con = (7 << LTQ_SPI_CON_BM_SHIFT); ++ /* Put controller into config mode */ ++ hw_enter_config_mode(drv); + -+ /* Disable transmitter and receiver */ -+ con |= (LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_TXOFF); ++ /* Disable all interrupts */ ++ ltq_writel(&drv->regs->irnen, 0); + -+ /* Set SPI mode -+ * Mapping: Mode CPOL CPHA CON.PO CON.PH -+ * 0 0 0 0 1 -+ * 1 0 1 0 0 -+ * 2 1 0 1 1 -+ * 3 1 1 1 0 -+ */ -+ if (sl->mode & SPI_CPHA) -+ con &= ~LTQ_SPI_CON_PH; -+ else -+ con |= LTQ_SPI_CON_PH; ++ /* Clear error flags */ ++ ltq_clrsetbits(&drv->regs->whbstate, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS); + -+ if (sl->mode & SPI_CPOL) -+ con |= LTQ_SPI_CON_PO; -+ else -+ con &= ~LTQ_SPI_CON_PO; ++ /* Enable error checking, disable TX/RX */ ++ ltq_writel(&drv->regs->con, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | ++ LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF | ++ LTQ_SPI_CON_RXOFF); + -+ /* Set heading control */ -+ if (sl->mode & SPI_LSB_FIRST) -+ con &= ~LTQ_SPI_CON_HB; -+ else -+ con |= LTQ_SPI_CON_HB; ++ /* Setup default SPI mode */ ++ drv->bits_per_word = 8; ++ drv->speed_hz = 0; ++ hw_setup_bits_per_word(drv, drv->bits_per_word); ++ hw_setup_clock_mode(drv, SPI_MODE_0); + -+ /* Set loopback control */ -+ if (sl->mode & SPI_LOOP) -+ con |= LTQ_SPI_CON_LB; -+ else -+ con &= ~LTQ_SPI_CON_LB; ++ /* Enable master mode and clear error flags */ ++ ltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_SETMS | ++ LTQ_SPI_WHBSTATE_CLR_ERRORS); + -+ ltq_writel(<q_spi_regs->con, con); ++ /* Reset GPIO/CS registers */ ++ ltq_writel(&drv->regs->gpocon, 0); ++ ltq_writel(&drv->regs->fgpo, 0xFF00); + -+ /* Set SPI master mode and enable SPI */ -+ ltq_setbits(<q_spi_regs->whbstate, -+ LTQ_SPI_WHBSTATE_SETEN | LTQ_SPI_WHBSTATE_SETMS); ++ /* Enable and flush FIFOs */ ++ hw_reset_fifos(drv); + -+ return 0; ++ /* SPI/DIN input */ ++ gpio_set_altfunc(16, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); ++ /* SPI/DOUT output */ ++ gpio_set_altfunc(17, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* SPI/CLK output */ ++ gpio_set_altfunc(18, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); +} + -+void spi_release_bus(struct spi_slave *slave) ++static void tx_fifo_write(struct ltq_spi_drv_data *drv) +{ -+ /* Put module in configuration mode */ -+ ltq_setbits(<q_spi_regs->whbstate, LTQ_SPI_WHBSTATE_CLREN); ++ const u8 *tx8; ++ const u16 *tx16; ++ const u32 *tx32; ++ u32 data; ++ unsigned int tx_free = tx_fifo_free(drv); ++ ++ while (drv->tx_todo && tx_free) { ++ switch (drv->bits_per_word) { ++ case 8: ++ tx8 = drv->tx; ++ data = *tx8; ++ drv->tx_todo--; ++ drv->tx++; ++ break; ++ case 16: ++ tx16 = (u16 *) drv->tx; ++ data = *tx16; ++ drv->tx_todo -= 2; ++ drv->tx += 2; ++ break; ++ case 32: ++ tx32 = (u32 *) drv->tx; ++ data = *tx32; ++ drv->tx_todo -= 4; ++ drv->tx += 4; ++ break; ++ default: ++ return; ++ } + -+ /* Flush RX and TX FIFOs */ -+ ltq_setbits(<q_spi_regs->txfcon, LTQ_SPI_TXFCON_TXFLU); -+ ltq_setbits(<q_spi_regs->rxfcon, LTQ_SPI_RXFCON_RXFLU); ++ ltq_writel(&drv->regs->tb, data); ++ tx_free--; ++ } +} + -+static inline void ltq_spi_txfifo_write(struct ltq_spi_slave *sl) ++static void rx_fifo_read_full_duplex(struct ltq_spi_drv_data *drv) +{ -+ u32 fstat, tb; -+ u16 fifo_space; ++ u8 *rx8; ++ u16 *rx16; ++ u32 *rx32; ++ u32 data; ++ unsigned int rx_fill = rx_fifo_level(drv); + -+ fstat = ltq_readl(<q_spi_regs->fstat); -+ fifo_space = sl->txfs - ((fstat & LTQ_SPI_FSTAT_TXFFL_MASK) >> -+ LTQ_SPI_FSTAT_TXFFL_SHIFT); ++ while (rx_fill) { ++ data = ltq_readl(&drv->regs->rb); + -+ while (sl->tx_cnt < sl->len && fifo_space) { -+ tb = *sl->tx++; -+ ltq_writel(<q_spi_regs->tb, tb); -+ fifo_space--; -+ sl->tx_cnt++; ++ switch (drv->bits_per_word) { ++ case 8: ++ rx8 = drv->rx; ++ *rx8 = data; ++ drv->rx_todo--; ++ drv->rx++; ++ break; ++ case 16: ++ rx16 = (u16 *) drv->rx; ++ *rx16 = data; ++ drv->rx_todo -= 2; ++ drv->rx += 2; ++ break; ++ case 32: ++ rx32 = (u32 *) drv->rx; ++ *rx32 = data; ++ drv->rx_todo -= 4; ++ drv->rx += 4; ++ break; ++ default: ++ return; ++ } ++ ++ rx_fill--; ++ } ++} ++ ++static void rx_fifo_read_half_duplex(struct ltq_spi_drv_data *drv) ++{ ++ u32 data, *rx32; ++ u8 *rx8; ++ unsigned int rxbv, shift; ++ unsigned int rx_fill = rx_fifo_level(drv); ++ ++ /* ++ * In RX-only mode the bits per word value is ignored by HW. A value ++ * of 32 is used instead. Thus all 4 bytes per FIFO must be read. ++ * If remaining RX bytes are less than 4, the FIFO must be read ++ * differently. The amount of received and valid bytes is indicated ++ * by STAT.RXBV register value. ++ */ ++ while (rx_fill) { ++ if (drv->rx_todo < 4) { ++ rxbv = (ltq_readl(&drv->regs->stat) & ++ LTQ_SPI_STAT_RXBV_MASK) >> ++ LTQ_SPI_STAT_RXBV_SHIFT; ++ data = ltq_readl(&drv->regs->rb); ++ ++ shift = (rxbv - 1) * 8; ++ rx8 = drv->rx; ++ ++ while (rxbv) { ++ *rx8++ = (data >> shift) & 0xFF; ++ rxbv--; ++ shift -= 8; ++ drv->rx_todo--; ++ drv->rx++; ++ ++ if (drv->rx_req) ++ drv->rx_req --; ++ } ++ } else { ++ data = ltq_readl(&drv->regs->rb); ++ rx32 = (u32 *) drv->rx; ++ ++ *rx32++ = data; ++ drv->rx_todo -= 4; ++ drv->rx += 4; ++ ++ if (drv->rx_req >= 4) ++ drv->rx_req -= 4; ++ } ++ rx_fill--; + } +} + -+static inline void ltq_spi_rx_request(struct ltq_spi_slave *sl) ++static void rx_request(struct ltq_spi_drv_data *drv) +{ -+ u32 rxreq, rxreq_max; ++ unsigned int rxreq, rxreq_max; ++ ++ if (drv->rx_req) ++ return; + + /* -+ * In RX-only mode the serial clock is activated only after writing -+ * the expected amount of RX bytes into RXREQ register. + * To avoid receive overflows at high clocks it is better to request + * only the amount of bytes that fits into all FIFOs. This value + * depends on the FIFO size implemented in hardware. + */ -+ rxreq = sl->len - sl->rx_cnt; -+ rxreq_max = sl->rxfs << 2; -+ rxreq = min(rxreq_max, rxreq); ++ rxreq = drv->rx_todo; ++ rxreq_max = rx_fifo_size(drv) * 4; ++ if (rxreq > rxreq_max) ++ rxreq = rxreq_max; + -+ if (!sl->rx_req && rxreq && sl->rx_cnt < sl->len) { -+ ltq_writel(<q_spi_regs->rxreq, rxreq); -+ sl->rx_req = rxreq; -+ } ++ drv->rx_req = rxreq; ++ ltq_writel(&drv->regs->rxreq, rxreq); +} + -+static void ltq_spi_rxfifo_read(struct ltq_spi_slave *sl) ++void spi_init(void) +{ -+ u32 fstat, data, *rx32; -+ u16 fifo_fill; -+ u8 rxbv, shift, *rx8; ++} + -+ /* Determine how much FIFOs are filled with RX data */ -+ fstat = ltq_readl(<q_spi_regs->fstat); -+ fifo_fill = fstat & LTQ_SPI_FSTAT_RXFFL_MASK; ++struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, ++ unsigned int max_hz, unsigned int mode) ++{ ++ struct ltq_spi_drv_data *drv; + -+ /* -+ * The 32 bit FIFO is always used completely independent from the -+ * bits_per_word value. Thus four bytes have to be read at once -+ * per FIFO. -+ */ -+ rx32 = (u32 *) sl->rx; -+ while (sl->len - sl->rx_cnt >= 4 && fifo_fill) { -+ data = ltq_readl(<q_spi_regs->rb); -+ *rx32++ = data; -+ sl->rx_cnt += 4; -+ sl->rx_req -= 4; -+ sl->rx += 4; -+ fifo_fill--; -+ } ++ if (!spi_cs_is_valid(bus, cs)) ++ return NULL; + -+ /* -+ * If there are remaining bytes, read byte count from STAT.RXBV -+ * register and read the data byte-wise. -+ */ -+ while (fifo_fill && sl->rx_cnt < sl->len) { -+ fstat = ltq_readl(<q_spi_regs->stat); -+ rxbv = (fstat & LTQ_SPI_STAT_RXBV_MASK) >> -+ LTQ_SPI_STAT_RXBV_SHIFT; ++ drv = ltq_spi_slave_alloc(bus, cs); ++ if (!drv) ++ return NULL; + -+ if (!rxbv) -+ break; ++ drv->regs = (struct ltq_spi_regs *) CKSEG1ADDR(LTQ_SPI_BASE); + -+ data = ltq_readl(<q_spi_regs->rb); ++ hw_init(drv); + -+ shift = (rxbv - 1) * 8; -+ rx8 = sl->rx; ++ drv->max_hz = max_hz; ++ drv->mode = mode; + -+ while (rxbv) { -+ *rx8++ = (data >> shift) & 0xFF; -+ rxbv--; -+ shift -= 8; -+ sl->rx_cnt++; -+ sl->rx_req--; -+ sl->rx++; -+ } ++ return &drv->slave; ++} ++ ++void spi_free_slave(struct spi_slave *slave) ++{ ++ ltq_spi_slave_free(slave); ++} ++ ++static int ltq_spi_wait_ready(struct ltq_spi_drv_data *drv) ++{ ++ const unsigned long timeout = 20000; ++ unsigned long timebase; ++ ++ timebase = get_timer(0); ++ ++ do { ++ WATCHDOG_RESET(); + -+ fifo_fill--; ++ if (!hw_is_busy(drv)) ++ return 0; ++ } while (get_timer(timebase) < timeout); ++ ++ return 1; ++} ++ ++int spi_claim_bus(struct spi_slave *slave) ++{ ++ struct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave); ++ int ret; ++ ++ ret = ltq_spi_wait_ready(drv); ++ if (ret) { ++ debug("cannot claim bus\n"); ++ return ret; + } ++ ++ hw_enter_config_mode(drv); ++ hw_setup_clock_mode(drv, drv->mode); ++ hw_setup_speed_hz(drv, drv->max_hz); ++ hw_setup_bits_per_word(drv, drv->bits_per_word); ++ hw_enter_active_mode(drv); ++ ++ return 0; ++} ++ ++void spi_release_bus(struct spi_slave *slave) ++{ ++ struct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave); ++ ++ hw_enter_config_mode(drv); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, -+ const void *dout, void *din, unsigned long flags) ++ const void *dout, void *din, unsigned long flags) +{ -+ struct ltq_spi_slave *sl = to_ltq_spi_slave(slave); -+ int ret; ++ ++ struct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave); ++ int ret = 0; + + if (bitlen % 8) + return 1; @@ -8892,60 +8984,73 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + goto done; + } + -+ sl->len = bitlen / 8; -+ sl->tx = dout; -+ sl->rx = din; -+ sl->tx_cnt = 0; -+ sl->rx_cnt = 0; -+ sl->rx_req = 0; -+ + if (flags & SPI_XFER_BEGIN) + spi_cs_activate(slave); + -+ /* Enable transmitter */ -+ if (sl->tx) -+ ltq_clrbits(<q_spi_regs->con, LTQ_SPI_CON_TXOFF); ++ drv->tx = dout; ++ drv->tx_todo = 0; ++ drv->rx = din; ++ drv->rx_todo = 0; ++ hw_set_rxtx(drv); + -+ /* Enable receiver */ -+ if (sl->rx) -+ ltq_clrbits(<q_spi_regs->con, LTQ_SPI_CON_RXOFF); ++ if (drv->tx) { ++ drv->tx_todo = bitlen / 8; + -+ if (sl->tx) -+ ltq_spi_txfifo_write(sl); -+ else if (sl->rx) -+ ltq_spi_rx_request(sl); ++ tx_fifo_write(drv); ++ } + -+ while (sl->tx_cnt != sl->len && sl->rx_cnt != sl->len) { -+ if (sl->rx) { -+ ltq_spi_rxfifo_read(sl); ++ if (drv->rx) { ++ drv->rx_todo = bitlen / 8; + -+ if (sl->tx) -+ ltq_spi_txfifo_write(sl); -+ else -+ ltq_spi_rx_request(sl); -+ } else if (sl->tx) -+ ltq_spi_txfifo_write(sl); ++ if (!drv->tx) ++ rx_request(drv); + } + -+ ret = ltq_spi_wait_ready(sl); ++ for (;;) { ++ if (drv->tx) { ++ if (drv->rx && drv->rx_todo) ++ rx_fifo_read_full_duplex(drv); ++ ++ if (drv->tx_todo) ++ tx_fifo_write(drv); ++ else ++ goto done; ++ } else if (drv->rx) { ++ if (drv->rx_todo) { ++ rx_fifo_read_half_duplex(drv); ++ ++ if (drv->rx_todo) ++ rx_request(drv); ++ else ++ goto done; ++ } else { ++ goto done; ++ } ++ } ++ } + +done: -+ /* Disable transmitter and receiver */ -+ ltq_setbits(<q_spi_regs->con, LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); ++ ret = ltq_spi_wait_ready(drv); ++ ++ drv->rx = NULL; ++ drv->tx = NULL; ++ hw_set_rxtx(drv); + + if (flags & SPI_XFER_END) + spi_cs_deactivate(slave); + + return ret; +} +diff --git a/include/configs/easy50712.h b/include/configs/easy50712.h +new file mode 100644 +index 0000000..6d7988c --- /dev/null +++ b/include/configs/easy50712.h -@@ -0,0 +1,78 @@ +@@ -0,0 +1,79 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H @@ -8965,6 +9070,8 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_LTQ_SUPPORT_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */ + ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH ++ +#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ + +#define CONFIG_LTQ_SPL_COMP_LZO @@ -9019,14 +9126,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + CONFIG_ENV_UPDATE_UBOOT_NOR + +#endif /* __CONFIG_H */ +diff --git a/include/configs/easy80920.h b/include/configs/easy80920.h +new file mode 100644 +index 0000000..ad69bc2 --- /dev/null +++ b/include/configs/easy80920.h -@@ -0,0 +1,93 @@ +@@ -0,0 +1,92 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H @@ -9115,27 +9224,33 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + CONFIG_ENV_UPDATE_UBOOT_SF + +#endif /* __CONFIG_H */ +diff --git a/include/phy.h b/include/phy.h +index f0f522a..818bd7f 100644 --- a/include/phy.h +++ b/include/phy.h -@@ -220,6 +220,7 @@ int gen10g_discover_mmds(struct phy_devi - int phy_atheros_init(void); +@@ -214,6 +214,7 @@ int phy_atheros_init(void); int phy_broadcom_init(void); int phy_davicom_init(void); + int phy_et1011c_init(void); +int phy_lantiq_init(void); int phy_lxt_init(void); int phy_marvell_init(void); int phy_micrel_init(void); +diff --git a/spl/Makefile b/spl/Makefile +index b366ac2..46eb851 100644 --- a/spl/Makefile +++ b/spl/Makefile -@@ -81,6 +81,8 @@ LIBS-$(CONFIG_SPL_POST_MEM_SUPPORT) += p - LIBS-$(CONFIG_SPL_NET_SUPPORT) += net/libnet.o - LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/libnet.o - LIBS-$(CONFIG_SPL_ETH_SUPPORT) += drivers/net/phy/libphy.o +@@ -100,6 +100,8 @@ LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/net/phy/libphy.o + LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o + LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o + LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o +LIBS-$(CONFIG_SPL_LZMA_SUPPORT) += lib/lzma/liblzma.o +LIBS-$(CONFIG_SPL_LZO_SUPPORT) += lib/lzo/liblzo.o - ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) + ifneq ($(CONFIG_OMAP_COMMON),) LIBS-y += $(CPUDIR)/omap-common/libomap-common.o +diff --git a/tools/.gitignore b/tools/.gitignore +index a7fee26..4d56882 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -2,6 +2,7 @@ @@ -9146,9 +9261,11 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> /kwboot /mkenvimage /mkimage +diff --git a/tools/Makefile b/tools/Makefile +index ca76f94..ae1714b 100644 --- a/tools/Makefile +++ b/tools/Makefile -@@ -65,6 +65,7 @@ BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_lo +@@ -49,6 +49,7 @@ BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX) BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX) BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) @@ -9156,15 +9273,15 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkenvimage$(SFX) BIN_FILES-y += mkimage$(SFX) -@@ -89,6 +90,7 @@ OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envc - NOPED_OBJ_FILES-y += fit_image.o - OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o - OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o +@@ -95,6 +96,7 @@ OBJ_FILES-$(CONFIG_MX28) += mxsboot.o + OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o + OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o + OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o +OBJ_FILES-$(CONFIG_SOC_LANTIQ) += ltq-boot-image.o + OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o - NOPED_OBJ_FILES-y += aisimage.o - NOPED_OBJ_FILES-y += kwbimage.o -@@ -193,6 +195,10 @@ $(obj)img2srec$(SFX): $(obj)img2srec.o + +@@ -195,6 +197,10 @@ $(obj)img2srec$(SFX): $(obj)img2srec.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ @@ -9175,14 +9292,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> $(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ +diff --git a/tools/ltq-boot-image.c b/tools/ltq-boot-image.c +new file mode 100644 +index 0000000..75a188c --- /dev/null +++ b/tools/ltq-boot-image.c -@@ -0,0 +1,316 @@ +@@ -0,0 +1,315 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <stdio.h> @@ -9409,7 +9528,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + int fd; + -+ fd = open(name, O_RDWR | O_CREAT | O_TRUNC | O_SYNC | O_BINARY, 0666); ++ fd = open(name, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, 0666); + if (0 > fd) { + fprintf(stderr, "Cannot open %s: %s\n", name, + strerror(errno)); @@ -9494,3 +9613,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return EXIT_FAILURE; +} +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0014-sf-macronix-add-support-for-MX25L25635E.patch b/package/boot/uboot-lantiq/patches/0014-sf-macronix-add-support-for-MX25L25635E.patch deleted file mode 100644 index 8e33836..0000000 --- a/package/boot/uboot-lantiq/patches/0014-sf-macronix-add-support-for-MX25L25635E.patch +++ /dev/null @@ -1,21 +0,0 @@ -From 0f31fef3d6a5110684ea31c5064c45fc448013d6 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 15:14:24 +0100 -Subject: sf: macronix: add support for MX25L25635E - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/macronix.c -+++ b/drivers/mtd/spi/macronix.c -@@ -79,6 +79,11 @@ static const struct macronix_spi_flash_p - .nr_blocks = 256, - .name = "MX25L12855E", - }, -+ { -+ .idcode = 0x2019, -+ .nr_blocks = 512, -+ .name = "MX25L25635E", -+ }, - }; - - static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash) diff --git a/package/boot/uboot-lantiq/patches/0015-MIPS-lantiq-add-support-for-Lantiq-XWAY-ARX100-SoC-f.patch b/package/boot/uboot-lantiq/patches/0015-MIPS-lantiq-add-support-for-Lantiq-XWAY-ARX100-SoC-f.patch new file mode 100644 index 0000000..6479ff9 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0015-MIPS-lantiq-add-support-for-Lantiq-XWAY-ARX100-SoC-f.patch @@ -0,0 +1,1283 @@ +From 4953294aa8f8b9023e6b5f7f39059706c72d916c Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 9 Dec 2012 17:54:56 +0100 +Subject: MIPS: lantiq: add support for Lantiq XWAY ARX100 SoC family + +Signed-off-by: Luka Perkov <luka@openwrt.org> +Signed-off-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/arch/mips/cpu/mips32/arx100/Makefile b/arch/mips/cpu/mips32/arx100/Makefile +new file mode 100644 +index 0000000..98f5f73 +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/Makefile +@@ -0,0 +1,31 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(SOC).o ++ ++COBJS-y += cgu.o chipid.o ebu.o mem.o pmu.o rcu.o ++SOBJS-y += cgu_init.o mem_init.o ++ ++COBJS := $(COBJS-y) ++SOBJS := $(SOBJS-y) ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) ++ ++all: $(LIB) ++ ++$(LIB): $(obj).depend $(OBJS) ++ $(call cmd_link_o_target, $(OBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/arch/mips/cpu/mips32/arx100/cgu.c b/arch/mips/cpu/mips32/arx100/cgu.c +new file mode 100644 +index 0000000..6e71ee7 +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/cgu.c +@@ -0,0 +1,109 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/arch/soc.h> ++#include <asm/lantiq/clk.h> ++#include <asm/lantiq/io.h> ++ ++#define CGU_SYS_DDR_SEL (1 << 0) ++#define CGU_SYS_CPU_SEL (1 << 2) ++#define CGU_SYS_SYS_SHIFT 3 ++#define CGU_SYS_SYS_MASK (0x3 << CGU_SYS_SYS_SHIFT) ++#define CGU_SYS_FPI_SEL (1 << 6) ++#define CGU_SYS_PPE_SEL (1 << 7) ++ ++struct ltq_cgu_regs { ++ u32 rsvd0; ++ __be32 pll0_cfg; /* PLL0 config */ ++ __be32 pll1_cfg; /* PLL1 config */ ++ u32 rsvd2; ++ __be32 sys; /* System clock */ ++ __be32 update; /* CGU update control */ ++ __be32 if_clk; /* Interface clock */ ++ u32 rsvd3; ++ __be32 smd; /* SDRAM Memory Control */ ++ u32 rsvd4; ++ __be32 ct1_sr; /* CT status 1 */ ++ __be32 ct_kval; /* CT K value */ ++ __be32 pcm_cr; /* PCM control */ ++}; ++ ++static struct ltq_cgu_regs *ltq_cgu_regs = ++ (struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE); ++ ++static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift) ++{ ++ return (ltq_readl(<q_cgu_regs->sys) & mask) >> shift; ++} ++ ++static unsigned long ltq_get_system_clock(void) ++{ ++ u32 sys_sel; ++ unsigned long clk; ++ ++ sys_sel = ltq_cgu_sys_readl(CGU_SYS_SYS_MASK, CGU_SYS_SYS_SHIFT); ++ ++ switch (sys_sel) { ++ case 0: ++ clk = CLOCK_333_MHZ; ++ break; ++ case 2: ++ clk = CLOCK_393_MHZ; ++ break; ++ default: ++ clk = 0; ++ break; ++ } ++ ++ return clk; ++} ++ ++unsigned long ltq_get_io_region_clock(void) ++{ ++ u32 ddr_sel; ++ unsigned long clk; ++ ++ ddr_sel = ltq_cgu_sys_readl(1, CGU_SYS_DDR_SEL); ++ ++ if (ddr_sel) ++ clk = ltq_get_system_clock() / 3; ++ else ++ clk = ltq_get_system_clock() / 2; ++ ++ return clk; ++} ++ ++unsigned long ltq_get_cpu_clock(void) ++{ ++ u32 cpu_sel; ++ unsigned long clk; ++ ++ cpu_sel = ltq_cgu_sys_readl(1, CGU_SYS_CPU_SEL); ++ ++ if (cpu_sel) ++ clk = ltq_get_io_region_clock(); ++ else ++ clk = ltq_get_system_clock(); ++ ++ return clk; ++} ++ ++unsigned long ltq_get_bus_clock(void) ++{ ++ u32 fpi_sel; ++ unsigned long clk; ++ ++ fpi_sel = ltq_cgu_sys_readl(1, CGU_SYS_FPI_SEL); ++ ++ if (fpi_sel) ++ clk = ltq_get_io_region_clock() / 2; ++ else ++ clk = ltq_get_io_region_clock(); ++ ++ return clk; ++} +diff --git a/arch/mips/cpu/mips32/arx100/cgu_init.S b/arch/mips/cpu/mips32/arx100/cgu_init.S +new file mode 100644 +index 0000000..ed70cb2 +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/cgu_init.S +@@ -0,0 +1,105 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <config.h> ++#include <asm/asm.h> ++#include <asm/regdef.h> ++#include <asm/addrspace.h> ++#include <asm/arch/soc.h> ++ ++/* CGU module register */ ++#define CGU_PLL0_CFG 0x0004 /* PLL0 config */ ++#define CGU_PLL1_CFG 0x0008 /* PLL1 config */ ++#define CGU_SYS 0x0010 /* System clock */ ++#define CGU_UPDATE 0x0014 /* Clock update control */ ++ ++/* Valid SYS.PPE_SEL values */ ++#define CGU_SYS_PPESEL_SHIFT 7 ++#define CGU_SYS_PPESEL_250_MHZ (0x1 << CGU_SYS_PPESEL_SHIFT) ++ ++/* Valid SYS.SYS_SEL values */ ++#define CGU_SYS_SYSSEL_SHIFT 3 ++#define CGU_SYS_SYSSEL_PLL0_333_MHZ (0x0 << CGU_SYS_SYSSEL_SHIFT) ++#define CGU_SYS_SYSSEL_PLL1_393_MHZ (0x2 << CGU_SYS_SYSSEL_SHIFT) ++ ++/* Valid SYS.CPU_SEL values */ ++#define CGU_SYS_CPUSEL_SHIFT 2 ++#define CGU_SYS_CPUSEL_EQUAL_SYSCLK (0x0 << CGU_SYS_CPUSEL_SHIFT) ++#define CGU_SYS_CPUSEL_EQUAL_DDRCLK (0x1 << CGU_SYS_CPUSEL_SHIFT) ++ ++/* Valid SYS.DDR_SEL values */ ++#define CGU_SYS_DDRSEL_HALF_SYSCLK 0x0 ++#define CGU_SYS_DDRSEL_THIRD_SYSCLK 0x1 ++ ++#define CGU_UPDATE_UPD 0x1 ++ ++#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_393_DDR_197) ++#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ ++#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL1_393_MHZ ++#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_SYSCLK ++#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK ++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_197_DDR_197) ++#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ ++#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL1_393_MHZ ++#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK ++#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK ++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_333_DDR_167) ++#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ ++#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL0_333_MHZ ++#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_SYSCLK ++#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK ++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_167_DDR_167) ++#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ ++#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL0_333_MHZ ++#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK ++#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_HALF_SYSCLK ++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_131_DDR_131) ++#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ ++#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL1_393_MHZ ++#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK ++#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_THIRD_SYSCLK ++#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_111_DDR_111) ++#define CGU_SYS_PPESEL_CONFIG CGU_SYS_PPESEL_250_MHZ ++#define CGU_SYS_SYSSEL_CONFIG CGU_SYS_SYSSEL_PLL0_333_MHZ ++#define CGU_SYS_CPUSEL_CONFIG CGU_SYS_CPUSEL_EQUAL_DDRCLK ++#define CGU_SYS_DDRSEL_CONFIG CGU_SYS_DDRSEL_THIRD_SYSCLK ++#else ++#error "Invalid system clock configuration!" ++#endif ++ ++/* Build register values */ ++#define CGU_SYS_VALUE (CGU_SYS_PPESEL_CONFIG | \ ++ CGU_SYS_SYSSEL_CONFIG | \ ++ CGU_SYS_CPUSEL_CONFIG | \ ++ CGU_SYS_DDRSEL_CONFIG) ++ ++ .set noreorder ++ ++LEAF(ltq_cgu_init) ++ /* Load current CGU register value */ ++ li t0, (LTQ_CGU_BASE | KSEG1) ++ lw t1, CGU_SYS(t0) ++ ++ /* Load target CGU register values */ ++ li t2, CGU_SYS_VALUE ++ ++ /* Only update registers if values differ */ ++ beq t1, t2, finished ++ nop ++ ++ /* Store target register values */ ++ sw t2, CGU_SYS(t0) ++ ++ /* Trigger CGU update */ ++ li t1, CGU_UPDATE_UPD ++ sw t1, CGU_UPDATE(t0) ++ ++finished: ++ jr ra ++ nop ++ ++ END(ltq_cgu_init) +diff --git a/arch/mips/cpu/mips32/arx100/chipid.c b/arch/mips/cpu/mips32/arx100/chipid.c +new file mode 100644 +index 0000000..e97d7ef +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/chipid.c +@@ -0,0 +1,60 @@ ++/* ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/lantiq/io.h> ++#include <asm/lantiq/chipid.h> ++#include <asm/arch/soc.h> ++ ++#define LTQ_CHIPID_VERSION_SHIFT 28 ++#define LTQ_CHIPID_VERSION_MASK (0xF << LTQ_CHIPID_VERSION_SHIFT) ++#define LTQ_CHIPID_PNUM_SHIFT 12 ++#define LTQ_CHIPID_PNUM_MASK (0xFFFF << LTQ_CHIPID_PNUM_SHIFT) ++ ++struct ltq_chipid_regs { ++ u32 manid; /* Manufacturer identification */ ++ u32 chipid; /* Chip identification */ ++}; ++ ++static struct ltq_chipid_regs *ltq_chipid_regs = ++ (struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE); ++ ++unsigned int ltq_chip_version_get(void) ++{ ++ u32 chipid; ++ ++ chipid = ltq_readl(<q_chipid_regs->chipid); ++ ++ return (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT; ++} ++ ++unsigned int ltq_chip_partnum_get(void) ++{ ++ u32 chipid; ++ ++ chipid = ltq_readl(<q_chipid_regs->chipid); ++ ++ return (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT; ++} ++ ++const char *ltq_chip_partnum_str(void) ++{ ++ enum ltq_chip_partnum partnum = ltq_chip_partnum_get(); ++ ++ switch (partnum) { ++ case LTQ_SOC_ARX188: ++ return "ARX188"; ++ case LTQ_SOC_ARX186: ++ case LTQ_SOC_ARX186_2: ++ return "ARX186"; ++ case LTQ_SOC_ARX182: ++ return "ARX182"; ++ default: ++ printf("Unknown partnum: %x\n", partnum); ++ } ++ ++ return ""; ++} +diff --git a/arch/mips/cpu/mips32/arx100/config.mk b/arch/mips/cpu/mips32/arx100/config.mk +new file mode 100644 +index 0000000..442156a +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/config.mk +@@ -0,0 +1,30 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,) ++PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_XRX) ++ ++ifdef CONFIG_SPL_BUILD ++PF_ABICALLS := -mno-abicalls ++PF_PIC := -fno-pic ++PF_PIE := ++USE_PRIVATE_LIBGCC := yes ++endif ++ ++LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o ++ ++ifndef CONFIG_SPL_BUILD ++ifdef CONFIG_SYS_BOOT_SFSPL ++ALL-y += $(obj)u-boot.ltq.sfspl ++ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl ++ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.sfspl ++endif ++ifdef CONFIG_SYS_BOOT_NORSPL ++ALL-y += $(obj)u-boot.ltq.norspl ++ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl ++ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl ++endif ++endif +diff --git a/arch/mips/cpu/mips32/arx100/ebu.c b/arch/mips/cpu/mips32/arx100/ebu.c +new file mode 100644 +index 0000000..4ab3cf1 +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/ebu.c +@@ -0,0 +1,111 @@ ++/* ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/arch/soc.h> ++#include <asm/lantiq/io.h> ++ ++#define EBU_ADDRSEL_MASK(mask) ((mask & 0xf) << 4) ++#define EBU_ADDRSEL_REGEN (1 << 0) ++ ++#define EBU_CON_WRDIS (1 << 31) ++#define EBU_CON_AGEN_DEMUX (0x0 << 24) ++#define EBU_CON_AGEN_MUX (0x2 << 24) ++#define EBU_CON_SETUP (1 << 22) ++#define EBU_CON_WAIT_DIS (0x0 << 20) ++#define EBU_CON_WAIT_ASYNC (0x1 << 20) ++#define EBU_CON_WAIT_SYNC (0x2 << 20) ++#define EBU_CON_WINV (1 << 19) ++#define EBU_CON_PW_8BIT (0x0 << 16) ++#define EBU_CON_PW_16BIT (0x1 << 16) ++#define EBU_CON_ALEC(cycles) ((cycles & 0x3) << 14) ++#define EBU_CON_BCGEN_CS (0x0 << 12) ++#define EBU_CON_BCGEN_INTEL (0x1 << 12) ++#define EBU_CON_BCGEN_MOTOROLA (0x2 << 12) ++#define EBU_CON_WAITWRC(cycles) ((cycles & 0x7) << 8) ++#define EBU_CON_WAITRDC(cycles) ((cycles & 0x3) << 6) ++#define EBU_CON_HOLDC(cycles) ((cycles & 0x3) << 4) ++#define EBU_CON_RECOVC(cycles) ((cycles & 0x3) << 2) ++#define EBU_CON_CMULT_1 0x0 ++#define EBU_CON_CMULT_4 0x1 ++#define EBU_CON_CMULT_8 0x2 ++#define EBU_CON_CMULT_16 0x3 ++ ++#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) ++#define ebu_region0_enable 1 ++#else ++#define ebu_region0_enable 0 ++#endif ++ ++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) ++#define ebu_region1_enable 1 ++#else ++#define ebu_region1_enable 0 ++#endif ++ ++struct ltq_ebu_regs { ++ u32 clc; ++ u32 rsvd0; ++ u32 id; ++ u32 rsvd1; ++ u32 con; ++ u32 rsvd2[3]; ++ u32 addr_sel_0; ++ u32 addr_sel_1; ++ u32 addr_sel_2; ++ u32 addr_sel_3; ++ u32 rsvd3[12]; ++ u32 con_0; ++ u32 con_1; ++ u32 con_2; ++ u32 con_3; ++}; ++ ++static struct ltq_ebu_regs *ltq_ebu_regs = ++ (struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE); ++ ++void ltq_ebu_init(void) ++{ ++ if (ebu_region0_enable) { ++ /* ++ * Map EBU region 0 to range 0x10000000-0x13ffffff and enable ++ * region control. This supports up to 32 MiB NOR flash in ++ * bank 0. ++ */ ++ ltq_writel(<q_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE | ++ EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN); ++ ++ ltq_writel(<q_ebu_regs->con_0, EBU_CON_AGEN_DEMUX | ++ EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT | ++ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL | ++ EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) | ++ EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) | ++ EBU_CON_CMULT_16); ++ } else ++ ltq_clrbits(<q_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN); ++ ++ if (ebu_region1_enable) { ++ /* ++ * Map EBU region 1 to range 0x14000000-0x13ffffff and enable ++ * region control. This supports NAND flash in bank 1. ++ */ ++ ltq_writel(<q_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE | ++ EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN); ++ ++ ltq_writel(<q_ebu_regs->con_1, EBU_CON_AGEN_DEMUX | ++ EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT | ++ EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL | ++ EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) | ++ EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) | ++ EBU_CON_CMULT_4); ++ } else ++ ltq_clrbits(<q_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN); ++} ++ ++void *flash_swap_addr(unsigned long addr) ++{ ++ return (void *)(addr ^ 2); ++} +diff --git a/arch/mips/cpu/mips32/arx100/mem.c b/arch/mips/cpu/mips32/arx100/mem.c +new file mode 100644 +index 0000000..1fba7cd +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/mem.c +@@ -0,0 +1,30 @@ ++/* ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/arch/soc.h> ++#include <asm/lantiq/io.h> ++ ++static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE); ++ ++static inline u32 ltq_mc_dc_read(u32 index) ++{ ++ return ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_DC_OFFSET(index)); ++} ++ ++phys_size_t initdram(int board_type) ++{ ++ u32 col, row, dc04, dc19, dc20; ++ ++ dc04 = ltq_mc_dc_read(4); ++ dc19 = ltq_mc_dc_read(19); ++ dc20 = ltq_mc_dc_read(20); ++ ++ row = (dc04 & 0xF) - ((dc19 & 0x700) >> 8); ++ col = ((dc04 & 0xF00) >> 8) - (dc20 & 0x7); ++ ++ return (1 << (row + col)) * 4 * 2; ++} +diff --git a/arch/mips/cpu/mips32/arx100/mem_init.S b/arch/mips/cpu/mips32/arx100/mem_init.S +new file mode 100644 +index 0000000..5d70842 +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/mem_init.S +@@ -0,0 +1,114 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <config.h> ++#include <asm/asm.h> ++#include <asm/regdef.h> ++#include <asm/addrspace.h> ++#include <asm/arch/soc.h> ++ ++/* Must be configured in BOARDDIR */ ++#include <ddr_settings.h> ++ ++#define LTQ_MC_GEN_ERRCAUSE 0x0010 ++#define LTQ_MC_GEN_ERRADDR 0x0020 ++#define LTQ_MC_GEN_CON 0x0060 ++#define LTQ_MC_GEN_STAT 0x0070 ++#define LTQ_MC_GEN_CON_SRAM_DDR_ENABLE 0xD ++#define LTQ_MC_GEN_STAT_DLCK_PWRON 0xC ++ ++#define LTQ_MC_DDR_DC03_MC_START 0x100 ++ ++ /* Store given value in MC DDR CCRx register */ ++ .macro dc_sw num, val ++ li t2, \val ++ sw t2, LTQ_MC_DDR_DC_OFFSET(\num)(t1) ++ .endm ++ ++LEAF(ltq_mem_init) ++ /* Load MC General and MC DDR module base */ ++ li t0, (LTQ_MC_GEN_BASE | KSEG1) ++ li t1, (LTQ_MC_DDR_BASE | KSEG1) ++ ++ /* Clear access error log registers */ ++ sw zero, LTQ_MC_GEN_ERRCAUSE(t0) ++ sw zero, LTQ_MC_GEN_ERRADDR(t0) ++ ++ /* Enable DDR and SRAM module in memory controller */ ++ li t2, LTQ_MC_GEN_CON_SRAM_DDR_ENABLE ++ sw t2, LTQ_MC_GEN_CON(t0) ++ ++ /* Clear start bit of DDR memory controller */ ++ sw zero, LTQ_MC_DDR_DC_OFFSET(3)(t1) ++ ++ /* Init memory controller registers with values ddr_settings.h */ ++ dc_sw 0, MC_DC00_VALUE ++ dc_sw 1, MC_DC01_VALUE ++ dc_sw 2, MC_DC02_VALUE ++ dc_sw 4, MC_DC04_VALUE ++ dc_sw 5, MC_DC05_VALUE ++ dc_sw 6, MC_DC06_VALUE ++ dc_sw 7, MC_DC07_VALUE ++ dc_sw 8, MC_DC08_VALUE ++ dc_sw 9, MC_DC09_VALUE ++ ++ dc_sw 10, MC_DC10_VALUE ++ dc_sw 11, MC_DC11_VALUE ++ dc_sw 12, MC_DC12_VALUE ++ dc_sw 13, MC_DC13_VALUE ++ dc_sw 14, MC_DC14_VALUE ++ dc_sw 15, MC_DC15_VALUE ++ dc_sw 16, MC_DC16_VALUE ++ dc_sw 17, MC_DC17_VALUE ++ dc_sw 18, MC_DC18_VALUE ++ dc_sw 19, MC_DC19_VALUE ++ ++ dc_sw 20, MC_DC20_VALUE ++ dc_sw 21, MC_DC21_VALUE ++ dc_sw 22, MC_DC22_VALUE ++ dc_sw 23, MC_DC23_VALUE ++ dc_sw 24, MC_DC24_VALUE ++ dc_sw 25, MC_DC25_VALUE ++ dc_sw 26, MC_DC26_VALUE ++ dc_sw 27, MC_DC27_VALUE ++ dc_sw 28, MC_DC28_VALUE ++ dc_sw 29, MC_DC29_VALUE ++ ++ dc_sw 30, MC_DC30_VALUE ++ dc_sw 31, MC_DC31_VALUE ++ dc_sw 32, MC_DC32_VALUE ++ dc_sw 33, MC_DC33_VALUE ++ dc_sw 34, MC_DC34_VALUE ++ dc_sw 35, MC_DC35_VALUE ++ dc_sw 36, MC_DC36_VALUE ++ dc_sw 37, MC_DC37_VALUE ++ dc_sw 38, MC_DC38_VALUE ++ dc_sw 39, MC_DC39_VALUE ++ ++ dc_sw 40, MC_DC40_VALUE ++ dc_sw 41, MC_DC41_VALUE ++ dc_sw 42, MC_DC42_VALUE ++ dc_sw 43, MC_DC43_VALUE ++ dc_sw 44, MC_DC44_VALUE ++ dc_sw 45, MC_DC45_VALUE ++ dc_sw 46, MC_DC46_VALUE ++ ++ /* Set start bit of DDR memory controller */ ++ li t2, LTQ_MC_DDR_DC03_MC_START ++ sw t2, LTQ_MC_DDR_DC_OFFSET(3)(t1) ++ ++ /* Wait until DLL has locked and core is ready for data transfers */ ++wait_ready: ++ lw t2, LTQ_MC_GEN_STAT(t0) ++ li t3, LTQ_MC_GEN_STAT_DLCK_PWRON ++ and t2, t3 ++ bne t2, t3, wait_ready ++ ++finished: ++ jr ra ++ ++ END(ltq_mem_init) +diff --git a/arch/mips/cpu/mips32/arx100/pmu.c b/arch/mips/cpu/mips32/arx100/pmu.c +new file mode 100644 +index 0000000..d2afe96 +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/pmu.c +@@ -0,0 +1,120 @@ ++/* ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/lantiq/io.h> ++#include <asm/lantiq/pm.h> ++#include <asm/arch/soc.h> ++ ++#define LTQ_PMU_PWDCR_RESERVED 0xE00C200C ++ ++#define LTQ_PMU_PWDCR_SWITCH (1 << 28) ++#define LTQ_PMU_PWDCR_USB1 (1 << 27) ++#define LTQ_PMU_PWDCR_USB1_PHY (1 << 26) ++#define LTQ_PMU_PWDCR_TDM (1 << 25) ++#define LTQ_PMU_PWDCR_DDR_MEM (1 << 24) ++#define LTQ_PMU_PWDCR_PPE_DP (1 << 23) ++#define LTQ_PMU_PWDCR_PPE_EMA (1 << 22) ++#define LTQ_PMU_PWDCR_PPE_TC (1 << 21) ++#define LTQ_PMU_PWDCR_DEU (1 << 20) ++#define LTQ_PMU_PWDCR_UART1 (1 << 17) ++#define LTQ_PMU_PWDCR_SDIO (1 << 16) ++#define LTQ_PMU_PWDCR_AHB (1 << 15) ++#define LTQ_PMU_PWDCR_FPI0 (1 << 14) ++#define LTQ_PMU_PWDCR_GPTC (1 << 12) ++#define LTQ_PMU_PWDCR_LEDC (1 << 11) ++#define LTQ_PMU_PWDCR_EBU (1 << 10) ++#define LTQ_PMU_PWDCR_DSL (1 << 9) ++#define LTQ_PMU_PWDCR_SPI (1 << 8) ++#define LTQ_PMU_PWDCR_UART0 (1 << 7) ++#define LTQ_PMU_PWDCR_USB (1 << 6) ++#define LTQ_PMU_PWDCR_DMA (1 << 5) ++#define LTQ_PMU_PWDCR_PCI (1 << 4) ++#define LTQ_PMU_PWDCR_FPI1 (1 << 1) ++#define LTQ_PMU_PWDCR_USB0_PHY (1 << 0) ++ ++struct ltq_pmu_regs { ++ u32 rsvd0[7]; ++ __be32 pwdcr; ++ __be32 sr; ++}; ++ ++static struct ltq_pmu_regs *ltq_pmu_regs = ++ (struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE); ++ ++u32 ltq_pm_map(enum ltq_pm_modules module) ++{ ++ u32 val; ++ ++ switch (module) { ++ case LTQ_PM_CORE: ++ val = LTQ_PMU_PWDCR_DDR_MEM | LTQ_PMU_PWDCR_UART1 | ++ LTQ_PMU_PWDCR_FPI0 | LTQ_PMU_PWDCR_LEDC | ++ LTQ_PMU_PWDCR_EBU; ++ break; ++ case LTQ_PM_DMA: ++ val = LTQ_PMU_PWDCR_DMA; ++ break; ++ case LTQ_PM_ETH: ++ val = LTQ_PMU_PWDCR_SWITCH | LTQ_PMU_PWDCR_PPE_DP | ++ LTQ_PMU_PWDCR_PPE_EMA | LTQ_PMU_PWDCR_PPE_TC; ++ break; ++ case LTQ_PM_SPI: ++ val = LTQ_PMU_PWDCR_SPI; ++ break; ++ default: ++ val = 0; ++ break; ++ } ++ ++ return val; ++} ++ ++int ltq_pm_enable(enum ltq_pm_modules module) ++{ ++ const unsigned long timeout = 1000; ++ unsigned long timebase; ++ u32 sr, val; ++ ++ val = ltq_pm_map(module); ++ if (unlikely(!val)) ++ return 1; ++ ++ ltq_clrbits(<q_pmu_regs->pwdcr, val); ++ ++ timebase = get_timer(0); ++ ++ do { ++ sr = ltq_readl(<q_pmu_regs->sr); ++ if (~sr & val) ++ return 0; ++ } while (get_timer(timebase) < timeout); ++ ++ return 1; ++} ++ ++int ltq_pm_disable(enum ltq_pm_modules module) ++{ ++ u32 val; ++ ++ val = ltq_pm_map(module); ++ if (unlikely(!val)) ++ return 1; ++ ++ ltq_setbits(<q_pmu_regs->pwdcr, val); ++ ++ return 0; ++} ++ ++void ltq_pmu_init(void) ++{ ++ u32 set, clr; ++ ++ clr = ltq_pm_map(LTQ_PM_CORE); ++ set = ~(LTQ_PMU_PWDCR_RESERVED | clr); ++ ++ ltq_clrsetbits(<q_pmu_regs->pwdcr, clr, set); ++} +diff --git a/arch/mips/cpu/mips32/arx100/rcu.c b/arch/mips/cpu/mips32/arx100/rcu.c +new file mode 100644 +index 0000000..4ff6935 +--- /dev/null ++++ b/arch/mips/cpu/mips32/arx100/rcu.c +@@ -0,0 +1,130 @@ ++/* ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/lantiq/io.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/cpu.h> ++#include <asm/arch/soc.h> ++ ++#define LTQ_RCU_RD_SRST (1 << 30) /* Global SW Reset */ ++#define LTQ_RCU_RD_USB1 (1 << 28) /* USB1 MAC and PHY */ ++#define LTQ_RCU_RD_REG25_PD (1 << 26) /* Power down 2.5V regulator */ ++#define LTQ_RCU_RD_PPE_ATM_TC (1 << 22) /* PPE ATM TC */ ++#define LTQ_RCU_RD_ETHSW (1 << 21) /* Ethernet switch */ ++#define LTQ_RCU_RD_DSP_DEN (1 << 20) /* Enable DSP JTAG */ ++#define LTQ_RCU_RD_TDM (1 << 19) /* TDM module interface */ ++#define LTQ_RCU_RD_MC (1 << 14) /* Memory Controller */ ++#define LTQ_RCU_RD_PCI (1 << 13) /* PCI core */ ++#define LTQ_RCU_RD_SDIO (1 << 10) /* SDIO core */ ++#define LTQ_RCU_RD_DMA (1 << 9) /* DMA core */ ++#define LTQ_RCU_RD_PPE (1 << 8) /* PPE core */ ++#define LTQ_RCU_RD_ARC_DFE (1 << 7) /* ARC/DFE core */ ++#define LTQ_RCU_RD_AHB (1 << 6) /* AHB bus */ ++#define LTQ_RCU_RD_USB (1 << 4) /* USB and Phy core */ ++#define LTQ_RCU_RD_FPI (1 << 2) /* FPI bus */ ++#define LTQ_RCU_RD_CPU0 (1 << 1) /* CPU0 subsystem */ ++#define LTQ_RCU_RD_HRST (1 << 0) /* HW reset via HRST pin */ ++ ++#define LTQ_RCU_STAT_BOOT_SHIFT 17 ++#define LTQ_RCU_STAT_BOOT_MASK (0xf << LTQ_RCU_STAT_BOOT_SHIFT) ++ ++struct ltq_rcu_regs { ++ u32 rsvd0[4]; ++ __be32 req; /* Reset request */ ++ __be32 stat; /* Reset status */ ++ __be32 usb0_cfg; /* USB0 config */ ++ u32 rsvd1[2]; ++ __be32 pci_rdy; /* PCI boot ready */ ++ __be32 ppe_conf; /* PPE config */ ++ u32 rsvd2; ++ __be32 usb1_cfg; /* USB1 config */ ++}; ++ ++static struct ltq_rcu_regs *ltq_rcu_regs = ++ (struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE); ++ ++u32 ltq_reset_map(enum ltq_reset_modules module) ++{ ++ u32 val; ++ ++ switch (module) { ++ case LTQ_RESET_CORE: ++ case LTQ_RESET_SOFT: ++ val = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU0; ++ break; ++ case LTQ_RESET_DMA: ++ val = LTQ_RCU_RD_DMA; ++ break; ++ case LTQ_RESET_ETH: ++ val = LTQ_RCU_RD_PPE | LTQ_RCU_RD_ETHSW; ++ break; ++ case LTQ_RESET_HARD: ++ val = LTQ_RCU_RD_HRST; ++ break; ++ default: ++ val = 0; ++ break; ++ } ++ ++ return val; ++} ++ ++int ltq_reset_activate(enum ltq_reset_modules module) ++{ ++ u32 val; ++ ++ val = ltq_reset_map(module); ++ if (unlikely(!val)) ++ return 1; ++ ++ ltq_setbits(<q_rcu_regs->req, val); ++ ++ return 0; ++} ++ ++int ltq_reset_deactivate(enum ltq_reset_modules module) ++{ ++ u32 val; ++ ++ val = ltq_reset_map(module); ++ if (unlikely(!val)) ++ return 1; ++ ++ ltq_clrbits(<q_rcu_regs->req, val); ++ ++ return 0; ++} ++ ++enum ltq_boot_select ltq_boot_select(void) ++{ ++ u32 stat; ++ unsigned int bootstrap; ++ ++ stat = ltq_readl(<q_rcu_regs->stat); ++ bootstrap = (stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT; ++ ++ switch (bootstrap) { ++ case 0: ++ return BOOT_NOR_NO_BOOTROM; ++ case 1: ++ return BOOT_RGMII0; ++ case 2: ++ return BOOT_NOR; ++ case 3: ++ return BOOT_MII0; ++ case 5: ++ return BOOT_RMII0; ++ case 6: ++ return BOOT_PCI; ++ case 8: ++ return BOOT_UART; ++ case 10: ++ return BOOT_SPI; ++ default: ++ return BOOT_UNKNOWN; ++ } ++} +diff --git a/arch/mips/cpu/mips32/lantiq-common/cpu.c b/arch/mips/cpu/mips32/lantiq-common/cpu.c +index 4a7acdf..aa37b35 100644 +--- a/arch/mips/cpu/mips32/lantiq-common/cpu.c ++++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c +@@ -20,6 +20,7 @@ static const char ltq_bootsel_strings[][16] = { + "PCI", + "MII0", + "RMII0", ++ "RGMII0", + "RGMII1", + "unknown", + }; +diff --git a/arch/mips/cpu/mips32/lantiq-common/start.S b/arch/mips/cpu/mips32/lantiq-common/start.S +index 481d739..fc8276e 100644 +--- a/arch/mips/cpu/mips32/lantiq-common/start.S ++++ b/arch/mips/cpu/mips32/lantiq-common/start.S +@@ -64,6 +64,11 @@ + #define STATUS_LANTIQ (STATUS_MIPS24K | STATUS_MIPS32_64) + #endif + ++#ifdef CONFIG_SOC_XWAY_ARX100 ++#define CONFIG0_LANTIQ (CONFIG0_MIPS34K | CONFIG0_MIPS32_64) ++#define STATUS_LANTIQ (STATUS_MIPS34K | STATUS_MIPS32_64) ++#endif ++ + #ifdef CONFIG_SOC_XWAY_VRX200 + #define CONFIG0_LANTIQ (CONFIG0_MIPS34K | CONFIG0_MIPS32_64) + #define STATUS_LANTIQ (STATUS_MIPS34K | STATUS_MIPS32_64) +diff --git a/arch/mips/include/asm/arch-arx100/config.h b/arch/mips/include/asm/arch-arx100/config.h +new file mode 100644 +index 0000000..1a6c9bc +--- /dev/null ++++ b/arch/mips/include/asm/arch-arx100/config.h +@@ -0,0 +1,175 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ * ++ * Common board configuration for Lantiq XWAY ARX100 family ++ * ++ * Use following defines in your board config to enable specific features ++ * and drivers for this SoC: ++ * ++ * CONFIG_LTQ_SUPPORT_UART ++ * - support the Danube ASC/UART interface and console ++ * ++ * CONFIG_LTQ_SUPPORT_NOR_FLASH ++ * - support a parallel NOR flash via the CFI interface in flash bank 0 ++ * ++ * CONFIG_LTQ_SUPPORT_ETHERNET ++ * - support the Danube ETOP and MAC interface ++ * ++ * CONFIG_LTQ_SUPPORT_SPI_FLASH ++ * - support the Danube SPI interface and serial flash drivers ++ * - specific SPI flash drivers must be configured separately ++ */ ++ ++#ifndef __ARX100_CONFIG_H__ ++#define __ARX100_CONFIG_H__ ++ ++/* CPU and SoC type */ ++#define CONFIG_SOC_LANTIQ ++#define CONFIG_SOC_XWAY_ARX100 ++ ++/* Cache configuration */ ++#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT ++#define CONFIG_SYS_DCACHE_SIZE (16 * 1024) ++#define CONFIG_SYS_ICACHE_SIZE (32 * 1024) ++#define CONFIG_SYS_CACHELINE_SIZE 32 ++#define CONFIG_SYS_MIPS_CACHE_EXT_INIT ++ ++/* ++ * Supported clock modes ++ * PLL0: rational PLL running at 500 MHz ++ * PLL1: fractional PLL running at 393.219 MHz ++ */ ++#define LTQ_CLK_CPU_393_DDR_197 0 ++#define LTQ_CLK_CPU_197_DDR_197 1 ++#define LTQ_CLK_CPU_333_DDR_167 2 ++#define LTQ_CLK_CPU_167_DDR_167 3 ++#define LTQ_CLK_CPU_131_DDR_131 4 ++#define LTQ_CLK_CPU_111_DDR_111 5 ++ ++/* CPU speed */ ++#define CONFIG_SYS_CLOCK_MODE LTQ_CLK_CPU_333_DDR_167 ++#define CONFIG_SYS_MIPS_TIMER_FREQ 166666667 ++#define CONFIG_SYS_HZ 1000 ++ ++/* RAM */ ++#define CONFIG_NR_DRAM_BANKS 1 ++#define CONFIG_SYS_SDRAM_BASE 0x80000000 ++#define CONFIG_SYS_SDRAM_BASE_UC 0xa0000000 ++#define CONFIG_SYS_MEMTEST_START 0x81000000 ++#define CONFIG_SYS_MEMTEST_END 0x82000000 ++#define CONFIG_SYS_LOAD_ADDR 0x81000000 ++#define CONFIG_SYS_INIT_SP_OFFSET (32 * 1024) ++ ++/* SRAM */ ++#define CONFIG_SYS_SRAM_BASE 0xBE1A0000 ++#define CONFIG_SYS_SRAM_SIZE 0x10000 ++ ++/* ASC/UART driver and console */ ++#define CONFIG_LANTIQ_SERIAL ++#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++/* GPIO */ ++#define CONFIG_LANTIQ_GPIO ++#define CONFIG_LTQ_GPIO_MAX_BANKS 3 ++#define CONFIG_LTQ_HAS_GPIO_BANK3 ++ ++/* FLASH driver */ ++#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) ++#define CONFIG_SYS_MAX_FLASH_BANKS 1 ++#define CONFIG_SYS_MAX_FLASH_SECT 256 ++#define CONFIG_SYS_FLASH_BASE 0xB0000000 ++#define CONFIG_FLASH_16BIT ++#define CONFIG_SYS_FLASH_CFI ++#define CONFIG_FLASH_CFI_DRIVER ++#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT ++#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE ++#define CONFIG_FLASH_SHOW_PROGRESS 50 ++#define CONFIG_SYS_FLASH_PROTECTION ++#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP ++ ++#define CONFIG_CMD_FLASH ++#else ++#define CONFIG_SYS_NO_FLASH ++#endif /* CONFIG_NOR_FLASH */ ++ ++#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH) ++#define CONFIG_LANTIQ_SPI ++#define CONFIG_SPI_FLASH ++ ++#define CONFIG_CMD_SF ++#define CONFIG_CMD_SPI ++#endif ++ ++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) ++#define CONFIG_NAND_LANTIQ ++#define CONFIG_SYS_MAX_NAND_DEVICE 1 ++#define CONFIG_SYS_NAND_BASE 0xB4000000 ++ ++#define CONFIG_CMD_NAND ++#endif ++ ++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) ++#define CONFIG_LANTIQ_DMA ++#define CONFIG_LANTIQ_ARX100_SWITCH ++ ++#define CONFIG_PHYLIB ++#define CONFIG_MII ++#define CONFIG_UDP_CHECKSUM ++ ++#define CONFIG_CMD_MII ++#define CONFIG_CMD_NET ++#endif ++ ++#define CONFIG_SPL_MAX_SIZE (32 * 1024) ++#define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024) ++#define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024) ++#define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024) ++#define CONFIG_SPL_STACK_BSS_IN_SRAM ++ ++#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM) ++#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SRAM_BASE + \ ++ CONFIG_SPL_MAX_SIZE + \ ++ CONFIG_SPL_STACK_MAX_SIZE - 1) ++#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1) ++#define CONFIG_SPL_MALLOC_BASE (CONFIG_SYS_SDRAM_BASE + \ ++ CONFIG_SYS_INIT_SP_OFFSET) ++#else ++#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SDRAM_BASE + \ ++ CONFIG_SYS_INIT_SP_OFFSET + \ ++ CONFIG_SPL_STACK_MAX_SIZE - 1) ++#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1) ++#define CONFIG_SPL_MALLOC_BASE (CONFIG_SPL_BSS_BASE + \ ++ CONFIG_SPL_BSS_MAX_SIZE) ++#endif ++ ++#if defined(CONFIG_SYS_BOOT_RAM) ++#define CONFIG_SYS_TEXT_BASE 0xA0100000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#endif ++ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_SYS_TEXT_BASE 0xB0000000 ++#endif ++ ++#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL) ++#define CONFIG_SYS_TEXT_BASE 0x80100000 ++#define CONFIG_SPL_TEXT_BASE 0xBE1A0000 ++#endif ++ ++#if defined(CONFIG_SYS_BOOT_NORSPL) ++#define CONFIG_SYS_TEXT_BASE 0x80100000 ++#define CONFIG_SPL_TEXT_BASE 0xB0000000 ++#endif ++ ++#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL) ++#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x688C688C ++#define CONFIG_XWAY_SWAP_BYTES ++#endif ++ ++#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE ++ ++#endif /* __ARX100_CONFIG_H__ */ +diff --git a/arch/mips/include/asm/arch-arx100/gpio.h b/arch/mips/include/asm/arch-arx100/gpio.h +new file mode 100644 +index 0000000..f6b6409 +--- /dev/null ++++ b/arch/mips/include/asm/arch-arx100/gpio.h +@@ -0,0 +1,12 @@ ++/* ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __ARX100_GPIO_H__ ++#define __ARX100_GPIO_H__ ++ ++#include <asm/lantiq/gpio.h> ++ ++#endif /* __ARX100_GPIO_H__ */ +diff --git a/arch/mips/include/asm/arch-arx100/nand.h b/arch/mips/include/asm/arch-arx100/nand.h +new file mode 100644 +index 0000000..231b68f +--- /dev/null ++++ b/arch/mips/include/asm/arch-arx100/nand.h +@@ -0,0 +1,13 @@ ++/* ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __VRX200_NAND_H__ ++#define __VRX200_NAND_H__ ++ ++struct nand_chip; ++int ltq_nand_init(struct nand_chip *nand); ++ ++#endif /* __VRX200_NAND_H__ */ +diff --git a/arch/mips/include/asm/arch-arx100/soc.h b/arch/mips/include/asm/arch-arx100/soc.h +new file mode 100644 +index 0000000..3ccaf3f +--- /dev/null ++++ b/arch/mips/include/asm/arch-arx100/soc.h +@@ -0,0 +1,37 @@ ++/* ++ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __ARX100_SOC_H__ ++#define __ARX100_SOC_H__ ++ ++#define LTQ_ASC0_BASE 0x1E100400 ++#define LTQ_SPI_BASE 0x1E100800 ++#define LTQ_GPIO_BASE 0x1E100B00 ++#define LTQ_SSIO_BASE 0x1E100BB0 ++#define LTQ_ASC1_BASE 0x1E100C00 ++#define LTQ_DMA_BASE 0x1E104100 ++ ++#define LTQ_EBU_BASE 0x1E105300 ++#define LTQ_EBU_REGION0_BASE 0x10000000 ++#define LTQ_EBU_REGION1_BASE 0x14000000 ++#define LTQ_EBU_NAND_BASE (LTQ_EBU_BASE + 0xB0) ++ ++#define LTQ_PPE_BASE 0x1E180000 ++#define LTQ_SWITCH_BASE 0x1E108000 ++ ++#define LTQ_PMU_BASE 0x1F102000 ++#define LTQ_CGU_BASE 0x1F103000 ++#define LTQ_MPS_BASE 0x1F107000 ++#define LTQ_CHIPID_BASE (LTQ_MPS_BASE + 0x340) ++#define LTQ_RCU_BASE 0x1F203000 ++ ++#define LTQ_MC_GEN_BASE 0x1F800000 ++#define LTQ_MC_SDR_BASE 0x1F800200 ++#define LTQ_MC_DDR_BASE 0x1F801000 ++#define LTQ_MC_DDR_DC_OFFSET(x) (x * 0x10) ++ ++#endif /* __ARX100_SOC_H__ */ +diff --git a/arch/mips/include/asm/lantiq/chipid.h b/arch/mips/include/asm/lantiq/chipid.h +index c9921b0..19adf97 100644 +--- a/arch/mips/include/asm/lantiq/chipid.h ++++ b/arch/mips/include/asm/lantiq/chipid.h +@@ -15,6 +15,10 @@ enum ltq_chip_partnum { + LTQ_SOC_DANUBE = 0x0129, + LTQ_SOC_DANUBE_S = 0x012B, + LTQ_SOC_TWINPASS = 0x012D, ++ LTQ_SOC_ARX188 = 0x016C, /* ARX188 */ ++ LTQ_SOC_ARX186 = 0x016D, /* ARX186 v1.1 */ ++ LTQ_SOC_ARX186_2 = 0x016E, /* ARX186 v1.2 */ ++ LTQ_SOC_ARX182 = 0x016F, /* ARX182 */ + LTQ_SOC_VRX288 = 0x01C0, /* VRX288 v1.1 */ + LTQ_SOC_VRX268 = 0x01C2, /* VRX268 v1.1 */ + LTQ_SOC_GRX288 = 0x01C9, /* GRX288 v1.1 */ +@@ -38,6 +42,38 @@ static inline int ltq_soc_is_danube(void) + } + #endif + ++#ifdef CONFIG_SOC_XWAY_ARX100 ++static inline int ltq_soc_is_arx100(void) ++{ ++ return 1; ++} ++ ++static inline int ltq_soc_is_arx100_v1(void) ++{ ++ return ltq_chip_version_get() == 1; ++} ++ ++static inline int ltq_soc_is_arx100_v2(void) ++{ ++ return ltq_chip_version_get() == 2; ++} ++#else ++static inline int ltq_soc_is_arx100(void) ++{ ++ return 0; ++} ++ ++static inline int ltq_soc_is_arx100_v1(void) ++{ ++ return 0; ++} ++ ++static inline int ltq_soc_is_arx100_v2(void) ++{ ++ return 0; ++} ++#endif ++ + #ifdef CONFIG_SOC_XWAY_VRX200 + static inline int ltq_soc_is_vrx200(void) + { +diff --git a/arch/mips/include/asm/lantiq/clk.h b/arch/mips/include/asm/lantiq/clk.h +index e13f000..5aea603 100644 +--- a/arch/mips/include/asm/lantiq/clk.h ++++ b/arch/mips/include/asm/lantiq/clk.h +@@ -13,9 +13,10 @@ enum ltq_clk { + CLOCK_83_MHZ = 83333333, + CLOCK_111_MHZ = 111111111, + CLOCK_125_MHZ = 125000000, ++ CLOCK_131_MHZ = 131073000, + CLOCK_133_MHZ = 133333333, + CLOCK_166_MHZ = 166666667, +- CLOCK_197_MHZ = 197000000, ++ CLOCK_197_MHZ = 196609500, + CLOCK_333_MHZ = 333333333, + CLOCK_393_MHZ = 393219000, + CLOCK_500_MHZ = 500000000, +diff --git a/arch/mips/include/asm/lantiq/cpu.h b/arch/mips/include/asm/lantiq/cpu.h +index b3a504e..e3b0312 100644 +--- a/arch/mips/include/asm/lantiq/cpu.h ++++ b/arch/mips/include/asm/lantiq/cpu.h +@@ -17,6 +17,7 @@ enum ltq_boot_select { + BOOT_PCI, + BOOT_MII0, + BOOT_RMII0, ++ BOOT_RGMII0, + BOOT_RGMII1, + BOOT_UNKNOWN, + }; +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0015-sf-macronix-add-support-for-MX66L51235L.patch b/package/boot/uboot-lantiq/patches/0015-sf-macronix-add-support-for-MX66L51235L.patch deleted file mode 100644 index fbc22e4..0000000 --- a/package/boot/uboot-lantiq/patches/0015-sf-macronix-add-support-for-MX66L51235L.patch +++ /dev/null @@ -1,21 +0,0 @@ -From a2d80b6b91ac63beea31455ce8d136230c030500 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Wed, 7 Nov 2012 15:14:40 +0100 -Subject: sf: macronix: add support for MX66L51235L - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/macronix.c -+++ b/drivers/mtd/spi/macronix.c -@@ -84,6 +84,11 @@ static const struct macronix_spi_flash_p - .nr_blocks = 512, - .name = "MX25L25635E", - }, -+ { -+ .idcode = 0x201A, -+ .nr_blocks = 1024, -+ .name = "MX66L51235L", -+ }, - }; - - static __maybe_unused int macronix_set_4byte_mode(struct spi_flash *flash) diff --git a/package/boot/uboot-lantiq/patches/0016-net-add-driver-for-Lantiq-XWAY-ARX100-switch.patch b/package/boot/uboot-lantiq/patches/0016-net-add-driver-for-Lantiq-XWAY-ARX100-switch.patch new file mode 100644 index 0000000..de1ecd2 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0016-net-add-driver-for-Lantiq-XWAY-ARX100-switch.patch @@ -0,0 +1,559 @@ +From 7288414298b34dcda1216fee1fe38d05ea0027a2 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 17 Dec 2012 23:32:39 +0100 +Subject: net: add driver for Lantiq XWAY ARX100 switch + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/arch/mips/include/asm/arch-arx100/config.h b/arch/mips/include/asm/arch-arx100/config.h +index 1a6c9bc..8f955e8 100644 +--- a/arch/mips/include/asm/arch-arx100/config.h ++++ b/arch/mips/include/asm/arch-arx100/config.h +@@ -10,17 +10,21 @@ + * and drivers for this SoC: + * + * CONFIG_LTQ_SUPPORT_UART +- * - support the Danube ASC/UART interface and console ++ * - support the ARX100 ASC/UART interface and console + * + * CONFIG_LTQ_SUPPORT_NOR_FLASH + * - support a parallel NOR flash via the CFI interface in flash bank 0 + * + * CONFIG_LTQ_SUPPORT_ETHERNET +- * - support the Danube ETOP and MAC interface ++ * - support the ARX100 ETOP and MAC interface + * + * CONFIG_LTQ_SUPPORT_SPI_FLASH +- * - support the Danube SPI interface and serial flash drivers ++ * - support the ARX100 SPI interface and serial flash drivers + * - specific SPI flash drivers must be configured separately ++ * ++ * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH ++ * - build a preloader that runs in the internal SRAM and loads ++ * the U-Boot from SPI flash into RAM + */ + + #ifndef __ARX100_CONFIG_H__ +diff --git a/arch/mips/include/asm/arch-arx100/switch.h b/arch/mips/include/asm/arch-arx100/switch.h +new file mode 100644 +index 0000000..301056c +--- /dev/null ++++ b/arch/mips/include/asm/arch-arx100/switch.h +@@ -0,0 +1,86 @@ ++/* ++ * Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __ARX100_SWITCH_H__ ++#define __ARX100_SWITCH_H__ ++ ++struct ar9_switch_regs { ++ __be32 ps; /* Port status*/ ++ __be32 p0_ctl; /* Port 0 control */ ++ __be32 p1_ctl; /* Port 1 control */ ++ __be32 p2_ctl; /* Port 2 control */ ++ __be32 p0_vlan; /* Port 0 VLAN control */ ++ __be32 p1_vlan; /* Port 1 VLAN control */ ++ __be32 p2_vlan; /* Port 2 VLAN control */ ++ __be32 p0_inctl; /* Port 0 ingress control */ ++ __be32 p1_inctl; /* Port 1 ingress control */ ++ __be32 p2_inctl; /* Port 2 ingress control */ ++ u32 rsvd0[16]; ++ __be32 sw_gctl0; /* Switch global control 0 */ ++ __be32 sw_gctl1; /* Switch global control 1 */ ++ __be32 arp; /* ARP/RARP */ ++ __be32 strm_ctl; /* Storm control */ ++ __be32 rgmii_ctl; /* RGMII/GMII port control */ ++ u32 rsvd1[4]; ++ __be32 pmac_hd_ctl; /* PMAC header control */ ++ u32 rsvd2[15]; ++ __be32 mdio_ctrl; /* MDIO indirect access control */ ++ __be32 mdio_data; /* MDIO indirect read data */ ++}; ++ ++#define BUILD_CHECK_AR9_REG(name, offset) \ ++ BUILD_BUG_ON(offsetof(struct ar9_switch_regs, name) != (offset)) ++ ++static inline void build_check_ar9_registers(void) ++{ ++ BUILD_CHECK_AR9_REG(sw_gctl0, 0x68); ++ BUILD_CHECK_AR9_REG(rgmii_ctl, 0x78); ++ BUILD_CHECK_AR9_REG(pmac_hd_ctl, 0x8c); ++ BUILD_CHECK_AR9_REG(mdio_ctrl, 0xcc); ++ BUILD_CHECK_AR9_REG(mdio_data, 0xd0); ++} ++ ++#define P0_CTL_FLP (1 << 18) ++#define P0_CTL_FLD (1 << 17) ++ ++#define SW_GCTL0_SE (1 << 31) ++ ++#define RGMII_CTL_P1_SHIFT 10 ++#define RGMII_CTL_P1_MASK (0x3FF << RGMII_CTL_P1_SHIFT) ++#define RGMII_CTL_P0_MASK 0x3FF ++#define RGMII_CTL_P0IS_SHIFT 8 ++#define RGMII_CTL_P0IS_RGMII (0x0 << RGMII_CTL_P0IS_SHIFT) ++#define RGMII_CTL_P0IS_MII (0x1 << RGMII_CTL_P0IS_SHIFT) ++#define RGMII_CTL_P0IS_REVMII (0x2 << RGMII_CTL_P0IS_SHIFT) ++#define RGMII_CTL_P0IS_RMII (0x3 << RGMII_CTL_P0IS_SHIFT) ++#define RGMII_CTL_P0RDLY_SHIFT 6 ++#define RGMII_CTL_P0RDLY_0_0 (0x0 << RGMII_CTL_P0RDLY_SHIFT) ++#define RGMII_CTL_P0RDLY_1_5 (0x1 << RGMII_CTL_P0RDLY_SHIFT) ++#define RGMII_CTL_P0RDLY_1_75 (0x2 << RGMII_CTL_P0RDLY_SHIFT) ++#define RGMII_CTL_P0RDLY_2_0 (0x3 << RGMII_CTL_P0RDLY_SHIFT) ++#define RGMII_CTL_P0TDLY_SHIFT 4 ++#define RGMII_CTL_P0TDLY_0_0 (0x0 << RGMII_CTL_P0TDLY_SHIFT) ++#define RGMII_CTL_P0TDLY_1_5 (0x1 << RGMII_CTL_P0TDLY_SHIFT) ++#define RGMII_CTL_P0TDLY_1_75 (0x2 << RGMII_CTL_P0TDLY_SHIFT) ++#define RGMII_CTL_P0TDLY_2_0 (0x3 << RGMII_CTL_P0TDLY_SHIFT) ++#define RGMII_CTL_P0SPD_SHIFT 2 ++#define RGMII_CTL_P0SPD_10 (0x0 << RGMII_CTL_P0SPD_SHIFT) ++#define RGMII_CTL_P0SPD_100 (0x1 << RGMII_CTL_P0SPD_SHIFT) ++#define RGMII_CTL_P0SPD_1000 (0x2 << RGMII_CTL_P0SPD_SHIFT) ++#define RGMII_CTL_P0DUP_FULL (1 << 1) ++#define RGMII_CTL_P0FCE_EN (1 << 0) ++ ++#define PMAC_HD_CTL_AC (1 << 18) ++ ++#define MDIO_CTRL_WD_SHIFT 16 ++#define MDIO_CTRL_MBUSY (1 << 15) ++#define MDIO_CTRL_OP_READ (1 << 11) ++#define MDIO_CTRL_OP_WRITE (1 << 10) ++#define MDIO_CTRL_PHYAD_SHIFT 5 ++#define MDIO_CTRL_PHYAD_MASK (0x1f << MDIO_CTRL_PHYAD_SHIFT) ++#define MDIO_CTRL_REGAD_MASK 0x1f ++ ++#endif /* __ARX100_SWITCH_H__ */ +diff --git a/drivers/net/Makefile b/drivers/net/Makefile +index bbc2c92..926b8c2 100644 +--- a/drivers/net/Makefile ++++ b/drivers/net/Makefile +@@ -38,6 +38,7 @@ COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o + COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o + COBJS-$(CONFIG_LAN91C96) += lan91c96.o + COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o ++COBJS-$(CONFIG_LANTIQ_ARX100_SWITCH) += lantiq_arx100_switch.o + COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o + COBJS-$(CONFIG_MACB) += macb.o + COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o +diff --git a/drivers/net/lantiq_arx100_switch.c b/drivers/net/lantiq_arx100_switch.c +new file mode 100644 +index 0000000..cc65249 +--- /dev/null ++++ b/drivers/net/lantiq_arx100_switch.c +@@ -0,0 +1,410 @@ ++/* ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++#define DEBUG ++#include <common.h> ++#include <malloc.h> ++#include <netdev.h> ++#include <miiphy.h> ++#include <switch.h> ++#include <linux/compiler.h> ++#include <asm/gpio.h> ++#include <asm/processor.h> ++#include <asm/lantiq/io.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/pm.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/dma.h> ++#include <asm/arch/soc.h> ++#include <asm/arch/switch.h> ++ ++#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX ++#define LTQ_ETH_TX_BUFFER_CNT 8 ++#define LTQ_ETH_RX_DATA_SIZE PKTSIZE_ALIGN ++#define LTQ_ETH_IP_ALIGN 2 ++ ++#define LTQ_MDIO_DRV_NAME "ltq-mdio" ++#define LTQ_ETH_DRV_NAME "ltq-eth" ++ ++#define LTQ_ETHSW_MAX_GMAC 2 ++#define LTQ_ETHSW_PMAC 2 ++ ++struct ltq_eth_priv { ++ struct ltq_dma_device dma_dev; ++ struct mii_dev *bus; ++ struct eth_device *dev; ++ struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC]; ++ int rx_num; ++ int tx_num; ++}; ++ ++static struct ar9_switch_regs *switch_regs = ++ (struct ar9_switch_regs *) CKSEG1ADDR(LTQ_SWITCH_BASE); ++ ++static int ltq_mdio_is_busy(void) ++{ ++ u32 mdio_ctrl = ltq_readl(&switch_regs->mdio_ctrl); ++ ++ return mdio_ctrl & MDIO_CTRL_MBUSY; ++} ++ ++static void ltq_mdio_poll(void) ++{ ++ while (ltq_mdio_is_busy()) ++ cpu_relax(); ++ ++ __udelay(1000); ++} ++ ++static int ltq_mdio_read(struct mii_dev *bus, int phyad, int devad, ++ int regad) ++{ ++ u32 mdio_ctrl; ++ int retval; ++ ++ mdio_ctrl = MDIO_CTRL_MBUSY | MDIO_CTRL_OP_READ | ++ ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) | ++ (regad & MDIO_CTRL_REGAD_MASK); ++ ++ ltq_mdio_poll(); ++ ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl); ++ ltq_mdio_poll(); ++ retval = ltq_readl(&switch_regs->mdio_data); ++ ltq_writel(&switch_regs->mdio_data, 0xFFFF); ++ ++ debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, retval); ++ ++ return retval; ++} ++ ++static int ltq_mdio_write(struct mii_dev *bus, int phyad, int devad, ++ int regad, u16 val) ++{ ++ u32 mdio_ctrl; ++ ++ debug("%s: phyad %02x, regad %02x, val %02x\n", __func__, phyad, regad, val); ++ ++ mdio_ctrl = (val << MDIO_CTRL_WD_SHIFT) | MDIO_CTRL_MBUSY | ++ MDIO_CTRL_OP_WRITE | ++ ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) | ++ (regad & MDIO_CTRL_REGAD_MASK); ++ ++ ltq_mdio_poll(); ++ ltq_writel(&switch_regs->mdio_ctrl, mdio_ctrl); ++ ++ return 0; ++} ++ ++static void ltq_eth_gmac_update(struct phy_device *phydev, int num) ++{ ++} ++ ++static inline u8 *ltq_eth_rx_packet_align(int rx_num) ++{ ++ u8 *packet = (u8 *) NetRxPackets[rx_num]; ++ ++ /* ++ * IP header needs ++ */ ++ return packet + LTQ_ETH_IP_ALIGN; ++} ++ ++static int ltq_eth_init(struct eth_device *dev, bd_t *bis) ++{ ++ struct ltq_eth_priv *priv = dev->priv; ++ struct ltq_dma_device *dma_dev = &priv->dma_dev; ++ struct phy_device *phydev; ++ int i; ++ ++ for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) { ++ phydev = priv->phymap[i]; ++ if (!phydev) ++ continue; ++ ++ phy_startup(phydev); ++ ltq_eth_gmac_update(phydev, i); ++ } ++ ++ for (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++) ++ ltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i), ++ LTQ_ETH_RX_DATA_SIZE); ++ ++ ltq_dma_enable(dma_dev); ++ ++ priv->rx_num = 0; ++ priv->tx_num = 0; ++ ++ return 0; ++} ++ ++static void ltq_eth_halt(struct eth_device *dev) ++{ ++ struct ltq_eth_priv *priv = dev->priv; ++ struct ltq_dma_device *dma_dev = &priv->dma_dev; ++ struct phy_device *phydev; ++ int i; ++ ++ ltq_dma_reset(dma_dev); ++ ++ for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) { ++ phydev = priv->phymap[i]; ++ if (!phydev) ++ continue; ++ ++ phy_shutdown(phydev); ++ phydev->link = 0; ++ ltq_eth_gmac_update(phydev, i); ++ } ++} ++ ++static int ltq_eth_send(struct eth_device *dev, void *packet, int length) ++{ ++ struct ltq_eth_priv *priv = dev->priv; ++ struct ltq_dma_device *dma_dev = &priv->dma_dev; ++ int err; ++ ++ err = ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10); ++ if (err) { ++ puts("NET: timeout on waiting for TX descriptor\n"); ++ return -1; ++ } ++ ++ priv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT; ++ ++ return err; ++} ++ ++static int ltq_eth_recv(struct eth_device *dev) ++{ ++ struct ltq_eth_priv *priv = dev->priv; ++ struct ltq_dma_device *dma_dev = &priv->dma_dev; ++ u8 *packet; ++ int len; ++ ++ if (!ltq_dma_rx_poll(dma_dev, priv->rx_num)) ++ return 0; ++ ++#if 0 ++ printf("%s: rx_num %d\n", __func__, priv->rx_num); ++#endif ++ ++ len = ltq_dma_rx_length(dma_dev, priv->rx_num); ++ packet = ltq_eth_rx_packet_align(priv->rx_num); ++ ++#if 0 ++ printf("%s: received: packet %p, len %u, rx_num %d\n", ++ __func__, packet, len, priv->rx_num); ++#endif ++ ++ if (len) ++ NetReceive(packet, len); ++ ++ ltq_dma_rx_map(dma_dev, priv->rx_num, packet, ++ LTQ_ETH_RX_DATA_SIZE); ++ ++ priv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT; ++ ++ return 0; ++} ++ ++static void ltq_eth_pmac_init(void) ++{ ++ /* Add CRC to packets from DMA to PMAC */ ++ ltq_setbits(&switch_regs->pmac_hd_ctl, PMAC_HD_CTL_AC); ++ ++ /* Force link up */ ++ ltq_setbits(&switch_regs->p2_ctl, P0_CTL_FLP); ++} ++ ++static void ltq_eth_hw_init(const struct ltq_eth_port_config *port) ++{ ++ /* Power up ethernet subsystems */ ++ ltq_pm_enable(LTQ_PM_ETH); ++ ++ /* Enable switch core */ ++ ltq_setbits(&switch_regs->sw_gctl0, SW_GCTL0_SE); ++ ++ /* MII/MDIO */ ++ gpio_set_altfunc(42, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* MII/MDC */ ++ gpio_set_altfunc(43, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ ++ ltq_eth_pmac_init(); ++} ++ ++static void ltq_eth_port_config(struct ltq_eth_priv *priv, ++ const struct ltq_eth_port_config *port) ++{ ++ struct phy_device *phydev; ++ struct switch_device *sw; ++ u32 rgmii_ctl; ++ unsigned int port_ctl, port_xmii = 0; ++ ++ if (port->num > 1) ++ return; ++ ++ rgmii_ctl = ltq_readl(&switch_regs->rgmii_ctl); ++ ++ if (port->num == 1) ++ port_ctl = ltq_readl(&switch_regs->p1_ctl); ++ else ++ port_ctl = ltq_readl(&switch_regs->p0_ctl); ++ ++ switch (port->phy_if) { ++ case PHY_INTERFACE_MODE_RGMII: ++ port_xmii = RGMII_CTL_P0IS_RGMII; ++ ++ switch (port->rgmii_tx_delay) { ++ case 1: ++ port_xmii |= RGMII_CTL_P0TDLY_1_5; ++ break; ++ case 2: ++ port_xmii |= RGMII_CTL_P0TDLY_1_75; ++ break; ++ case 3: ++ port_xmii |= RGMII_CTL_P0TDLY_2_0; ++ break; ++ default: ++ break; ++ } ++ ++ switch (port->rgmii_rx_delay) { ++ case 1: ++ port_xmii |= RGMII_CTL_P0RDLY_1_5; ++ break; ++ case 2: ++ port_xmii |= RGMII_CTL_P0RDLY_1_75; ++ break; ++ case 3: ++ port_xmii |= RGMII_CTL_P0RDLY_2_0; ++ break; ++ default: ++ break; ++ } ++ ++ if (!(port->flags & LTQ_ETH_PORT_PHY)) { ++ port_xmii |= (RGMII_CTL_P0SPD_1000 | ++ RGMII_CTL_P0DUP_FULL); ++ port_ctl |= P0_CTL_FLP; ++ } ++ ++ break; ++ case PHY_INTERFACE_MODE_MII: ++ port_xmii = RGMII_CTL_P0IS_MII; ++ ++ if (!(port->flags & LTQ_ETH_PORT_PHY)) { ++ port_xmii |= (RGMII_CTL_P0SPD_100 | ++ RGMII_CTL_P0DUP_FULL); ++ port_ctl |= P0_CTL_FLP; ++ } ++ ++ break; ++ default: ++ break; ++ } ++ ++ if (port->num == 1) { ++ ltq_writel(&switch_regs->p1_ctl, port_ctl); ++ ++ rgmii_ctl &= ~RGMII_CTL_P1_MASK; ++ rgmii_ctl |= (port_xmii << RGMII_CTL_P1_SHIFT); ++ } else { ++ ltq_writel(&switch_regs->p0_ctl, port_ctl); ++ ++ rgmii_ctl &= ~RGMII_CTL_P0_MASK; ++ rgmii_ctl |= port_xmii; ++ } ++ ++ ltq_writel(&switch_regs->rgmii_ctl, rgmii_ctl); ++ ++ /* Connect to external switch */ ++ if (port->flags & LTQ_ETH_PORT_SWITCH) { ++ sw = switch_connect(priv->bus); ++ if (sw) ++ switch_setup(sw); ++ } ++ ++ /* Connect to internal/external PHYs */ ++ if (port->flags & LTQ_ETH_PORT_PHY) { ++ phydev = phy_connect(priv->bus, port->phy_addr, priv->dev, ++ port->phy_if); ++ if (phydev) ++ phy_config(phydev); ++ ++ priv->phymap[port->num] = phydev; ++ } ++} ++ ++int ltq_eth_initialize(const struct ltq_eth_board_config *board_config) ++{ ++ struct eth_device *dev; ++ struct mii_dev *bus; ++ struct ltq_eth_priv *priv; ++ struct ltq_dma_device *dma_dev; ++ const struct ltq_eth_port_config *port = &board_config->ports[0]; ++ int i, ret; ++ ++ build_check_ar9_registers(); ++ ++ ltq_dma_init(); ++ ltq_eth_hw_init(port); ++ ++ dev = calloc(1, sizeof(*dev)); ++ if (!dev) ++ return -1; ++ ++ priv = calloc(1, sizeof(*priv)); ++ if (!priv) ++ return -1; ++ ++ bus = mdio_alloc(); ++ if (!bus) ++ return -1; ++ ++ sprintf(dev->name, LTQ_ETH_DRV_NAME); ++ dev->priv = priv; ++ dev->init = ltq_eth_init; ++ dev->halt = ltq_eth_halt; ++ dev->recv = ltq_eth_recv; ++ dev->send = ltq_eth_send; ++ ++ sprintf(bus->name, LTQ_MDIO_DRV_NAME); ++ bus->read = ltq_mdio_read; ++ bus->write = ltq_mdio_write; ++ bus->priv = priv; ++ ++ dma_dev = &priv->dma_dev; ++ dma_dev->port = 0; ++ dma_dev->rx_chan.chan_no = 0; ++ dma_dev->rx_chan.class = 0; ++ dma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT; ++ dma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0; ++ dma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS; ++ dma_dev->tx_chan.chan_no = 1; ++ dma_dev->tx_chan.class = 0; ++ dma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT; ++ dma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0; ++ dma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS; ++ ++ priv->bus = bus; ++ priv->dev = dev; ++ ++ ret = ltq_dma_register(dma_dev); ++ if (ret) ++ return ret; ++ ++ ret = mdio_register(bus); ++ if (ret) ++ return ret; ++ ++ ret = eth_register(dev); ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < board_config->num_ports; i++) ++ ltq_eth_port_config(priv, &board_config->ports[i]); ++ ++ return 0; ++} +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0016-sf-add-MTD-layer-driver-for-SPI-flash-devices.patch b/package/boot/uboot-lantiq/patches/0016-sf-add-MTD-layer-driver-for-SPI-flash-devices.patch deleted file mode 100644 index a9ee560..0000000 --- a/package/boot/uboot-lantiq/patches/0016-sf-add-MTD-layer-driver-for-SPI-flash-devices.patch +++ /dev/null @@ -1,133 +0,0 @@ -From 7f6ded11965b09daf6da44d4fa98da17b9fba36c Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Tue, 6 Nov 2012 19:41:26 +0100 -Subject: sf: add MTD layer driver for SPI flash devices - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/Makefile -+++ b/drivers/mtd/spi/Makefile -@@ -30,6 +30,7 @@ COBJS-$(CONFIG_SPL_SPI_LOAD) += spi_spl_ - endif - - COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o -+COBJS-$(CONFIG_SPI_FLASH_MTD) += spi_flash_mtd.o - COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o - COBJS-$(CONFIG_SPI_FLASH_EON) += eon.o - COBJS-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.o ---- a/drivers/mtd/spi/spi_flash_internal.h -+++ b/drivers/mtd/spi/spi_flash_internal.h -@@ -122,6 +122,9 @@ static inline int spi_flash_set_4byte_mo - } - #endif - -+/* SPI flash MTD adapter init */ -+int spi_flash_mtd_init(struct spi_flash *flash); -+ - /* Manufacturer-specific probe functions */ - int spi_flash_probe_spansion(struct spi_flash *flash, u8 *idcode); - int spi_flash_probe_atmel(struct spi_flash *flash, u8 *idcode); ---- /dev/null -+++ b/drivers/mtd/spi/spi_flash_mtd.c -@@ -0,0 +1,101 @@ -+/* -+ * (C) Copyright 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com -+ * -+ * MTD layer driver for SPI flash devices -+ * -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ */ -+ -+#include <common.h> -+#include <malloc.h> -+#include <asm/errno.h> -+#include <linux/mtd/mtd.h> -+#include <spi_flash.h> -+ -+static struct mtd_info sf_mtd_info; -+static char sf_mtd_name[8]; -+ -+static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) -+{ -+ struct spi_flash *flash = mtd->priv; -+ int err; -+ -+ instr->state = MTD_ERASING; -+ -+ err = spi_flash_erase(flash, instr->addr, instr->len); -+ if (err) { -+ instr->state = MTD_ERASE_FAILED; -+ instr->fail_addr = MTD_FAIL_ADDR_UNKNOWN; -+ return -EIO; -+ } -+ -+ instr->state = MTD_ERASE_DONE; -+ mtd_erase_callback(instr); -+ -+ return 0; -+} -+ -+static int spi_flash_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, -+ size_t *retlen, u_char *buf) -+{ -+ struct spi_flash *flash = mtd->priv; -+ int err; -+ -+ err = spi_flash_read(flash, from, len, buf); -+ if (!err) -+ *retlen = len; -+ -+ return err; -+} -+ -+static int spi_flash_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, -+ size_t *retlen, const u_char *buf) -+{ -+ struct spi_flash *flash = mtd->priv; -+ int err; -+ -+ err = spi_flash_write(flash, to, len, buf); -+ if (!err) -+ *retlen = len; -+ -+ return err; -+} -+ -+static void spi_flash_mtd_sync(struct mtd_info *mtd) -+{ -+} -+ -+static int spi_flash_mtd_number(void) -+{ -+#ifdef CONFIG_SYS_MAX_FLASH_BANKS -+ return CONFIG_SYS_MAX_FLASH_BANKS; -+#else -+ return 0; -+#endif -+} -+ -+int spi_flash_mtd_init(struct spi_flash *flash) -+{ -+ memset(&sf_mtd_info, 0, sizeof(sf_mtd_info)); -+ sprintf(sf_mtd_name, "nor%d", spi_flash_mtd_number()); -+ -+ sf_mtd_info.name = sf_mtd_name; -+ sf_mtd_info.type = MTD_NORFLASH; -+ sf_mtd_info.flags = MTD_CAP_NORFLASH; -+ sf_mtd_info.writesize = 1; -+ -+ sf_mtd_info.erase = spi_flash_mtd_erase; -+ sf_mtd_info.read = spi_flash_mtd_read; -+ sf_mtd_info.write = spi_flash_mtd_write; -+ sf_mtd_info.sync = spi_flash_mtd_sync; -+ -+ sf_mtd_info.size = flash->size; -+ sf_mtd_info.priv = flash; -+ -+ /* Only uniform flash devices for now */ -+ sf_mtd_info.numeraseregions = 0; -+ sf_mtd_info.erasesize = flash->sector_size; -+ -+ return add_mtd_device(&sf_mtd_info); -+} diff --git a/package/boot/uboot-lantiq/patches/0017-sf-add-init-function.patch b/package/boot/uboot-lantiq/patches/0017-sf-add-init-function.patch deleted file mode 100644 index 2d29051..0000000 --- a/package/boot/uboot-lantiq/patches/0017-sf-add-init-function.patch +++ /dev/null @@ -1,57 +0,0 @@ -From aa9d5d64ca6441cb24e22dc3c1f707da62da2887 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Tue, 6 Nov 2012 19:35:17 +0100 -Subject: sf: add init function - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/drivers/mtd/spi/spi_flash.c -+++ b/drivers/mtd/spi/spi_flash.c -@@ -482,3 +482,36 @@ void spi_flash_free(struct spi_flash *fl - spi_flash_free_spl(flash); - free(flash); - } -+ -+#ifdef CONFIG_SPI_FLASH_MTD -+static int spi_flash_mtd_register(void) -+{ -+ struct spi_flash *flash; -+ int err; -+ -+ flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, -+ CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); -+ if (!flash) -+ return -1; -+ -+ err = spi_flash_mtd_init(flash); -+ if (err) -+ spi_flash_free(flash); -+ -+ return err; -+} -+#else -+static int spi_flash_mtd_register(void) -+{ -+ return 0; -+} -+#endif -+ -+int spi_flash_init(void) -+{ -+ int err; -+ -+ err = spi_flash_mtd_register(); -+ -+ return err; -+} ---- a/include/spi_flash.h -+++ b/include/spi_flash.h -@@ -51,6 +51,8 @@ struct spi_flash { - #endif - }; - -+int spi_flash_init(void); -+ - struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode); - void spi_flash_free(struct spi_flash *flash); diff --git a/package/boot/uboot-lantiq/patches/0029-tools-add-some-helper-tools-for-Lantiq-SoCs.patch b/package/boot/uboot-lantiq/patches/0017-tools-add-some-helper-tools-for-Lantiq-SoCs.patch index 77d48d1..08347bb 100644 --- a/package/boot/uboot-lantiq/patches/0029-tools-add-some-helper-tools-for-Lantiq-SoCs.patch +++ b/package/boot/uboot-lantiq/patches/0017-tools-add-some-helper-tools-for-Lantiq-SoCs.patch @@ -1,11 +1,14 @@ -From 1b77d4249b5addbf3b0848db6992a445019a1865 Mon Sep 17 00:00:00 2001 +From 1da5479d59b39d7931a2b0efabdfa314f6788b6d Mon Sep 17 00:00:00 2001 From: Luka Perkov <luka@openwrt.org> -Date: Wed, 29 Aug 2012 22:08:42 +0200 +Date: Sat, 2 Mar 2013 23:34:00 +0100 Subject: tools: add some helper tools for Lantiq SoCs Signed-off-by: Luka Perkov Luka Perkov <luka@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/tools/gct.pl b/tools/gct.pl +new file mode 100755 +index 0000000..33fa6f7 --- /dev/null +++ b/tools/gct.pl @@ -0,0 +1,155 @@ @@ -164,44 +167,150 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + $holder=""; + } +} +diff --git a/tools/lantiq_bdi_conf.awk b/tools/lantiq_bdi_conf.awk +new file mode 100755 +index 0000000..c732289 --- /dev/null -+++ b/tools/lantiq_extract_openwrt_patches.sh -@@ -0,0 +1,15 @@ -+#!/bin/bash ++++ b/tools/lantiq_bdi_conf.awk +@@ -0,0 +1,116 @@ ++#!/usr/bin/awk -f ++# ++# Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++# Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++# ++# Usage: ++# awk -f lantiq_bdi_conf.awk -v soc=ar9 board=<name> PATH_TO_BOARD/ddr_settings.h ++# ++# Additional information: ++# http://www.abatron.ch/fileadmin/user_upload/products/pdf/ManGDBR4K-3000.pdf ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++function print_header() ++{ ++ print "; " ++ print "; Copyright (C) 2013 Luka Perkov <luka@openwrt.org> " ++ print "; Copyright (C) 2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> " ++ print "; " ++ print "; This file has been generated with lantiq_bdi_conf.awk script. " ++ print "; " ++ print "; SPDX-License-Identifier: GPL-2.0+ " ++ print "; " ++ print "" ++} ++ ++function init_ar9_prologue() ++{ ++ print "WM32 0xBF103010 0x80 ; CGU for CPU 333Mhz, DDR 167Mhz" ++ print "WM32 0xBF103014 0x01 ; CGU update" ++ print "WM32 0xBF800010 0x0 ; Clear error access log register" ++ print "WM32 0xBF800020 0x0 ; Clear error access log register" ++ print "WM32 0xBF800060 0xD ; Enable FPI, DDR and SRAM module in memory controller" ++ print "WM32 0xBF801030 0x0 ; Clear start bit of DDR memory controller" ++} ++ ++function init_ar9_epilogue() ++{ ++ print "WM32 0xBE105360 0x4001D7FF ; EBU setup" ++} + -+set -e -+set -x ++function init_ddr1_epilogue() ++{ ++ print "WM32 0xBF801030 0x100 ; Set start bit of DDR memory controller" ++} ++ ++function ar9_target() ++{ ++ print "CPUTYPE M34K" ++ print "ENDIAN BIG" ++ print "JTAGCLOCK 1" ++ print "BDIMODE AGENT ; [ LOADONLY, AGENT ]" ++ print "RESET JTAG ; [ NONE, JTAG, HARD ]" ++ print "POWERUP 100" ++ print "WAKEUP 100" ++ print "BREAKMODE HARD ; [ SOFT, HARD ]" ++ print "STEPMODE SWBP ; [ JTAG, HWBP, SWBP ]" ++ print "VECTOR CATCH" ++ print "SCANSUCC 1 5" ++} ++ ++function flash_p2601hnfx() ++{ ++ print "CHIPTYPE MIRRORX16" ++ print "CHIPSIZE 0x1000000" ++ print "BUSWIDTH 16" ++} ++ ++BEGIN { ++ switch (soc) { ++ case "ar9": ++ reg_base = 0xbf801000 ++ print_header() ++ print "[INIT]" ++ init_ar9_prologue() ++ break ++ default: ++ print "Invalid or no value for SoC specified!" ++ exit 1 ++ } ++} + -+test $# -eq 1 ++/^#define/ { ++ /* DC03 contains MC enable bit and must not be set here */ ++ if (tolower($2) != "mc_dc03_value") ++ printf("WM32 0x%x %s\n", reg_base, tolower($3)) + -+openwrt_root=$(readlink -f $1) -+test -d $openwrt_root ++ reg_base += 0x10 ++} + -+uboot_lantiq_dir=$openwrt_root/package/boot/uboot-lantiq/patches -+test -d $uboot_lantiq_dir ++END { ++ switch (soc) { ++ case "ar9": ++ init_ddr1_epilogue() ++ init_ar9_epilogue() ++ print "" ++ print "[TARGET]" ++ ar9_target() ++ print "" ++ print "[HOST]" ++ print "PROMPT \"ar9> \"" ++ print "" ++ break ++ default: ++ } + -+rm -vf $uboot_lantiq_dir/* -+git format-patch -k -p --no-renames --text --full-index -o $uboot_lantiq_dir v2012.10..openwrt/v2013.01 ++ switch (board) { ++ case "p2601hnfx": ++ print "[FLASH]" ++ flash_p2601hnfx() ++ print "" ++ break ++ default: ++ } ++} +diff --git a/tools/lantiq_ram_extract_magic.awk b/tools/lantiq_ram_extract_magic.awk +new file mode 100755 +index 0000000..64f1cbc --- /dev/null +++ b/tools/lantiq_ram_extract_magic.awk -@@ -0,0 +1,70 @@ +@@ -0,0 +1,69 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> +# -+# Copyright (C) 2011 Luka Perkov <luka@openwrt.org> ++# Usage: ++# mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk +# -+# usage: mips-openwrt-linux-objdump -EB -b binary -m mips:isa32r2 -D YOUR_IMAGE_DUMP | awk -f lantiq_ram_extract_magic.awk ++# SPDX-License-Identifier: GPL-2.0+ +# + +BEGIN { + print "/* " -+ print " * This file is released under the terms of GPL v2 and any later version. " -+ print " * See the file COPYING in the root directory of the source tree for details. " ++ print " * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> " + print " * " -+ print " * generated with lantiq_ram_extract_magic.awk " ++ print " * This file has been generated with lantiq_ram_extract_magic.awk script. " + print " * " -+ print " * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> " ++ print " * SPDX-License-Identifier: GPL-2.0+ " + print " */ " + print "" + @@ -255,35 +364,36 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + if ($4 == "t2,736(t1)") + right_section=0 +} +diff --git a/tools/lantiq_ram_init_uart.awk b/tools/lantiq_ram_init_uart.awk +new file mode 100755 +index 0000000..dc82645 --- /dev/null +++ b/tools/lantiq_ram_init_uart.awk -@@ -0,0 +1,101 @@ +@@ -0,0 +1,117 @@ +#!/usr/bin/awk -f +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. -+# +# Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org> +# Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +# -+# usage: awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h ++# Usage: ++# awk -f lantiq_ram_init_uart.awk -v soc=<danube|ar9|vr9> PATH_TO_BOARD/ddr_settings.h ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +function print_header() +{ + print "; " -+ print "; This file is released under the terms of GPL v2 and any later version. " -+ print "; See the file COPYING in the root directory of the source tree for details. " ++ print "; Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> " ++ print "; Copyright (C) 2012-2013 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> " + print "; " -+ print "; generated with lantiq_ram_init_uart.awk " -+ print "; " -+ print "; Copyright (C) 2011-2012 Luka Perkov <luka@openwrt.org> " -+ print "; Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@gmail.com> " ++ print "; This file has been generated with lantiq_ram_init_uart.awk script. " + print "; " ++ print "; SPDX-License-Identifier: GPL-2.0+ " + print "" +} + -+function mc_ddr1_prologue() ++function mc_danube_prologue() +{ + /* Clear access error log registers */ + print "0xbf800010", "0x0" @@ -296,6 +406,19 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + print "0xbf801030", "0x0" +} + ++function mc_ar9_prologue() ++{ ++ /* Clear access error log registers */ ++ print "0xbf800010", "0x0" ++ print "0xbf800020", "0x0" ++ ++ /* Enable FPI, DDR and SRAM module in memory controller */ ++ print "0xbf800060", "0xD" ++ ++ /* Clear start bit of DDR memory controller */ ++ print "0xbf801030", "0x0" ++} ++ +function mc_ddr1_epilogue() +{ + /* Set start bit of DDR memory controller */ @@ -318,10 +441,14 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +BEGIN { + switch (soc) { + case "danube": ++ reg_base = 0xbf801000 ++ print_header() ++ mc_danube_prologue() ++ break + case "ar9": + reg_base = 0xbf801000 + print_header() -+ mc_ddr1_prologue() ++ mc_ar9_prologue() + break + case "vr9": + reg_base = 0xbf401000 @@ -337,14 +464,15 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +} + +/^#define/ { -+ printf("0x%x %s\n", reg_base, tolower($3)) -+ reg_base += 0x10 -+} ++ /* CCR07 contains MC enable bit and must not be set here */ ++ if (tolower($2) == "mc_ccr07_value") ++ mc_ccr07_value = strtonum($3) ++ if (tolower($2) == "mc_dc03_value") ++ /* CCR07 contains MC enable bit and must not be set here */ ++ else ++ printf("0x%x %s\n", reg_base, tolower($3)) + -+/^#define(.*)MC_CCR07_VALUE/ { -+ printf("0x%x %s\n", reg_base, tolower($3)) + reg_base += 0x10 -+ mc_ccr07_value = strtonum($3) +} + +END { @@ -359,3 +487,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + default: + } +} +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0018-MIPS-add-SPI-flash-init-hook.patch b/package/boot/uboot-lantiq/patches/0018-MIPS-add-SPI-flash-init-hook.patch deleted file mode 100644 index 71f094b..0000000 --- a/package/boot/uboot-lantiq/patches/0018-MIPS-add-SPI-flash-init-hook.patch +++ /dev/null @@ -1,47 +0,0 @@ -From 888b33e84082fe72d60d528c05c885c0c9d70bc4 Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Tue, 6 Nov 2012 21:19:43 +0100 -Subject: MIPS: add SPI flash init hook - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/arch/mips/lib/board.c -+++ b/arch/mips/lib/board.c -@@ -32,6 +32,7 @@ - #include <nand.h> - #include <onenand_uboot.h> - #include <spi.h> -+#include <spi_flash.h> - - #ifdef CONFIG_BITBANGMII - #include <miiphy.h> -@@ -312,6 +313,16 @@ void board_init_r(gd_t *id, ulong dest_a - onenand_init(); - #endif - -+#ifdef CONFIG_CMD_SPI -+ puts("SPI: "); -+ spi_init(); /* go init the SPI */ -+ puts("ready\n"); -+#endif -+ -+#if defined(CONFIG_SPI_FLASH) -+ spi_flash_init(); -+#endif -+ - /* relocate environment function pointers etc. */ - env_relocate(); - -@@ -335,12 +346,6 @@ void board_init_r(gd_t *id, ulong dest_a - /* Initialize from environment */ - load_addr = getenv_ulong("loadaddr", 16, load_addr); - --#ifdef CONFIG_CMD_SPI -- puts("SPI: "); -- spi_init(); /* go init the SPI */ -- puts("ready\n"); --#endif -- - #if defined(CONFIG_MISC_INIT_R) - /* miscellaneous platform dependent initialisations */ - misc_init_r(); diff --git a/package/boot/uboot-lantiq/patches/0018-tools-lantiq-add-NAND-SPL-support.patch b/package/boot/uboot-lantiq/patches/0018-tools-lantiq-add-NAND-SPL-support.patch new file mode 100644 index 0000000..04c254f --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0018-tools-lantiq-add-NAND-SPL-support.patch @@ -0,0 +1,228 @@ +From 43b9a7c9b903302c56d0a1d292a146dbf4de8e49 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 12 Aug 2013 01:17:08 +0200 +Subject: tools: lantiq: add NAND SPL support + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/tools/ltq-boot-image.c b/tools/ltq-boot-image.c +index 75a188c..743fc6f 100644 +--- a/tools/ltq-boot-image.c ++++ b/tools/ltq-boot-image.c +@@ -14,7 +14,8 @@ + + enum image_types { + IMAGE_NONE, +- IMAGE_SFSPL ++ IMAGE_SFSPL, ++ IMAGE_NANDSPL + }; + + /* Lantiq non-volatile bootstrap command IDs */ +@@ -43,6 +44,8 @@ enum nvb_cmd_flags { + struct args { + enum image_types type; + __u32 entry_addr; ++ loff_t uboot_offset; ++ unsigned int page_size; + const char *uboot_bin; + const char *spl_bin; + const char *out_bin; +@@ -50,10 +53,11 @@ struct args { + + static void usage_msg(const char *name) + { +- fprintf(stderr, "%s: [-h] -t type -e entry-addr -u uboot-bin [-s spl-bin] -o out-bin\n", ++ fprintf(stderr, "%s: [-h] -t type -e entry-addr [-x uboot-offset] [-p page-size] -u uboot-bin [-s spl-bin] -o out-bin\n", + name); + fprintf(stderr, " Image types:\n" +- " sfspl - SPL + [compressed] U-Boot for SPI flash\n"); ++ " sfspl - SPL + [compressed] U-Boot for SPI flash\n" ++ " nandspl - SPL + [compressed] U-Boot for NAND flash\n"); + } + + static enum image_types parse_image_type(const char *type) +@@ -64,6 +68,9 @@ static enum image_types parse_image_type(const char *type) + if (!strncmp(type, "sfspl", 6)) + return IMAGE_SFSPL; + ++ if (!strncmp(type, "nandspl", 6)) ++ return IMAGE_NANDSPL; ++ + return IMAGE_NONE; + } + +@@ -73,7 +80,7 @@ static int parse_args(int argc, char *argv[], struct args *arg) + + memset(arg, 0, sizeof(*arg)); + +- while ((opt = getopt(argc, argv, "ht:e:u:s:o:")) != -1) { ++ while ((opt = getopt(argc, argv, "ht:e:x:p:u:s:o:")) != -1) { + switch (opt) { + case 'h': + usage_msg(argv[0]); +@@ -84,6 +91,12 @@ static int parse_args(int argc, char *argv[], struct args *arg) + case 'e': + arg->entry_addr = strtoul(optarg, NULL, 16); + break; ++ case 'x': ++ arg->uboot_offset = strtoul(optarg, NULL, 16); ++ break; ++ case 'p': ++ arg->page_size = strtoul(optarg, NULL, 10); ++ break; + case 'u': + arg->uboot_bin = optarg; + break; +@@ -114,11 +127,22 @@ static int parse_args(int argc, char *argv[], struct args *arg) + goto parse_error; + } + +- if (arg->type == IMAGE_SFSPL && !arg->spl_bin) { ++ if ((arg->type == IMAGE_SFSPL || arg->type == IMAGE_NANDSPL) && ++ !arg->spl_bin) { + fprintf(stderr, "Missing SPL binary\n"); + goto parse_error; + } + ++ if (arg->type == IMAGE_NANDSPL && !arg->uboot_offset) { ++ fprintf(stderr, "Missing U-Boot offset\n"); ++ goto parse_error; ++ } ++ ++ if (arg->type == IMAGE_NANDSPL && !arg->page_size) { ++ fprintf(stderr, "Missing NAND page size\n"); ++ goto parse_error; ++ } ++ + return 0; + + parse_error: +@@ -174,6 +198,19 @@ static int write_nvb_start_header(int fd, __u32 addr) + return write_header(fd, hdr, sizeof(hdr)); + } + ++#if 0 ++static int write_nvb_regcfg_header(int fd, __u32 addr) ++{ ++ __u32 hdr[2]; ++ ++ hdr[0] = build_nvb_command(NVB_CMD_REGCFG, NVB_FLAG_SDBG | ++ NVB_FLAG_DBG); ++ hdr[1] = cpu_to_be32(addr); ++ ++ return write_header(fd, hdr, sizeof(hdr)); ++} ++#endif ++ + static int open_input_bin(const char *name, void **ptr, size_t *size) + { + struct stat sbuf; +@@ -238,9 +275,37 @@ static int open_output_bin(const char *name) + return fd; + } + +-static int create_sfspl(const struct args *arg) ++static int pad_to_offset(int fd, loff_t offset) + { +- int out_fd, uboot_fd, spl_fd, ret; ++ loff_t pos; ++ size_t size; ++ ssize_t n; ++ __u8 *buf; ++ ++ pos = lseek(fd, 0, SEEK_CUR); ++ size = offset - pos; ++ ++ buf = malloc(size); ++ if (!buf) { ++ fprintf(stderr, "Failed to malloc buffer\n"); ++ return -1; ++ } ++ ++ memset(buf, 0xff, size); ++ n = write(fd, buf, size); ++ free(buf); ++ ++ if (n != size) { ++ fprintf(stderr, "Failed to write pad bytes\n"); ++ return -1; ++ } ++ ++ return 0; ++} ++ ++static int create_spl_image(const struct args *arg) ++{ ++ int out_fd, uboot_fd, spl_fd, ret = 0; + void *uboot_ptr, *spl_ptr; + size_t uboot_size, spl_size; + +@@ -256,9 +321,22 @@ static int create_sfspl(const struct args *arg) + if (0 > uboot_fd) + goto err_uboot; + ++#if 0 ++ ret = write_nvb_regcfg_header(out_fd, 0); ++ if (ret) ++ goto err_write; ++#endif ++ + ret = write_nvb_dwnld_header(out_fd, spl_size, arg->entry_addr); + if (ret) + goto err_write; ++#if 0 ++ if (arg->page_size) { ++ ret = pad_to_offset(out_fd, arg->page_size); ++ if (ret) ++ goto err_write; ++ } ++#endif + + ret = copy_bin(out_fd, spl_ptr, spl_size); + if (ret) +@@ -268,16 +346,16 @@ static int create_sfspl(const struct args *arg) + if (ret) + goto err_write; + ++ if (arg->uboot_offset) { ++ ret = pad_to_offset(out_fd, arg->uboot_offset); ++ if (ret) ++ goto err_write; ++ } ++ + ret = copy_bin(out_fd, uboot_ptr, uboot_size); + if (ret) + goto err_write; + +- close_input_bin(uboot_fd, uboot_ptr, uboot_size); +- close_input_bin(spl_fd, spl_ptr, spl_size); +- close(out_fd); +- +- return 0; +- + err_write: + close_input_bin(uboot_fd, uboot_ptr, uboot_size); + err_uboot: +@@ -285,7 +363,7 @@ err_uboot: + err_spl: + close(out_fd); + err: +- return -1; ++ return ret; + } + + int main(int argc, char *argv[]) +@@ -299,7 +377,8 @@ int main(int argc, char *argv[]) + + switch (arg.type) { + case IMAGE_SFSPL: +- ret = create_sfspl(&arg); ++ case IMAGE_NANDSPL: ++ ret = create_spl_image(&arg); + break; + default: + fprintf(stderr, "Image type not implemented\n"); +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0019-Makefile-add-Lantiq-NAND-SPL-images.patch b/package/boot/uboot-lantiq/patches/0019-Makefile-add-Lantiq-NAND-SPL-images.patch new file mode 100644 index 0000000..4ea965c --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0019-Makefile-add-Lantiq-NAND-SPL-images.patch @@ -0,0 +1,53 @@ +From 2e01dc015bc8bb9ca45f369025c342ede990863e Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 12 Aug 2013 01:16:09 +0200 +Subject: Makefile: add Lantiq NAND SPL images + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/.gitignore b/.gitignore +index 7abdc37..869b1b8 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -54,6 +54,9 @@ + /u-boot.ltq.lzma.norspl + /u-boot.ltq.lzo.norspl + /u-boot.ltq.norspl ++/u-boot.ltq.lzma.nandspl ++/u-boot.ltq.lzo.nandspl ++/u-boot.ltq.nandspl + /u-boot.lzma.img + /u-boot.lzo.img + +diff --git a/Makefile b/Makefile +index 73ec67d..0445035 100644 +--- a/Makefile ++++ b/Makefile +@@ -599,6 +599,24 @@ $(obj)u-boot.ltq.lzma.sfspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \ + -s $(obj)spl/u-boot-spl.bin -u $< -o $@ + ++$(obj)u-boot.ltq.nandspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin ++ $(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \ ++ -x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \ ++ -p $(CONFIG_SYS_NAND_PAGE_SIZE) \ ++ -s $(obj)spl/u-boot-spl.bin -u $< -o $@ ++ ++$(obj)u-boot.ltq.lzo.nandspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin ++ $(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \ ++ -x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \ ++ -p $(CONFIG_SYS_NAND_PAGE_SIZE) \ ++ -s $(obj)spl/u-boot-spl.bin -u $< -o $@ ++ ++$(obj)u-boot.ltq.lzma.nandspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin ++ $(obj)tools/ltq-boot-image -t nandspl -e $(CONFIG_SPL_TEXT_BASE) \ ++ -x $(CONFIG_SYS_NAND_U_BOOT_OFFS) \ ++ -p $(CONFIG_SYS_NAND_PAGE_SIZE) \ ++ -s $(obj)spl/u-boot-spl.bin -u $< -o $@ ++ + $(obj)u-boot.ltq.norspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin + cat $(obj)spl/u-boot-spl.bin $< > $@ + +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0020-MIPS-lantiq-add-NAND-SPL-support.patch b/package/boot/uboot-lantiq/patches/0020-MIPS-lantiq-add-NAND-SPL-support.patch new file mode 100644 index 0000000..a5ea68f --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0020-MIPS-lantiq-add-NAND-SPL-support.patch @@ -0,0 +1,172 @@ +From e17398316e82d8b28217232b4fd6030c65138e74 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 12 Aug 2013 01:18:00 +0200 +Subject: MIPS: lantiq: add NAND SPL support + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/arch/mips/cpu/mips32/lantiq-common/spl.c b/arch/mips/cpu/mips32/lantiq-common/spl.c +index 489a82b..3d9d4d4 100644 +--- a/arch/mips/cpu/mips32/lantiq-common/spl.c ++++ b/arch/mips/cpu/mips32/lantiq-common/spl.c +@@ -8,6 +8,7 @@ + #include <image.h> + #include <version.h> + #include <spi_flash.h> ++#include <nand.h> + #include <linux/compiler.h> + #include <lzma/LzmaDec.h> + #include <linux/lzo.h> +@@ -63,6 +64,18 @@ + #define spl_boot_nor_flash 0 + #endif + ++#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL) ++#define spl_boot_nand_flash 1 ++#else ++#define spl_boot_nand_flash 0 ++#ifndef CONFIG_SYS_NAND_U_BOOT_OFFS ++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0 ++#endif ++#ifndef CONFIG_SYS_NAND_PAGE_SIZE ++#define CONFIG_SYS_NAND_PAGE_SIZE 0 ++#endif ++#endif ++ + #define spl_sync() __asm__ __volatile__("sync"); + + struct spl_image { +@@ -337,6 +350,58 @@ static int spl_load_nor_flash(struct spl_image *spl) + return ret; + } + ++static int spl_load_nand_flash(struct spl_image *spl) ++{ ++ image_header_t *hdr; ++ int ret; ++ unsigned long loadaddr; ++ ++ /* ++ * Image format: ++ * ++ * - 12 byte non-volatile bootstrap header ++ * - SPL binary ++ * - 12 byte non-volatile bootstrap header ++ * - padding bytes up to CONFIG_SYS_NAND_U_BOOT_OFFS ++ * - 64 byte U-Boot mkimage header ++ * - U-Boot binary ++ */ ++ spl->data_addr = CONFIG_SYS_NAND_U_BOOT_OFFS; ++ ++ spl_puts("SPL: initializing NAND flash\n"); ++ nand_init(); ++ ++ spl_debug("SPL: reading image header at page offset %lx\n", ++ spl->data_addr); ++ ++ hdr = (image_header_t *) CONFIG_LOADADDR; ++ ret = nand_spl_load_image(spl->data_addr, ++ CONFIG_SYS_NAND_PAGE_SIZE, hdr); ++ if (ret) ++ return ret; ++ ++ spl_debug("SPL: checking image header at address %p\n", hdr); ++ ++ ret = spl_parse_image(hdr, spl); ++ if (ret) ++ return ret; ++ ++ if (spl_is_compressed(spl)) ++ loadaddr = CONFIG_LOADADDR; ++ else ++ loadaddr = spl->entry_addr; ++ ++ spl_puts("SPL: loading U-Boot to RAM\n"); ++ ++ ret = nand_spl_load_image(spl->data_addr, spl->data_size, ++ (void *) loadaddr); ++ ++ if (spl_is_compressed(spl)) ++ ret = spl_uncompress(spl, loadaddr); ++ ++ return ret; ++} ++ + static int spl_load(struct spl_image *spl) + { + int ret; +@@ -345,6 +410,8 @@ static int spl_load(struct spl_image *spl) + ret = spl_load_spi_flash(spl); + else if (spl_boot_nor_flash) + ret = spl_load_nor_flash(spl); ++ else if (spl_boot_nand_flash) ++ ret = spl_load_nand_flash(spl); + else + ret = 1; + +diff --git a/arch/mips/include/asm/lantiq/config.h b/arch/mips/include/asm/lantiq/config.h +index feac30d..483cc94 100644 +--- a/arch/mips/include/asm/lantiq/config.h ++++ b/arch/mips/include/asm/lantiq/config.h +@@ -40,6 +40,26 @@ + #define CONFIG_SPI_SPL_SIMPLE + #endif + ++/* ++ * NAND flash SPL ++ * BOOT CFG 06 only (address cycle based probing, 2KB or 512B page size) ++ */ ++#if defined(CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH) && defined(CONFIG_SYS_BOOT_NANDSPL) ++#define CONFIG_SPL ++#define CONFIG_SPL_NAND_SUPPORT ++#define CONFIG_SPL_NAND_DRIVERS ++#define CONFIG_SPL_NAND_SIMPLE ++#define CONFIG_SPL_NAND_ECC ++ ++/* use software ECC until driver supports HW ECC */ ++#define CONFIG_SPL_NAND_SOFTECC ++#define CONFIG_SYS_NAND_ECCSIZE 256 ++#define CONFIG_SYS_NAND_ECCBYTES 3 ++#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \ ++ 48, 49, 50, 51, 52, 53, 54, 55, \ ++ 56, 57, 58, 59, 60, 61, 62, 63} ++#endif ++ + #if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL) + #define CONFIG_SPL + #endif +@@ -148,6 +168,21 @@ + #define CONFIG_ENV_LOAD_UBOOT_SF + #endif + ++#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) ++#define CONFIG_ENV_WRITE_UBOOT_NAND \ ++ "write-uboot-nand=" \ ++ "nand erase 0 $filesize && " \ ++ "nand write $fileaddr 0 $filesize\0" ++ ++#define CONFIG_ENV_LOAD_UBOOT_NAND \ ++ "load-uboot-nandspl=tftpboot u-boot.ltq.nandspl\0" \ ++ "load-uboot-nandspl-lzo=tftpboot u-boot.ltq.lzo.nandspl\0" \ ++ "load-uboot-nandspl-lzma=tftpboot u-boot.ltq.lzma.nandspl\0" ++#else ++#define CONFIG_ENV_WRITE_UBOOT_NAND ++#define CONFIG_ENV_LOAD_UBOOT_NAND ++#endif ++ + #define CONFIG_ENV_LANTIQ_DEFAULTS \ + CONFIG_ENV_CONSOLEDEV \ + CONFIG_ENV_ADDCONSOLE \ +@@ -159,6 +194,8 @@ + CONFIG_ENV_LOAD_UBOOT_NOR \ + CONFIG_ENV_SF_PROBE \ + CONFIG_ENV_WRITE_UBOOT_SF \ +- CONFIG_ENV_LOAD_UBOOT_SF ++ CONFIG_ENV_LOAD_UBOOT_SF \ ++ CONFIG_ENV_WRITE_UBOOT_NAND \ ++ CONFIG_ENV_LOAD_UBOOT_NAND + + #endif /* __LANTIQ_CONFIG_H__ */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch b/package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch new file mode 100644 index 0000000..160ede9 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0021-MIPS-vrx200-add-NAND-SPL-support.patch @@ -0,0 +1,37 @@ +From 7361581a1baaec43058f5b9350c32c7ac4e58064 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 12 Aug 2013 00:11:16 +0200 +Subject: MIPS: vrx200: add NAND SPL support + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/arch/mips/cpu/mips32/vrx200/config.mk b/arch/mips/cpu/mips32/vrx200/config.mk +index 442156a..b0fc882 100644 +--- a/arch/mips/cpu/mips32/vrx200/config.mk ++++ b/arch/mips/cpu/mips32/vrx200/config.mk +@@ -27,4 +27,9 @@ ALL-y += $(obj)u-boot.ltq.norspl + ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl + ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl + endif ++ifdef CONFIG_SYS_BOOT_NANDSPL ++ALL-y += $(obj)u-boot.ltq.nandspl ++ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.nandspl ++ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.nandspl ++endif + endif +diff --git a/arch/mips/include/asm/arch-vrx200/config.h b/arch/mips/include/asm/arch-vrx200/config.h +index 88ef256..4ec6092 100644 +--- a/arch/mips/include/asm/arch-vrx200/config.h ++++ b/arch/mips/include/asm/arch-vrx200/config.h +@@ -164,7 +164,7 @@ + #define CONFIG_SYS_TEXT_BASE 0xB0000000 + #endif + +-#if defined(CONFIG_SYS_BOOT_SFSPL) ++#if defined(CONFIG_SYS_BOOT_SFSPL) || defined(CONFIG_SYS_BOOT_NANDSPL) + #define CONFIG_SYS_TEXT_BASE 0x80100000 + #define CONFIG_SPL_TEXT_BASE 0xBE220000 + #endif +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch b/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch new file mode 100644 index 0000000..478193e --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0022-MIPS-lantiq-easy80920-add-support-for-NAND-SPL.patch @@ -0,0 +1,68 @@ +From 6fa1c350fa19a054371eccef84e4885cfdd6a2d7 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 19 Aug 2013 18:11:31 +0200 +Subject: MIPS: lantiq: easy80920: add support for NAND SPL + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/boards.cfg b/boards.cfg +index f090726..394ede7 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -509,6 +509,7 @@ Active mips mips32 incaip - incaip + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> ++Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/include/configs/easy80920.h b/include/configs/easy80920.h +index ad69bc2..56ceedb 100644 +--- a/include/configs/easy80920.h ++++ b/include/configs/easy80920.h +@@ -31,6 +31,14 @@ + + #define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ + ++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ ++#define CONFIG_SYS_NAND_PAGE_COUNT 128 ++#define CONFIG_SYS_NAND_PAGE_SIZE 2048 ++#define CONFIG_SYS_NAND_OOBSIZE 64 ++#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) ++#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS ++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 ++ + #define CONFIG_LTQ_SPL_COMP_LZO + #define CONFIG_LTQ_SPL_CONSOLE + +@@ -57,6 +65,11 @@ + #define CONFIG_ENV_OVERWRITE + #define CONFIG_ENV_OFFSET (192 * 1024) + #define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#elif defined(CONFIG_SYS_BOOT_NANDSPL) ++#define CONFIG_ENV_IS_IN_NAND ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (256 * 1024) + #else + #define CONFIG_ENV_IS_NOWHERE + #endif +@@ -84,9 +97,13 @@ + #define CONFIG_ENV_UPDATE_UBOOT_SF \ + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" + ++#define CONFIG_ENV_UPDATE_UBOOT_NAND \ ++ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" ++ + #define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_ENV_LANTIQ_DEFAULTS \ + CONFIG_ENV_UPDATE_UBOOT_NOR \ +- CONFIG_ENV_UPDATE_UBOOT_SF ++ CONFIG_ENV_UPDATE_UBOOT_SF \ ++ CONFIG_ENV_UPDATE_UBOOT_NAND + + #endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch b/package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch new file mode 100644 index 0000000..172729c --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0023-MIPS-lantiq-add-default-openwrt-config.patch @@ -0,0 +1,56 @@ +From 8f584936adad0fca8beece5f55eadcdcd02fad0a Mon Sep 17 00:00:00 2001 +From: Luka Perkov <luka@openwrt.org> +Date: Sat, 17 Aug 2013 03:44:46 +0200 +Subject: MIPS: lantiq: add default openwrt config + +Signed-off-by: Luka Perkov <luka@openwrt.org> +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/include/configs/openwrt-lantiq-common.h b/include/configs/openwrt-lantiq-common.h +new file mode 100644 +index 0000000..d119bef +--- /dev/null ++++ b/include/configs/openwrt-lantiq-common.h +@@ -0,0 +1,39 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __OPENWRT_LANTIQ_COMMON_H ++#define __OPENWRT_LANTIQ_COMMON_H ++ ++/* Commands */ ++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) ++#define CONFIG_CMD_PING ++#endif ++ ++/* Compression */ ++#define CONFIG_LZMA ++ ++/* Auto boot */ ++#define CONFIG_BOOTDELAY 2 ++ ++/* Environment */ ++#if !defined(CONFIG_SYS_BOOT_RAM) ++#define CONFIG_BOOTCOMMAND \ ++ "bootm ${kernel_addr}" ++#endif ++ ++/* Ethernet */ ++#if defined(CONFIG_LTQ_SUPPORT_ETHERNET) ++#define CONFIG_ETHADDR 00:01:02:03:04:05 ++#define CONFIG_SERVERIP 192.168.1.2 ++#define CONFIG_IPADDR 192.168.1.1 ++#endif ++ ++/* Unnecessary */ ++#undef CONFIG_BOOTM_NETBSD ++#undef CONFIG_BOOTM_PLAN9 ++#undef CONFIG_BOOTM_RTEMS ++ ++#endif /* __OPENWRT_LANTIQ_COMMON_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0024-MIPS-VRX200-add-option-to-boot-from-AVM-EVA-loader.patch b/package/boot/uboot-lantiq/patches/0024-MIPS-VRX200-add-option-to-boot-from-AVM-EVA-loader.patch deleted file mode 100644 index ba24bae..0000000 --- a/package/boot/uboot-lantiq/patches/0024-MIPS-VRX200-add-option-to-boot-from-AVM-EVA-loader.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 2c6115188c7353a601835885a6c544240cfc479e Mon Sep 17 00:00:00 2001 -From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Fri, 30 Nov 2012 18:09:25 +0100 -Subject: MIPS: VRX200: add option to boot from AVM EVA loader - -Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> - ---- a/arch/mips/cpu/mips32/vrx200/config.mk -+++ b/arch/mips/cpu/mips32/vrx200/config.mk -@@ -17,6 +17,9 @@ endif - LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o - - ifndef CONFIG_SPL_BUILD -+ifdef CONFIG_SYS_BOOT_EVA -+ALL-y += $(obj)u-boot.bin.lzma -+endif - ifdef CONFIG_SYS_BOOT_SFSPL - ALL-y += $(obj)u-boot.ltq.sfspl - ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl ---- a/arch/mips/include/asm/arch-vrx200/config.h -+++ b/arch/mips/include/asm/arch-vrx200/config.h -@@ -161,6 +161,11 @@ - #define CONFIG_SYS_DISABLE_CACHE - #endif - -+#if defined(CONFIG_SYS_BOOT_EVA) -+#define CONFIG_SYS_TEXT_BASE 0x80100000 -+#define CONFIG_SKIP_LOWLEVEL_INIT -+#endif -+ - #if defined(CONFIG_SYS_BOOT_NOR) - #define CONFIG_SYS_TEXT_BASE 0xB0000000 - #endif diff --git a/package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch b/package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch new file mode 100644 index 0000000..8c9edb9 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0024-MIPS-lantiq-easy50712-add-openwrt-lantiq-common.h.patch @@ -0,0 +1,31 @@ +From ac6896098d9dd62a248340e6a090574399e1fd87 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 19 Aug 2013 18:46:47 +0200 +Subject: MIPS: lantiq: easy50712: add openwrt-lantiq-common.h + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/include/configs/easy50712.h b/include/configs/easy50712.h +index 6d7988c..bc8820a 100644 +--- a/include/configs/easy50712.h ++++ b/include/configs/easy50712.h +@@ -62,13 +62,13 @@ + #define CONFIG_CONSOLE_ASC 1 + #define CONFIG_CONSOLE_DEV "ttyLTQ1" + +-/* Commands */ +-#define CONFIG_CMD_PING +- + /* Pull in default board configs for Lantiq XWAY Danube */ + #include <asm/lantiq/config.h> + #include <asm/arch/config.h> + ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ + #define CONFIG_ENV_UPDATE_UBOOT_NOR \ + "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" + +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch b/package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch new file mode 100644 index 0000000..15fc4c5 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0025-MIPS-lantiq-easy80920-add-openwrt-lantiq-common.h.patch @@ -0,0 +1,31 @@ +From 7afbe4633773905ef94a8404510fb5a459926000 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Mon, 19 Aug 2013 18:11:57 +0200 +Subject: MIPS: lantiq: easy80920: add openwrt-lantiq-common.h + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/include/configs/easy80920.h b/include/configs/easy80920.h +index 56ceedb..6f5ac03 100644 +--- a/include/configs/easy80920.h ++++ b/include/configs/easy80920.h +@@ -84,13 +84,13 @@ + #define CONFIG_CONSOLE_ASC 1 + #define CONFIG_CONSOLE_DEV "ttyLTQ1" + +-/* Commands */ +-#define CONFIG_CMD_PING +- + /* Pull in default board configs for Lantiq XWAY VRX200 */ + #include <asm/lantiq/config.h> + #include <asm/arch/config.h> + ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ + #define CONFIG_ENV_UPDATE_UBOOT_NOR \ + "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" + +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch b/package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch index 4698e67..aa1543b 100644 --- a/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-Arcadyan-ARV4519.patch +++ b/package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Arcadyan-ARV4519.patch @@ -1,20 +1,21 @@ -From 4a738c02a7190756e01ba58c93c4b07bc6d6c2aa Mon Sep 17 00:00:00 2001 +From 9f915cf9550a6234adecaf3031c2b279835e14af Mon Sep 17 00:00:00 2001 From: Luka Perkov <luka@openwrt.org> -Date: Wed, 29 Aug 2012 22:08:42 +0200 +Date: Sat, 2 Mar 2013 23:34:00 +0100 Subject: MIPS: add board support for Arcadyan ARV4519 Signed-off-by: Luka Perkov <luka@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/board/arcadyan/arv4519pw/Makefile b/board/arcadyan/arv4519pw/Makefile +new file mode 100644 +index 0000000..3a547c2 --- /dev/null +++ b/board/arcadyan/arv4519pw/Makefile -@@ -0,0 +1,29 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,27 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -38,14 +39,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/board/arcadyan/arv4519pw/arv4519pw.c b/board/arcadyan/arv4519pw/arv4519pw.c +new file mode 100644 +index 0000000..a9dfd03 --- /dev/null +++ b/board/arcadyan/arv4519pw/arv4519pw.c -@@ -0,0 +1,52 @@ +@@ -0,0 +1,51 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -93,27 +96,31 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + return switch_device_register(&ar8216_dev); +} +diff --git a/board/arcadyan/arv4519pw/config.mk b/board/arcadyan/arv4519pw/config.mk +new file mode 100644 +index 0000000..9d8953b --- /dev/null +++ b/board/arcadyan/arv4519pw/config.mk -@@ -0,0 +1,8 @@ +@@ -0,0 +1,7 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com +# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/arcadyan/arv4519pw/ddr_settings.h b/board/arcadyan/arv4519pw/ddr_settings.h +new file mode 100644 +index 0000000..c5e88b3 --- /dev/null +++ b/board/arcadyan/arv4519pw/ddr_settings.h -@@ -0,0 +1,56 @@ +@@ -0,0 +1,55 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org> + * -+ * generated with lantiq_ram_extract_magic.awk ++ * This file has been generated with lantiq_ram_extract_magic.awk script. + * -+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MC_DC00_VALUE 0x1B1B @@ -163,25 +170,30 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +#define MC_DC46_VALUE 0x0 +diff --git a/boards.cfg b/boards.cfg +index 394ede7..f300d5a 100644 --- a/boards.cfg +++ b/boards.cfg -@@ -438,6 +438,8 @@ vct_premium mips - vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND - vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE - vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE -+arv4519pw_ram mips mips32 arv4519pw arcadyan danube arv4519pw:SYS_BOOT_RAM -+arv4519pw_nor mips mips32 arv4519pw arcadyan danube arv4519pw:SYS_BOOT_NOR - arv7518pw_ram mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_RAM - arv7518pw_nor mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_NOR - dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000 +@@ -502,6 +502,9 @@ Active mips mips32 au1x00 - dbau1x00 + Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 - ++Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/include/configs/arv4519pw.h b/include/configs/arv4519pw.h +new file mode 100644 +index 0000000..6907108 --- /dev/null +++ b/include/configs/arv4519pw.h -@@ -0,0 +1,69 @@ +@@ -0,0 +1,67 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org> + * -+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H @@ -193,7 +205,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +/* Configure SoC */ +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ + +/* Switch devices */ @@ -205,44 +219,44 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SIZE (64 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#else +#define CONFIG_ENV_IS_NOWHERE -+#define CONFIG_ENV_SIZE (2 * 1024) +#endif + ++#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ +/* Console */ +#define CONFIG_LTQ_ADVANCED_CONSOLE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONSOLE_ASC 1 +#define CONFIG_CONSOLE_DEV "ttyLTQ1" + -+/* Commands */ -+#define CONFIG_CMD_PING -+ +/* Pull in default board configs for Lantiq XWAY Danube */ +#include <asm/lantiq/config.h> +#include <asm/arch/config.h> + -+/* Compression */ -+#define CONFIG_LZMA -+ -+/* Auto boot */ -+#define CONFIG_BOOTDELAY 2 -+ -+/* Environment configuration */ -+#define CONFIG_BOOTCOMMAND \ -+ "run addeth; bootm ${kernel_addr}" ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" + +#define CONFIG_ENV_UPDATE_UBOOT_NOR \ + "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" + -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ + "kernel_addr=0xB0040000\0" + +#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch b/package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch index 4156089..2e9b855 100644 --- a/package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch +++ b/package/boot/uboot-lantiq/patches/0027-MIPS-add-board-support-for-Arcadyan-ARV7518.patch @@ -1,20 +1,21 @@ -From 289f7ed5d725067b4eb4b1a105bb63d55bf20392 Mon Sep 17 00:00:00 2001 +From 54a31b334162e8dc2ea891057ddeab42978db8b3 Mon Sep 17 00:00:00 2001 From: Luka Perkov <luka@openwrt.org> -Date: Wed, 29 Aug 2012 22:08:41 +0200 +Date: Sat, 2 Mar 2013 23:34:00 +0100 Subject: MIPS: add board support for Arcadyan ARV7518 Signed-off-by: Luka Perkov <luka@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/board/arcadyan/arv7518pw/Makefile b/board/arcadyan/arv7518pw/Makefile +new file mode 100644 +index 0000000..3a547c2 --- /dev/null +++ b/board/arcadyan/arv7518pw/Makefile -@@ -0,0 +1,29 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,27 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -38,14 +39,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/board/arcadyan/arv7518pw/arv7518pw.c b/board/arcadyan/arv7518pw/arv7518pw.c +new file mode 100644 +index 0000000..a9dfd03 --- /dev/null +++ b/board/arcadyan/arv7518pw/arv7518pw.c -@@ -0,0 +1,52 @@ +@@ -0,0 +1,51 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -93,27 +96,31 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +{ + return switch_device_register(&ar8216_dev); +} +diff --git a/board/arcadyan/arv7518pw/config.mk b/board/arcadyan/arv7518pw/config.mk +new file mode 100644 +index 0000000..9d8953b --- /dev/null +++ b/board/arcadyan/arv7518pw/config.mk -@@ -0,0 +1,8 @@ +@@ -0,0 +1,7 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com +# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/arcadyan/arv7518pw/ddr_settings.h b/board/arcadyan/arv7518pw/ddr_settings.h +new file mode 100644 +index 0000000..8b5e9c5 --- /dev/null +++ b/board/arcadyan/arv7518pw/ddr_settings.h -@@ -0,0 +1,56 @@ +@@ -0,0 +1,55 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org> + * -+ * generated with lantiq_ram_extract_magic.awk ++ * This file has been generated with lantiq_ram_extract_magic.awk script. + * -+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MC_DC00_VALUE 0x1B1B @@ -163,25 +170,30 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +#define MC_DC46_VALUE 0x0 +diff --git a/boards.cfg b/boards.cfg +index f300d5a..e832423 100644 --- a/boards.cfg +++ b/boards.cfg -@@ -438,6 +438,8 @@ vct_premium mips - vct_premium_onenand mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND - vct_premium_onenand_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE - vct_premium_small mips mips32 vct micronas - vct:VCT_PREMIUM,VCT_SMALL_IMAGE -+arv7518pw_ram mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_RAM -+arv7518pw_nor mips mips32 arv7518pw arcadyan danube arv7518pw:SYS_BOOT_NOR - dbau1000 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1000 - dbau1100 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1100 - dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500 +@@ -505,6 +505,9 @@ Active mips mips32 au1x00 - pb1x00 + Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/include/configs/arv7518pw.h b/include/configs/arv7518pw.h +new file mode 100644 +index 0000000..8cf1708 --- /dev/null +++ b/include/configs/arv7518pw.h -@@ -0,0 +1,69 @@ +@@ -0,0 +1,67 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org> + * -+ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H @@ -193,7 +205,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +/* Configure SoC */ +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ + +/* Switch devices */ @@ -205,44 +219,44 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (192 * 1024) -+#define CONFIG_ENV_SIZE (64 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#else +#define CONFIG_ENV_IS_NOWHERE -+#define CONFIG_ENV_SIZE (2 * 1024) +#endif + ++#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ +/* Console */ +#define CONFIG_LTQ_ADVANCED_CONSOLE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONSOLE_ASC 1 +#define CONFIG_CONSOLE_DEV "ttyLTQ1" + -+/* Commands */ -+#define CONFIG_CMD_PING -+ +/* Pull in default board configs for Lantiq XWAY Danube */ +#include <asm/lantiq/config.h> +#include <asm/arch/config.h> + -+/* Compression */ -+#define CONFIG_LZMA -+ -+/* Auto boot */ -+#define CONFIG_BOOTDELAY 2 -+ -+/* Environment configuration */ -+#define CONFIG_BOOTCOMMAND \ -+ "run addeth; bootm ${kernel_addr}" ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" + +#define CONFIG_ENV_UPDATE_UBOOT_NOR \ + "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" + -+#define CONFIG_EXTRA_ENV_SETTINGS \ -+ CONFIG_ENV_LANTIQ_DEFAULTS \ -+ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ + "kernel_addr=0xB0040000\0" + +#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch b/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch new file mode 100644 index 0000000..c56365b --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0028-MIPS-add-board-support-for-AudioCodes-MP-252.patch @@ -0,0 +1,268 @@ +From 4bacfc80eae768be45f9ddf7588ec55281354648 Mon Sep 17 00:00:00 2001 +From: Daniel Golle <daniel.golle@gmail.com> +Date: Fri, 8 Mar 2013 13:29:04 +0200 +Subject: MIPS: add board support for AudioCodes MP-252 + +Signed-off-by: Daniel Golle <dgolle@allnet.de> + +diff --git a/board/audiocodes/acmp252/Makefile b/board/audiocodes/acmp252/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/audiocodes/acmp252/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/audiocodes/acmp252/acmp252.c b/board/audiocodes/acmp252/acmp252.c +new file mode 100644 +index 0000000..3368506 +--- /dev/null ++++ b/board/audiocodes/acmp252/acmp252.c +@@ -0,0 +1,66 @@ ++/* ++ * Copyright (C) 2013 Daniel Golle <daniel.golle@gmail.com> ++ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <switch.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/chipid.h> ++ ++static void gpio_init(void) ++{ ++ /* Activate reset line of ADM6996I switch */ ++ gpio_direction_output(19, 0); ++} ++ ++int board_early_init_f(void) ++{ ++ gpio_init(); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Lantiq ADM6996I switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device adm6996i_dev = { ++ .name = "adm6996i", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ /* Deactivate reset line of ADM6996I switch */ ++ gpio_set_value(19, 1); ++ ++ /* ADM6996I needs some time to come out of reset */ ++ __udelay(50000); ++ ++ return switch_device_register(&adm6996i_dev); ++} +diff --git a/board/audiocodes/acmp252/config.mk b/board/audiocodes/acmp252/config.mk +new file mode 100644 +index 0000000..9d8953b +--- /dev/null ++++ b/board/audiocodes/acmp252/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/audiocodes/acmp252/ddr_settings.h b/board/audiocodes/acmp252/ddr_settings.h +new file mode 100644 +index 0000000..d0b4f20 +--- /dev/null ++++ b/board/audiocodes/acmp252/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x403 ++#define MC_DC08_VALUE 0x103 ++#define MC_DC09_VALUE 0x80B ++#define MC_DC10_VALUE 0x304 ++#define MC_DC11_VALUE 0xD03 ++#define MC_DC12_VALUE 0x2C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x13C ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x402 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1700 ++#define MC_DC22_VALUE 0x1717 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5C ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x2D93 ++#define MC_DC30_VALUE 0x8300 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +diff --git a/boards.cfg b/boards.cfg +index e832423..9f407b8 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -508,6 +508,8 @@ Active mips mips32 danube arcadyan arv4519pw + Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com> ++Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/include/configs/acmp252.h b/include/configs/acmp252.h +new file mode 100644 +index 0000000..2c9ab19 +--- /dev/null ++++ b/include/configs/acmp252.h +@@ -0,0 +1,60 @@ ++/* ++ * Copyright (C) 2013 Daniel Golle <daniel.golle@gmail.com> ++ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ACMP252" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "AudioCodes MP-252" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_ADM6996I ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0025-MIPS-add-board-support-for-AVM-FritzBox-3370.patch b/package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch index b680a97..3d13f5c 100644 --- a/package/boot/uboot-lantiq/patches/0025-MIPS-add-board-support-for-AVM-FritzBox-3370.patch +++ b/package/boot/uboot-lantiq/patches/0029-MIPS-add-board-support-for-AVM-FritzBox-3370.patch @@ -1,20 +1,22 @@ -From 51f04c00e831b49587f9f766ff1af67d2122feb2 Mon Sep 17 00:00:00 2001 +From 37a95ae4ba75407a26862ece6f48fa68aa6c5c78 Mon Sep 17 00:00:00 2001 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> -Date: Fri, 30 Nov 2012 18:09:47 +0100 +Date: Sat, 2 Mar 2013 23:34:00 +0100 Subject: MIPS: add board support for AVM FritzBox 3370 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/board/avm/fb3370/Makefile b/board/avm/fb3370/Makefile +new file mode 100644 +index 0000000..e3d621e --- /dev/null +++ b/board/avm/fb3370/Makefile -@@ -0,0 +1,29 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,28 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com +# ++# SPDX-License-Identifier: GPL-2.0+ ++# + +include $(TOPDIR)/config.mk + @@ -37,26 +39,30 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/board/avm/fb3370/config.mk b/board/avm/fb3370/config.mk +new file mode 100644 +index 0000000..4dcfd05 --- /dev/null +++ b/board/avm/fb3370/config.mk -@@ -0,0 +1,8 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,7 @@ +# +# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com +# ++# SPDX-License-Identifier: GPL-2.0+ ++# + +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/avm/fb3370/ddr_settings.h b/board/avm/fb3370/ddr_settings.h +new file mode 100644 +index 0000000..307c084 --- /dev/null +++ b/board/avm/fb3370/ddr_settings.h -@@ -0,0 +1,70 @@ +@@ -0,0 +1,69 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MC_CCR00_VALUE 0x101 @@ -100,8 +106,8 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MC_CCR38_VALUE 0x0 +#define MC_CCR39_VALUE 0x141F04 +#define MC_CCR40_VALUE 0x142704 -+#define MC_CCR41_VALUE 0x141b42 -+#define MC_CCR42_VALUE 0x141b42 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 +#define MC_CCR43_VALUE 0x566504 +#define MC_CCR44_VALUE 0x566504 +#define MC_CCR45_VALUE 0x565F17 @@ -121,14 +127,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MC_CCR59_VALUE 0x7800301 +#define MC_CCR60_VALUE 0x7800301 +#define MC_CCR61_VALUE 0x4 +diff --git a/board/avm/fb3370/fb3370.c b/board/avm/fb3370/fb3370.c +new file mode 100644 +index 0000000..ff44c68 --- /dev/null +++ b/board/avm/fb3370/fb3370.c -@@ -0,0 +1,139 @@ +@@ -0,0 +1,138 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -263,26 +271,30 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + break; + } +} +diff --git a/boards.cfg b/boards.cfg +index 9f407b8..ea5c4f9 100644 --- a/boards.cfg +++ b/boards.cfg -@@ -451,6 +451,9 @@ incaip mips - incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 - incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 - incaip_150MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=150000000 -+fb3370_ram mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_RAM -+fb3370_eva mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_EVA -+fb3370_sfspl mips mips32 fb3370 avm vrx200 fb3370:SYS_BOOT_SFSPL - easy80920_nor mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NOR - easy80920_norspl mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_NORSPL - easy80920_ram mips mips32 easy80920 lantiq vrx200 easy80920:SYS_BOOT_RAM +@@ -517,6 +517,9 @@ Active mips mips32 incaip - incaip + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> ++Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/include/configs/fb3370.h b/include/configs/fb3370.h +new file mode 100644 +index 0000000..8ae1373 --- /dev/null +++ b/include/configs/fb3370.h -@@ -0,0 +1,75 @@ +@@ -0,0 +1,78 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com + * -+ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H @@ -293,24 +305,24 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_BOARD_NAME "AVM FritzBox 3370" + +/* Configure SoC */ -+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ + -+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ + +#define CONFIG_LTQ_SUPPORT_SPI_FLASH -+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */ ++#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */ + +#define CONFIG_LTQ_SUPPORT_NAND_FLASH + +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ +#define CONFIG_SPL_SPI_BUS 0 +#define CONFIG_SPL_SPI_CS 4 +#define CONFIG_SPL_SPI_MAX_HZ 25000000 +#define CONFIG_SPL_SPI_MODE 0 + -+#define CONFIG_LTQ_SPL_COMP_LZO -+#define CONFIG_LTQ_SPL_CONSOLE -+ +#define CONFIG_SYS_DRAM_PROBE + +/* Environment */ @@ -329,22 +341,26 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#endif + +#define CONFIG_ENV_SIZE (8 * 1024) -+ +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + ++#if defined(CONFIG_SYS_BOOT_EVA) ++#define CONFIG_SYS_TEXT_BASE 0x80100000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#endif ++ +/* Console */ +#define CONFIG_LTQ_ADVANCED_CONSOLE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_CONSOLE_ASC 1 +#define CONFIG_CONSOLE_DEV "ttyLTQ1" + -+/* Commands */ -+#define CONFIG_CMD_PING -+ +/* Pull in default board configs for Lantiq XWAY VRX200 */ +#include <asm/lantiq/config.h> +#include <asm/arch/config.h> + ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ +#define CONFIG_ENV_UPDATE_UBOOT_SF \ + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" + @@ -353,3 +369,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + CONFIG_ENV_UPDATE_UBOOT_SF + +#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Gigaset-SX76X.patch b/package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch index 810770a..91c6263 100644 --- a/package/boot/uboot-lantiq/patches/0026-MIPS-add-board-support-for-Gigaset-SX76X.patch +++ b/package/boot/uboot-lantiq/patches/0030-MIPS-add-board-support-for-Gigaset-SX76X.patch @@ -1,20 +1,21 @@ -From 66b56aa3a4810f10e0b0c77bb87279a8d64b566b Mon Sep 17 00:00:00 2001 +From 9e9dec563e4d061e7b34d2d59a89eb05c60f43a7 Mon Sep 17 00:00:00 2001 From: Luka Perkov <luka@openwrt.org> -Date: Fri, 16 Dec 2011 11:55:45 +0100 +Date: Sat, 2 Mar 2013 23:34:00 +0100 Subject: MIPS: add board support for Gigaset SX76X Signed-off-by: Luka Perkov <luka@openwrt.org> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/board/gigaset/sx76x/Makefile b/board/gigaset/sx76x/Makefile +new file mode 100644 +index 0000000..3a547c2 --- /dev/null +++ b/board/gigaset/sx76x/Makefile -@@ -0,0 +1,29 @@ -+# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. +@@ -0,0 +1,27 @@ +# +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk @@ -38,27 +39,31 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +sinclude $(obj).depend + +######################################################################### +diff --git a/board/gigaset/sx76x/config.mk b/board/gigaset/sx76x/config.mk +new file mode 100644 +index 0000000..9d8953b --- /dev/null +++ b/board/gigaset/sx76x/config.mk -@@ -0,0 +1,8 @@ +@@ -0,0 +1,7 @@ +# -+# This file is released under the terms of GPL v2 and any later version. -+# See the file COPYING in the root directory of the source tree for details. ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com +# -+# Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++# SPDX-License-Identifier: GPL-2.0+ +# + +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/gigaset/sx76x/ddr_settings.h b/board/gigaset/sx76x/ddr_settings.h +new file mode 100644 +index 0000000..13cd81b --- /dev/null +++ b/board/gigaset/sx76x/ddr_settings.h -@@ -0,0 +1,56 @@ +@@ -0,0 +1,55 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> + * -+ * generated with lantiq_ram_extract_magic.awk ++ * This file has been generated with lantiq_ram_extract_magic.awk script. + * -+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#define MC_DC00_VALUE 0x1B1B @@ -108,14 +113,16 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define MC_DC44_VALUE 0x0 +#define MC_DC45_VALUE 0x500 +#define MC_DC46_VALUE 0x0 +diff --git a/board/gigaset/sx76x/sx76x.c b/board/gigaset/sx76x/sx76x.c +new file mode 100644 +index 0000000..71996a1 --- /dev/null +++ b/board/gigaset/sx76x/sx76x.c -@@ -0,0 +1,66 @@ +@@ -0,0 +1,65 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. -+ * + * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> @@ -177,32 +184,36 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + + return switch_device_register(&adm6996i_dev); +} +diff --git a/boards.cfg b/boards.cfg +index ea5c4f9..2163cdb 100644 --- a/boards.cfg +++ b/boards.cfg -@@ -447,6 +447,8 @@ pb1000 mips - easy50712_nor mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_NOR - easy50712_norspl mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_NORSPL - easy50712_ram mips mips32 easy50712 lantiq danube easy50712:SYS_BOOT_RAM -+gigasx76x_nor mips mips32 sx76x gigaset danube sx76x:SYS_BOOT_NOR -+gigasx76x_ram mips mips32 sx76x gigaset danube sx76x:SYS_BOOT_RAM - incaip mips mips32 incaip - incaip - incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000 - incaip_133MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=133000000 +@@ -510,6 +510,8 @@ Active mips mips32 danube arcadyan arv7518pw + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com> + Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com> ++Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube gigaset sx76x gigasx76x_ram sx76x:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/include/configs/sx76x.h b/include/configs/sx76x.h +new file mode 100644 +index 0000000..236851e --- /dev/null +++ b/include/configs/sx76x.h -@@ -0,0 +1,71 @@ +@@ -0,0 +1,59 @@ +/* -+ * This file is released under the terms of GPL v2 and any later version. -+ * See the file COPYING in the root directory of the source tree for details. ++ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> + * -+ * Copyright (C) 2011 Luka Perkov <luka@openwrt.org> ++ * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MACH_TYPE "GIGASX76X" -+#define CONFIG_IDENT_STRING " sx76x" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE +#define CONFIG_BOARD_NAME "Gigaset sx76x" + +/* Configure SoC */ @@ -221,13 +232,12 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (256 * 1024) -+#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_ENV_SECT_SIZE (64 * 1024) +#else +#define CONFIG_ENV_IS_NOWHERE -+#define CONFIG_ENV_SIZE (2 * 1024) +#endif + ++#define CONFIG_ENV_SIZE (8 * 1024) +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +/* Console */ @@ -236,22 +246,12 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +#define CONFIG_CONSOLE_ASC 1 +#define CONFIG_CONSOLE_DEV "ttyLTQ1" + -+/* Commands */ -+#define CONFIG_CMD_PING -+ +/* Pull in default board configs for Lantiq XWAY Danube */ +#include <asm/lantiq/config.h> +#include <asm/arch/config.h> + -+/* Compression */ -+#define CONFIG_LZMA -+ -+/* Auto boot */ -+#define CONFIG_BOOTDELAY 2 -+ -+/* Environment configuration */ -+#define CONFIG_BOOTCOMMAND \ -+ "run addeth; bootm ${kernel_addr}" ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" + +#define CONFIG_ENV_UPDATE_UBOOT_NOR \ + "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" @@ -262,3 +262,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + "kernel_addr=0xB0040000\0" + +#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0031-MIPS-add-board-support-for-ZTE-ZXHN-H367N.patch b/package/boot/uboot-lantiq/patches/0031-MIPS-add-board-support-for-ZTE-ZXHN-H367N.patch new file mode 100644 index 0000000..bd1bf58 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0031-MIPS-add-board-support-for-ZTE-ZXHN-H367N.patch @@ -0,0 +1,327 @@ +From 0597056e2ba19ea783ef5c3d14c75c4722740e48 Mon Sep 17 00:00:00 2001 +From: Luka Perkov <luka@openwrt.org> +Date: Sun, 10 Mar 2013 17:59:56 +0100 +Subject: MIPS: add board support for ZTE ZXHN H367N + +Signed-off-by: Luka Perkov <luka@openwrt.org> + +diff --git a/board/zte/zxhnh367n/Makefile b/board/zte/zxhnh367n/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/zte/zxhnh367n/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/zte/zxhnh367n/config.mk b/board/zte/zxhnh367n/config.mk +new file mode 100644 +index 0000000..9d33739 +--- /dev/null ++++ b/board/zte/zxhnh367n/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/zte/zxhnh367n/ddr_settings.h b/board/zte/zxhnh367n/ddr_settings.h +new file mode 100644 +index 0000000..b3f81de +--- /dev/null ++++ b/board/zte/zxhnh367n/ddr_settings.h +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * The values have been extracted from original ZTE U-Boot. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000101 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x100 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x0 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000401 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401B04 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x0 ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1D445D ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x141F04 ++#define MC_CCR40_VALUE 0x142704 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x0 ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7800301 ++#define MC_CCR58_VALUE 0x7800301 ++#define MC_CCR59_VALUE 0x7800301 ++#define MC_CCR60_VALUE 0x7800301 ++#define MC_CCR61_VALUE 0x4 +diff --git a/board/zte/zxhnh367n/zxhnh367n.c b/board/zte/zxhnh367n/zxhnh367n.c +new file mode 100644 +index 0000000..f64f105 +--- /dev/null ++++ b/board/zte/zxhnh367n/zxhnh367n.c +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/chipid.h> ++#include <asm/lantiq/cpu.h> ++#include <asm/arch/gphy.h> ++ ++#if defined(CONFIG_SPL_BUILD) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 0 ++#elif defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++static void gpio_init(void) ++{ ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* GPIO 3.0 as input for NAND Ready Busy */ ++ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); ++ /* GPIO 3.1 as output for NAND Read */ ++ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ ++ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC1: unused */ ++ { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* GMAC2: internal GPHY0 with 10/100 firmware for LAN port 1 */ ++ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++ /* GMAC3: internal GPHY0 with 10/100 firmware for LAN port 2 */ ++ { 3, 0x12, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++ /* GMAC4: internal GPHY1 with 10/100 firmware for LAN port 3 */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++ /* GMAC5: internal GPHY1 with 10/100 firmware for LAN port 4 */ ++ { 5, 0x14, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_MII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_addr = 0x80FF0000; ++ ++ ltq_gphy_phy22f_a2x_load(fw_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_addr); ++ ltq_rcu_gphy_boot(1, fw_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} +diff --git a/boards.cfg b/boards.cfg +index 2163cdb..4b18a26 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -527,6 +527,9 @@ Active mips mips32 vrx200 lantiq easy80920 + Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> ++Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_nandspl zxhnh367n:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org> ++Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_ram zxhnh367n:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_zte zxhnh367n:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org> + Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - + Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - + Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com> +diff --git a/include/configs/zxhnh367n.h b/include/configs/zxhnh367n.h +new file mode 100644 +index 0000000..55d2e2a +--- /dev/null ++++ b/include/configs/zxhnh367n.h +@@ -0,0 +1,72 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ZXHN H367N" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "ZTE ZXHN H367N" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a NAND flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++#define CONFIG_SYS_NAND_PAGE_COUNT 128 ++#define CONFIG_SYS_NAND_PAGE_SIZE 2048 ++#define CONFIG_SYS_NAND_OOBSIZE 64 ++#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024) ++#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS ++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 ++ ++#define CONFIG_SYS_DRAM_PROBE ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NANDSPL) ++#define CONFIG_ENV_IS_IN_NAND ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (256 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++#if defined(CONFIG_SYS_BOOT_ZTE) ++#define CONFIG_SYS_TEXT_BASE 0x80800000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NAND \ ++ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NAND ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0032-MIPS-add-board-support-for-ZTE-ZXV10-H201L.patch b/package/boot/uboot-lantiq/patches/0032-MIPS-add-board-support-for-ZTE-ZXV10-H201L.patch new file mode 100644 index 0000000..26a7935 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0032-MIPS-add-board-support-for-ZTE-ZXV10-H201L.patch @@ -0,0 +1,271 @@ +From 2473526cf879ead429c6aa1fb7fb77ed3407baaa Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 9 Dec 2012 17:35:09 +0100 +Subject: MIPS: add board support for ZTE ZXV10 H201L + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/board/zte/zxv10h201l/Makefile b/board/zte/zxv10h201l/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/zte/zxv10h201l/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/zte/zxv10h201l/config.mk b/board/zte/zxv10h201l/config.mk +new file mode 100644 +index 0000000..9d33739 +--- /dev/null ++++ b/board/zte/zxv10h201l/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/zte/zxv10h201l/ddr_settings.h b/board/zte/zxv10h201l/ddr_settings.h +new file mode 100644 +index 0000000..8814957 +--- /dev/null ++++ b/board/zte/zxv10h201l/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * The values have been extracted from original ZTE U-Boot. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x307 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x103 ++#define MC_DC09_VALUE 0x80B ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xE02 ++#define MC_DC12_VALUE 0x2C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x100 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xF ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA04 ++#define MC_DC21_VALUE 0x1600 ++#define MC_DC22_VALUE 0x1616 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5D ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x5FB ++#define MC_DC29_VALUE 0x35DF ++#define MC_DC30_VALUE 0x99E9 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x600 ++#define MC_DC46_VALUE 0x0 +diff --git a/board/zte/zxv10h201l/zxv10h201l.c b/board/zte/zxv10h201l/zxv10h201l.c +new file mode 100644 +index 0000000..8218a9d +--- /dev/null ++++ b/board/zte/zxv10h201l/zxv10h201l.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <switch.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/chipid.h> ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: REALTEK RTL8306 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device rtl8306_dev = { ++ .name = "rtl8306", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&rtl8306_dev); ++} +diff --git a/boards.cfg b/boards.cfg +index 4b18a26..4362856 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -496,6 +496,9 @@ Active mips mips32 - micronas vct + Active mips mips32 - micronas vct vct_premium_onenand vct:VCT_PREMIUM,VCT_ONENAND - + Active mips mips32 - micronas vct vct_premium_onenand_small vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE - + Active mips mips32 - micronas vct vct_premium_small vct:VCT_PREMIUM,VCT_SMALL_IMAGE - ++Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org> + Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se> +diff --git a/include/configs/zxv10h201l.h b/include/configs/zxv10h201l.h +new file mode 100644 +index 0000000..bfe116d +--- /dev/null ++++ b/include/configs/zxv10h201l.h +@@ -0,0 +1,77 @@ ++/* ++ * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ZXV10 H201L" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "ZTE ZXV10 H201L" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_RTL8306 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#elif defined(CONFIG_SYS_BOOT_NORSPL) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (128 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++#if defined(CONFIG_SYS_BOOT_ZTE) ++#define CONFIG_SYS_TEXT_BASE 0x80800000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++#if defined(CONFIG_SYS_BOOT_ZTE) ++#define CONFIG_SYS_TEXT_BASE 0x80800000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#endif ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0033-MIPS-add-board-support-for-ZyXEL-P-661HNU-Fx.patch b/package/boot/uboot-lantiq/patches/0033-MIPS-add-board-support-for-ZyXEL-P-661HNU-Fx.patch new file mode 100644 index 0000000..ffe9b9f --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0033-MIPS-add-board-support-for-ZyXEL-P-661HNU-Fx.patch @@ -0,0 +1,324 @@ +From a18f994f373db4467a4680f83ead997c8122908e Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Wed, 22 May 2013 17:48:08 +0200 +Subject: MIPS: add board support for ZyXEL P-661HNU-Fx + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/board/zyxel/p661hnufx/Makefile b/board/zyxel/p661hnufx/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/zyxel/p661hnufx/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/zyxel/p661hnufx/config.mk b/board/zyxel/p661hnufx/config.mk +new file mode 100644 +index 0000000..9d33739 +--- /dev/null ++++ b/board/zyxel/p661hnufx/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/zyxel/p661hnufx/ddr_settings.h b/board/zyxel/p661hnufx/ddr_settings.h +new file mode 100644 +index 0000000..83693b8 +--- /dev/null ++++ b/board/zyxel/p661hnufx/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * The values have been extracted from original ZyXEL U-Boot. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x307 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x103 ++#define MC_DC09_VALUE 0x80B ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xE02 ++#define MC_DC12_VALUE 0x2C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x100 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xF ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA04 ++#define MC_DC21_VALUE 0x1600 ++#define MC_DC22_VALUE 0x1616 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5D ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x5FB ++#define MC_DC29_VALUE 0x35DF ++#define MC_DC30_VALUE 0x99E9 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x600 ++#define MC_DC46_VALUE 0x0 +diff --git a/board/zyxel/p661hnufx/p661hnufx.c b/board/zyxel/p661hnufx/p661hnufx.c +new file mode 100644 +index 0000000..dfaca51 +--- /dev/null ++++ b/board/zyxel/p661hnufx/p661hnufx.c +@@ -0,0 +1,102 @@ ++/* ++ * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <switch.h> ++#include <spi.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/chipid.h> ++ ++static void gpio_init(void) ++{ ++ /* SPI CS 0.4 to serial flash */ ++ gpio_direction_output(10, 1); ++} ++ ++int board_early_init_f(void) ++{ ++ gpio_init(); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Lantiq Tantos switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++ /* MAC1: unused */ ++ { 1, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device psb697x_dev = { ++ .name = "psb697x", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ printf("%s\n", __func__); ++ ++#if 0 ++ ltq_reset_once(LTQ_RESET_HARD, 200000); ++ __udelay(50000); ++#endif ++ ++ return switch_device_register(&psb697x_dev); ++} ++ ++int spi_cs_is_valid(unsigned int bus, unsigned int cs) ++{ ++ if (bus) ++ return 0; ++ ++ if (cs == 4) ++ return 1; ++ ++ return 0; ++} ++ ++void spi_cs_activate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 0); ++ break; ++ default: ++ break; ++ } ++} ++ ++void spi_cs_deactivate(struct spi_slave *slave) ++{ ++ switch (slave->cs) { ++ case 4: ++ gpio_set_value(10, 1); ++ break; ++ default: ++ break; ++ } ++} +diff --git a/boards.cfg b/boards.cfg +index 4362856..e505203 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -499,6 +499,9 @@ Active mips mips32 - micronas vct + Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> + Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zyxel p661hnufx p661hnufx_ram p661hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zyxel p661hnufx p661hnufx_sfspl p661hnufx:SYS_BOOT_SFSPL Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zyxel p661hnufx p661hnufx_zyxel p661hnufx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org> + Active mips mips32 au1x00 - dbau1x00 dbau1000 dbau1x00:DBAU1000 Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - dbau1x00 dbau1100 dbau1x00:DBAU1100 Thomas Lange <thomas@corelatus.se> + Active mips mips32 au1x00 - dbau1x00 dbau1500 dbau1x00:DBAU1500 Thomas Lange <thomas@corelatus.se> +diff --git a/include/configs/p661hnufx.h b/include/configs/p661hnufx.h +new file mode 100644 +index 0000000..85e3e1e +--- /dev/null ++++ b/include/configs/p661hnufx.h +@@ -0,0 +1,79 @@ ++/* ++ * Copyright (C) 2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "P-661HNU-Fx" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "ZyXEL P-661HNU-Fx" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_SPI_FLASH ++#define CONFIG_SPI_FLASH_MACRONIX /* Supports Macronix serial flash */ ++#define CONFIG_SPI_FLASH_4BYTE_MODE ++ ++#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++#define CONFIG_SPL_SPI_BUS 0 ++#define CONFIG_SPL_SPI_CS 4 ++#define CONFIG_SPL_SPI_MAX_HZ 25000000 ++#define CONFIG_SPL_SPI_MODE 0 ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_PSB697X ++ ++/* Environment */ ++#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS ++#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS ++#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ ++#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE ++ ++#if defined(CONFIG_SYS_BOOT_SFSPL) ++#define CONFIG_ENV_IS_IN_SPI_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (512 * 1024) ++#define CONFIG_ENV_SECT_SIZE (256 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++#if defined(CONFIG_SYS_BOOT_ZYXEL) ++#define CONFIG_SYS_TEXT_BASE 0x80800000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_SF \ ++ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_SF ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0034-MIPS-add-board-support-for-ZyXEL-P-2601HN-Fx.patch b/package/boot/uboot-lantiq/patches/0034-MIPS-add-board-support-for-ZyXEL-P-2601HN-Fx.patch new file mode 100644 index 0000000..0cbcd6c --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0034-MIPS-add-board-support-for-ZyXEL-P-2601HN-Fx.patch @@ -0,0 +1,262 @@ +From 4bfa74583bc938d2da41f255f22baa1845332893 Mon Sep 17 00:00:00 2001 +From: Luka Perkov <luka@openwrt.org> +Date: Tue, 12 Mar 2013 01:42:46 +0100 +Subject: MIPS: add board support for ZyXEL P-2601HN-Fx + +Signed-off-by: Luka Perkov <luka@openwrt.org> + +diff --git a/board/zyxel/p2601hnfx/Makefile b/board/zyxel/p2601hnfx/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/zyxel/p2601hnfx/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/zyxel/p2601hnfx/config.mk b/board/zyxel/p2601hnfx/config.mk +new file mode 100644 +index 0000000..9d33739 +--- /dev/null ++++ b/board/zyxel/p2601hnfx/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/zyxel/p2601hnfx/ddr_settings.h b/board/zyxel/p2601hnfx/ddr_settings.h +new file mode 100644 +index 0000000..92af4fa +--- /dev/null ++++ b/board/zyxel/p2601hnfx/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * The values have been extracted from original ZyXEL U-Boot. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x306 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x144 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1900 ++#define MC_DC22_VALUE 0x1919 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x66 ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x50A ++#define MC_DC29_VALUE 0x2D65 ++#define MC_DC30_VALUE 0x81B1 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x600 ++#define MC_DC46_VALUE 0x0 +diff --git a/board/zyxel/p2601hnfx/p2601hnfx.c b/board/zyxel/p2601hnfx/p2601hnfx.c +new file mode 100644 +index 0000000..6a69af9 +--- /dev/null ++++ b/board/zyxel/p2601hnfx/p2601hnfx.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <switch.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/chipid.h> ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: REALTEK RTL8306 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device rtl8306_dev = { ++ .name = "rtl8306", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&rtl8306_dev); ++} +diff --git a/boards.cfg b/boards.cfg +index e505203..45c2aa0 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -499,6 +499,10 @@ Active mips mips32 - micronas vct + Active mips mips32 arx100 zte zxv10h201l zxv10h201l_nor zxv10h201l:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> + Active mips mips32 arx100 zte zxv10h201l zxv10h201l_ram zxv10h201l:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 arx100 zte zxv10h201l zxv10h201l_zte zxv10h201l:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_nor p2601hnfx:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_norspl p2601hnfx:SYS_BOOT_NORSPL Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_ram p2601hnfx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 arx100 zyxel p2601hnfx p2601hnfx_zyxel p2601hnfx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org> + Active mips mips32 arx100 zyxel p661hnufx p661hnufx_ram p661hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 arx100 zyxel p661hnufx p661hnufx_sfspl p661hnufx:SYS_BOOT_SFSPL Luka Perkov <luka@openwrt.org> + Active mips mips32 arx100 zyxel p661hnufx p661hnufx_zyxel p661hnufx:SYS_BOOT_ZYXEL Luka Perkov <luka@openwrt.org> +diff --git a/include/configs/p2601hnfx.h b/include/configs/p2601hnfx.h +new file mode 100644 +index 0000000..5cba30f +--- /dev/null ++++ b/include/configs/p2601hnfx.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "P-2601HN-Fx" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "ZyXEL P-2601HN-Fx" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#elif defined(CONFIG_SYS_BOOT_NORSPL) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (128 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++#if defined(CONFIG_SYS_BOOT_ZYXEL) ++#define CONFIG_SYS_TEXT_BASE 0x80800000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch b/package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch new file mode 100644 index 0000000..c68a6ae --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0035-MIPS-add-board-support-for-ZyXEL-P-2812HNU-Fx.patch @@ -0,0 +1,321 @@ +From 3f7be04a148d23cdb5fd320e0e2923983f8bd1f4 Mon Sep 17 00:00:00 2001 +From: Luka Perkov <luka@openwrt.org> +Date: Tue, 6 Aug 2013 22:51:00 +0200 +Subject: MIPS: add board support for ZyXEL P-2812HNU-Fx + +Signed-off-by: Luka Perkov <luka@openwrt.org> + +diff --git a/board/zyxel/p2812hnufx/Makefile b/board/zyxel/p2812hnufx/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/zyxel/p2812hnufx/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/zyxel/p2812hnufx/config.mk b/board/zyxel/p2812hnufx/config.mk +new file mode 100644 +index 0000000..9d33739 +--- /dev/null ++++ b/board/zyxel/p2812hnufx/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/zyxel/p2812hnufx/ddr_settings.h b/board/zyxel/p2812hnufx/ddr_settings.h +new file mode 100644 +index 0000000..128c42e +--- /dev/null ++++ b/board/zyxel/p2812hnufx/ddr_settings.h +@@ -0,0 +1,70 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * The values have been extracted from original ZyXEL U-Boot. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000100 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x101 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x0 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000300 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401B04 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x0 ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1D445D ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x141F04 ++#define MC_CCR40_VALUE 0x142704 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x0 ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7800301 ++#define MC_CCR58_VALUE 0x7800301 ++#define MC_CCR59_VALUE 0x7800301 ++#define MC_CCR60_VALUE 0x7800301 ++#define MC_CCR61_VALUE 0x4 +diff --git a/board/zyxel/p2812hnufx/p2812hnufx.c b/board/zyxel/p2812hnufx/p2812hnufx.c +new file mode 100644 +index 0000000..cd2f819 +--- /dev/null ++++ b/board/zyxel/p2812hnufx/p2812hnufx.c +@@ -0,0 +1,97 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/chipid.h> ++#include <asm/lantiq/cpu.h> ++#include <asm/arch/gphy.h> ++ ++#if defined(CONFIG_SPL_BUILD) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 0 ++#elif defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++static void gpio_init(void) ++{ ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* GPIO 3.0 as input for NAND Ready Busy */ ++ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); ++ /* GPIO 3.1 as output for NAND Read */ ++ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */ ++ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */ ++ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */ ++ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC3: unused */ ++ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE }, ++ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */ ++ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_addr = 0x80FF0000; ++ ++ ltq_gphy_phy11g_a1x_load(fw_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_addr); ++ ltq_rcu_gphy_boot(1, fw_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} +diff --git a/boards.cfg b/boards.cfg +index 45c2aa0..0cbf756 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -540,6 +540,8 @@ Active mips mips32 vrx200 lantiq easy80920 + Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_nandspl zxhnh367n:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org> + Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_ram zxhnh367n:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 vrx200 zte zxhnh367n zxhnh367n_zte zxhnh367n:SYS_BOOT_ZTE Luka Perkov <luka@openwrt.org> ++Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_nandspl p2812hnufx:SYS_BOOT_NANDSPL Luka Perkov <luka@openwrt.org> ++Active mips mips32 vrx200 zyxel p2812hnufx p2812hnufx_ram p2812hnufx:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN - + Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN - + Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com> +diff --git a/include/configs/p2812hnufx.h b/include/configs/p2812hnufx.h +new file mode 100644 +index 0000000..6806eb1 +--- /dev/null ++++ b/include/configs/p2812hnufx.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "P-2812HNU-Fx" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "ZyXEL P-2812HNU-Fx" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH /* Have a K9F1G08U0D NAND flash */ ++ ++#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */ ++#define CONFIG_LTQ_SPL_COMP_LZO /* Compress SPL with LZO */ ++#define CONFIG_LTQ_SPL_CONSOLE /* Enable SPL console */ ++ ++#define CONFIG_SYS_NAND_PAGE_COUNT 64 ++#define CONFIG_SYS_NAND_PAGE_SIZE 2048 ++#define CONFIG_SYS_NAND_OOBSIZE 64 ++#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) ++#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS ++#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000 ++ ++#define CONFIG_SYS_DRAM_PROBE ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NANDSPL) ++#define CONFIG_ENV_IS_IN_NAND ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NAND \ ++ "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NAND ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0036-MIPS-add-board-support-for-Arcadyan-Easybox-904.patch b/package/boot/uboot-lantiq/patches/0036-MIPS-add-board-support-for-Arcadyan-Easybox-904.patch new file mode 100644 index 0000000..fbb31e5 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0036-MIPS-add-board-support-for-Arcadyan-Easybox-904.patch @@ -0,0 +1,297 @@ +From 60856fa8f9866f292df740ea98752a70738eb59a Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Fri, 9 Aug 2013 18:11:07 +0200 +Subject: MIPS: add board support for Arcadyan Easybox 904 + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/board/arcadyan/easybox904/Makefile b/board/arcadyan/easybox904/Makefile +new file mode 100644 +index 0000000..0380dea +--- /dev/null ++++ b/board/arcadyan/easybox904/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/arcadyan/easybox904/config.mk b/board/arcadyan/easybox904/config.mk +new file mode 100644 +index 0000000..9d8953b +--- /dev/null ++++ b/board/arcadyan/easybox904/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/arcadyan/easybox904/ddr_settings.h b/board/arcadyan/easybox904/ddr_settings.h +new file mode 100644 +index 0000000..24541bc +--- /dev/null ++++ b/board/arcadyan/easybox904/ddr_settings.h +@@ -0,0 +1,68 @@ ++/* ++ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_CCR00_VALUE 0x101 ++#define MC_CCR01_VALUE 0x1000100 ++#define MC_CCR02_VALUE 0x1010000 ++#define MC_CCR03_VALUE 0x101 ++#define MC_CCR04_VALUE 0x1000000 ++#define MC_CCR05_VALUE 0x1000101 ++#define MC_CCR06_VALUE 0x1000100 ++#define MC_CCR07_VALUE 0x1010000 ++#define MC_CCR08_VALUE 0x1000101 ++#define MC_CCR09_VALUE 0x1000000 ++#define MC_CCR10_VALUE 0x2000100 ++#define MC_CCR11_VALUE 0x2000300 ++#define MC_CCR12_VALUE 0x30000 ++#define MC_CCR13_VALUE 0x202 ++#define MC_CCR14_VALUE 0x7080A0F ++#define MC_CCR15_VALUE 0x2040F ++#define MC_CCR16_VALUE 0x40000 ++#define MC_CCR17_VALUE 0x70102 ++#define MC_CCR18_VALUE 0x4020002 ++#define MC_CCR19_VALUE 0x30302 ++#define MC_CCR20_VALUE 0x8000700 ++#define MC_CCR21_VALUE 0x40F020A ++#define MC_CCR22_VALUE 0x0 ++#define MC_CCR23_VALUE 0xC020000 ++#define MC_CCR24_VALUE 0x4401503 ++#define MC_CCR25_VALUE 0x0 ++#define MC_CCR26_VALUE 0x0 ++#define MC_CCR27_VALUE 0x6420000 ++#define MC_CCR28_VALUE 0x0 ++#define MC_CCR29_VALUE 0x0 ++#define MC_CCR30_VALUE 0x798 ++#define MC_CCR31_VALUE 0x0 ++#define MC_CCR32_VALUE 0x0 ++#define MC_CCR33_VALUE 0x650000 ++#define MC_CCR34_VALUE 0x200C8 ++#define MC_CCR35_VALUE 0x1536B0 ++#define MC_CCR36_VALUE 0xC8 ++#define MC_CCR37_VALUE 0xC351 ++#define MC_CCR38_VALUE 0x0 ++#define MC_CCR39_VALUE 0x142404 ++#define MC_CCR40_VALUE 0x142604 ++#define MC_CCR41_VALUE 0x141B42 ++#define MC_CCR42_VALUE 0x141B42 ++#define MC_CCR43_VALUE 0x566504 ++#define MC_CCR44_VALUE 0x566504 ++#define MC_CCR45_VALUE 0x565F17 ++#define MC_CCR46_VALUE 0x565F17 ++#define MC_CCR47_VALUE 0x0 ++#define MC_CCR48_VALUE 0x0 ++#define MC_CCR49_VALUE 0x0 ++#define MC_CCR50_VALUE 0x0 ++#define MC_CCR51_VALUE 0x0 ++#define MC_CCR52_VALUE 0x133 ++#define MC_CCR53_VALUE 0xF3014B27 ++#define MC_CCR54_VALUE 0xF3014B27 ++#define MC_CCR55_VALUE 0xF3014B27 ++#define MC_CCR56_VALUE 0xF3014B27 ++#define MC_CCR57_VALUE 0x7C00301 ++#define MC_CCR58_VALUE 0x7C00301 ++#define MC_CCR59_VALUE 0x7C00301 ++#define MC_CCR60_VALUE 0x7C00301 ++#define MC_CCR61_VALUE 0x4 +diff --git a/board/arcadyan/easybox904/easybox904.c b/board/arcadyan/easybox904/easybox904.c +new file mode 100644 +index 0000000..4dbe044 +--- /dev/null ++++ b/board/arcadyan/easybox904/easybox904.c +@@ -0,0 +1,98 @@ ++/* ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <spi.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/chipid.h> ++#include <asm/lantiq/cpu.h> ++#include <asm/arch/gphy.h> ++ ++#if defined(CONFIG_SPL_BUILD) ++#define do_gpio_init 1 ++#define do_pll_init 1 ++#define do_dcdc_init 0 ++#elif defined(CONFIG_SYS_BOOT_RAM) ++#define do_gpio_init 1 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#else ++#define do_gpio_init 0 ++#define do_pll_init 0 ++#define do_dcdc_init 1 ++#endif ++ ++static inline void gpio_init(void) ++{ ++ /* EBU.FL_CS1 as output for NAND CE */ ++ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A23 as output for NAND CLE */ ++ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* EBU.FL_A24 as output for NAND ALE */ ++ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++ /* GPIO 3.0 as input for NAND Ready Busy */ ++ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN); ++ /* GPIO 3.1 as output for NAND Read */ ++ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT); ++} ++ ++int board_early_init_f(void) ++{ ++ if (do_gpio_init) ++ gpio_init(); ++ ++ if (do_pll_init) ++ ltq_pll_init(); ++ ++ if (do_dcdc_init) ++ ltq_dcdc_init(0x7F); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* GMAC0: ??? */ ++ { 0, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE }, ++ /* GMAC1: ??? */ ++ { 1, 0x1, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE }, ++ /* GMAC2: ??? */ ++ { 2, 0x11, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE }, ++ /* GMAC3: unused */ ++ { 3, 0x0, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE }, ++ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for WANoE port */ ++ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII }, ++ /* GMAC5: ??? */ ++ { 5, 0x5, LTQ_ETH_PORT_NONE, LTQ_ETH_PORT_NONE }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t * bis) ++{ ++ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0; ++ const ulong fw_ge_addr = 0x80FE0000; ++ ++ ltq_gphy_phy11g_a2x_load(fw_ge_addr); ++ ++ ltq_cgu_gphy_clk_src(clk); ++ ++ ltq_rcu_gphy_boot(0, fw_ge_addr); ++ ltq_rcu_gphy_boot(1, fw_ge_addr); ++ ++ return ltq_eth_initialize(ð_board_config); ++} +diff --git a/boards.cfg b/boards.cfg +index 0cbf756..f10be39 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -529,6 +529,7 @@ Active mips mips32 incaip - incaip + Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de> + Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de> ++Active mips mips32 vrx200 arcadyan easybox904 easybox904_ram easybox904:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 avm fb3370 fb3370_eva fb3370:SYS_BOOT_EVA Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 avm fb3370 fb3370_ram fb3370:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + Active mips mips32 vrx200 avm fb3370 fb3370_sfspl fb3370:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +diff --git a/include/configs/easybox904.h b/include/configs/easybox904.h +new file mode 100644 +index 0000000..c892d77 +--- /dev/null ++++ b/include/configs/easybox904.h +@@ -0,0 +1,45 @@ ++/* ++ * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "EASYBOX904" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan EasyBox 904" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NAND_FLASH ++ ++#define CONFIG_SYS_DRAM_PROBE ++ ++/* Environment */ ++#define CONFIG_ENV_IS_NOWHERE ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY VRX200 */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch b/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch new file mode 100644 index 0000000..31b6b76 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0037-MIPS-add-board-support-for-Arcadyan-ARV752DPW.patch @@ -0,0 +1,262 @@ +From fbdbf2ddf2b34d675d53de679c179788b0604c1a Mon Sep 17 00:00:00 2001 +From: Oliver Muth <dr.o.muth@gmx.de> +Date: Sat, 12 Oct 2013 16:49:53 +0200 +Subject: MIPS: add board support for Arcadyan ARV752DPW + +Signed-off-by: Oliver Muth <dr.o.muth@gmx.de> +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/board/arcadyan/arv752dpw/Makefile b/board/arcadyan/arv752dpw/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/arcadyan/arv752dpw/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/arcadyan/arv752dpw/arv752dpw.c b/board/arcadyan/arv752dpw/arv752dpw.c +new file mode 100644 +index 0000000..d555904 +--- /dev/null ++++ b/board/arcadyan/arv752dpw/arv752dpw.c +@@ -0,0 +1,51 @@ ++/* ++ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> ++ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <switch.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/chipid.h> ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Realtek rtl8306 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++static struct switch_device rtl8306_dev = { ++ .name = "rtl8306", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&rtl8306_dev); ++} +diff --git a/board/arcadyan/arv752dpw/config.mk b/board/arcadyan/arv752dpw/config.mk +new file mode 100644 +index 0000000..9d8953b +--- /dev/null ++++ b/board/arcadyan/arv752dpw/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/arcadyan/arv752dpw/ddr_settings.h b/board/arcadyan/arv752dpw/ddr_settings.h +new file mode 100644 +index 0000000..a226322 +--- /dev/null ++++ b/board/arcadyan/arv752dpw/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x134 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1400 ++#define MC_DC22_VALUE 0x1414 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5B ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +diff --git a/boards.cfg b/boards.cfg +index f10be39..79cba2d 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -518,6 +518,9 @@ Active mips mips32 danube arcadyan arv4519pw + Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN - ++Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR - ++Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM - + Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com> + Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com> + Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> +diff --git a/include/configs/arv752dpw.h b/include/configs/arv752dpw.h +new file mode 100644 +index 0000000..f6d6092 +--- /dev/null ++++ b/include/configs/arv752dpw.h +@@ -0,0 +1,67 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV752DPW" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_RTL8206 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch b/package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch new file mode 100644 index 0000000..9e7b739 --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch @@ -0,0 +1,264 @@ +From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001 +From: Oliver Muth <dr.o.muth@gmx.de> +Date: Sat, 12 Oct 2013 16:49:53 +0200 +Subject: MIPS: add board support for Arcadyan ARV752DPW22 + +Signed-off-by: Oliver Muth <dr.o.muth@gmx.de> +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/board/arcadyan/arv752dpw22/Makefile b/board/arcadyan/arv752dpw22/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/arcadyan/arv752dpw22/arv752dpw22.c b/board/arcadyan/arv752dpw22/arv752dpw22.c +new file mode 100644 +index 0000000..9b2d89f +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/arv752dpw22.c +@@ -0,0 +1,52 @@ ++/* ++ * Copyright (C) 2012 Luka Perkov <luka@openwrt.org> ++ * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <switch.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/chipid.h> ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: Atheros ar8216 switch */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device ar8216_dev = { ++ .name = "ar8216", ++ .cpu_port = 0, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ return switch_device_register(&ar8216_dev); ++} +diff --git a/board/arcadyan/arv752dpw22/config.mk b/board/arcadyan/arv752dpw22/config.mk +new file mode 100644 +index 0000000..9d8953b +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/arcadyan/arv752dpw22/ddr_settings.h b/board/arcadyan/arv752dpw22/ddr_settings.h +new file mode 100644 +index 0000000..a226322 +--- /dev/null ++++ b/board/arcadyan/arv752dpw22/ddr_settings.h +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org> ++ * ++ * This file has been generated with lantiq_ram_extract_magic.awk script. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x134 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA03 ++#define MC_DC21_VALUE 0x1400 ++#define MC_DC22_VALUE 0x1414 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x5B ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +diff --git a/boards.cfg b/boards.cfg +index 79cba2d..287f974 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -521,6 +521,9 @@ Active mips mips32 danube arcadyan arv7518pw + Active mips mips32 danube arcadyan arv752dpw arv752dpw_brn arv752dpw:SYS_BOOT_BRN - + Active mips mips32 danube arcadyan arv752dpw arv752dpw_nor arv752dpw:SYS_BOOT_NOR - + Active mips mips32 danube arcadyan arv752dpw arv752dpw_ram arv752dpw:SYS_BOOT_RAM - ++Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_brn arv752dpw22:SYS_BOOT_BRN - ++Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_nor arv752dpw22:SYS_BOOT_NOR - ++Active mips mips32 danube arcadyan arv752dpw22 arv752dpw22_ram arv752dpw22:SYS_BOOT_RAM - + Active mips mips32 danube audiocodes acmp252 acmp252_nor acmp252:SYS_BOOT_NOR Daniel Golle <daniel.golle@gmail.com> + Active mips mips32 danube audiocodes acmp252 acmp252_ram acmp252:SYS_BOOT_RAM Daniel Golle <daniel.golle@gmail.com> + Active mips mips32 danube gigaset sx76x gigasx76x_nor sx76x:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> +diff --git a/include/configs/arv752dpw22.h b/include/configs/arv752dpw22.h +new file mode 100644 +index 0000000..f17aa70 +--- /dev/null ++++ b/include/configs/arv752dpw22.h +@@ -0,0 +1,68 @@ ++/* ++ * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV752DPW22" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV752DPW22" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_AR8216 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (192 * 1024) ++#define CONFIG_ENV_SECT_SIZE (64 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Burnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0040000\0" ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch b/package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch new file mode 100644 index 0000000..de39b4f --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch @@ -0,0 +1,289 @@ +From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001 +From: Matti Laakso <malaakso@elisanet.fi> +Date: Sat, 2 Mar 2013 23:34:00 +0100 +Subject: MIPS: add board support for Arcadyan ARV7510 + +Signed-off-by: Matti Laakso <malaakso@elisanet.fi> +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/board/arcadyan/arv7510pw/Makefile b/board/arcadyan/arv7510pw/Makefile +new file mode 100644 +index 0000000..3a547c2 +--- /dev/null ++++ b/board/arcadyan/arv7510pw/Makefile +@@ -0,0 +1,27 @@ ++# ++# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++include $(TOPDIR)/config.mk ++ ++LIB = $(obj)lib$(BOARD).o ++ ++COBJS = $(BOARD).o ++ ++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) ++OBJS := $(addprefix $(obj),$(COBJS)) ++SOBJS := $(addprefix $(obj),$(SOBJS)) ++ ++$(LIB): $(obj).depend $(OBJS) $(SOBJS) ++ $(call cmd_link_o_target, $(OBJS) $(SOBJS)) ++ ++######################################################################### ++ ++# defines $(obj).depend target ++include $(SRCTREE)/rules.mk ++ ++sinclude $(obj).depend ++ ++######################################################################### +diff --git a/board/arcadyan/arv7510pw/arv7510pw.c b/board/arcadyan/arv7510pw/arv7510pw.c +new file mode 100644 +index 0000000..6880b4c +--- /dev/null ++++ b/board/arcadyan/arv7510pw/arv7510pw.c +@@ -0,0 +1,72 @@ ++/* ++ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <switch.h> ++#include <asm/gpio.h> ++#include <asm/lantiq/eth.h> ++#include <asm/lantiq/reset.h> ++#include <asm/lantiq/chipid.h> ++#include <asm/lantiq/cpu.h> ++ ++static void gpio_init(void) ++{ ++ /* Initialize SSIO GPIOs */ ++ gpio_set_altfunc(4, 1, 0, 1); ++ gpio_set_altfunc(5, 1, 0, 1); ++ gpio_set_altfunc(6, 1, 0, 1); ++ ltq_gpio_init(); ++ ++ /* Power led on */ ++ gpio_direction_output(76, 1); ++} ++ ++int board_early_init_f(void) ++{ ++ gpio_init(); ++ ++ return 0; ++} ++ ++int checkboard(void) ++{ ++ puts("Board: " CONFIG_BOARD_NAME "\n"); ++ ltq_chip_print_info(); ++ ++ return 0; ++} ++ ++static const struct ltq_eth_port_config eth_port_config[] = { ++ /* MAC0: ADM6996I */ ++ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII }, ++}; ++ ++static const struct ltq_eth_board_config eth_board_config = { ++ .ports = eth_port_config, ++ .num_ports = ARRAY_SIZE(eth_port_config), ++}; ++ ++int board_eth_init(bd_t *bis) ++{ ++ return ltq_eth_initialize(ð_board_config); ++} ++ ++static struct switch_device adm6996i_dev = { ++ .name = "adm6996i", ++ .cpu_port = 5, ++ .port_mask = 0xF, ++}; ++ ++int board_switch_init(void) ++{ ++ /* Deactivate HRST line to release reset of ADM6996I switch */ ++ ltq_reset_once(LTQ_RESET_HARD, 200000); ++ ++ /* ADM6996I needs some time to come out of reset */ ++ __udelay(50000); ++ ++ return switch_device_register(&adm6996i_dev); ++} +diff --git a/board/arcadyan/arv7510pw/config.mk b/board/arcadyan/arv7510pw/config.mk +new file mode 100644 +index 0000000..9d8953b +--- /dev/null ++++ b/board/arcadyan/arv7510pw/config.mk +@@ -0,0 +1,7 @@ ++# ++# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR) +diff --git a/board/arcadyan/arv7510pw/ddr_settings.h b/board/arcadyan/arv7510pw/ddr_settings.h +new file mode 100644 +index 0000000..e63f591 +--- /dev/null ++++ b/board/arcadyan/arv7510pw/ddr_settings.h +@@ -0,0 +1,53 @@ ++/* ++ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#define MC_DC00_VALUE 0x1B1B ++#define MC_DC01_VALUE 0x0 ++#define MC_DC02_VALUE 0x0 ++#define MC_DC03_VALUE 0x0 ++#define MC_DC04_VALUE 0x0 ++#define MC_DC05_VALUE 0x200 ++#define MC_DC06_VALUE 0x605 ++#define MC_DC07_VALUE 0x303 ++#define MC_DC08_VALUE 0x102 ++#define MC_DC09_VALUE 0x70A ++#define MC_DC10_VALUE 0x203 ++#define MC_DC11_VALUE 0xC02 ++#define MC_DC12_VALUE 0x1C8 ++#define MC_DC13_VALUE 0x1 ++#define MC_DC14_VALUE 0x0 ++#define MC_DC15_VALUE 0x120 ++#define MC_DC16_VALUE 0xC800 ++#define MC_DC17_VALUE 0xD ++#define MC_DC18_VALUE 0x301 ++#define MC_DC19_VALUE 0x200 ++#define MC_DC20_VALUE 0xA04 ++#define MC_DC21_VALUE 0x1700 ++#define MC_DC22_VALUE 0x1717 ++#define MC_DC23_VALUE 0x0 ++#define MC_DC24_VALUE 0x52 ++#define MC_DC25_VALUE 0x0 ++#define MC_DC26_VALUE 0x0 ++#define MC_DC27_VALUE 0x0 ++#define MC_DC28_VALUE 0x510 ++#define MC_DC29_VALUE 0x4E20 ++#define MC_DC30_VALUE 0x8235 ++#define MC_DC31_VALUE 0x0 ++#define MC_DC32_VALUE 0x0 ++#define MC_DC33_VALUE 0x0 ++#define MC_DC34_VALUE 0x0 ++#define MC_DC35_VALUE 0x0 ++#define MC_DC36_VALUE 0x0 ++#define MC_DC37_VALUE 0x0 ++#define MC_DC38_VALUE 0x0 ++#define MC_DC39_VALUE 0x0 ++#define MC_DC40_VALUE 0x0 ++#define MC_DC41_VALUE 0x0 ++#define MC_DC42_VALUE 0x0 ++#define MC_DC43_VALUE 0x0 ++#define MC_DC44_VALUE 0x0 ++#define MC_DC45_VALUE 0x500 ++#define MC_DC46_VALUE 0x0 +diff --git a/boards.cfg b/boards.cfg +index 287f974..29156d4 100644 +--- a/boards.cfg ++++ b/boards.cfg +@@ -515,6 +515,9 @@ Active mips mips32 au1x00 - pb1x00 + Active mips mips32 danube arcadyan arv4519pw arv4519pw_brn arv4519pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv4519pw arv4519pw_nor arv4519pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv4519pw arv4519pw_ram arv4519pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv7510pw arv7510pw_brn arv7510pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv7510pw arv7510pw_nor arv7510pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> ++Active mips mips32 danube arcadyan arv7510pw arv7510pw_ram arv7510pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv7518pw arv7518pw_brn arv7518pw:SYS_BOOT_BRN Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv7518pw arv7518pw_nor arv7518pw:SYS_BOOT_NOR Luka Perkov <luka@openwrt.org> + Active mips mips32 danube arcadyan arv7518pw arv7518pw_ram arv7518pw:SYS_BOOT_RAM Luka Perkov <luka@openwrt.org> +diff --git a/include/configs/arv7510pw.h b/include/configs/arv7510pw.h +new file mode 100644 +index 0000000..9eacfa1 +--- /dev/null ++++ b/include/configs/arv7510pw.h +@@ -0,0 +1,75 @@ ++/* ++ * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi> ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MACH_TYPE "ARV7510PW" ++#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE ++#define CONFIG_BOARD_NAME "Arcadyan ARV7510PW" ++ ++/* Configure SoC */ ++#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */ ++#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */ ++#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */ ++ ++/* Switch devices */ ++#define CONFIG_SWITCH_MULTI ++#define CONFIG_SWITCH_ADM6996I ++ ++/* SSIO */ ++#define CONFIG_LTQ_SSIO_SHIFT_REGS ++#define CONFIG_LTQ_SSIO_EDGE_FALLING ++#define CONFIG_LTQ_SSIO_GPHY1_MODE 0 ++#define CONFIG_LTQ_SSIO_GPHY2_MODE 0 ++#define CONFIG_LTQ_SSIO_INIT_VALUE 0 ++ ++/* Environment */ ++#if defined(CONFIG_SYS_BOOT_NOR) ++#define CONFIG_ENV_IS_IN_FLASH ++#define CONFIG_ENV_OVERWRITE ++#define CONFIG_ENV_OFFSET (256 * 1024) ++#define CONFIG_ENV_SECT_SIZE (128 * 1024) ++#else ++#define CONFIG_ENV_IS_NOWHERE ++#endif ++ ++#define CONFIG_ENV_SIZE (8 * 1024) ++#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR ++ ++/* Brnboot loadable image */ ++#if defined(CONFIG_SYS_BOOT_BRN) ++#define CONFIG_SYS_TEXT_BASE 0x80002000 ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_SYS_DISABLE_CACHE ++#define CONFIG_ENV_OVERWRITE 1 ++#endif ++ ++/* Console */ ++#define CONFIG_LTQ_ADVANCED_CONSOLE ++#define CONFIG_BAUDRATE 115200 ++#define CONFIG_CONSOLE_ASC 1 ++#define CONFIG_CONSOLE_DEV "ttyLTQ1" ++ ++/* Pull in default board configs for Lantiq XWAY Danube */ ++#include <asm/lantiq/config.h> ++#include <asm/arch/config.h> ++ ++/* Buffered write broken in ARV7510PW */ ++#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE ++ ++/* Pull in default OpenWrt configs for Lantiq SoC */ ++#include "openwrt-lantiq-common.h" ++ ++#define CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "update-uboot-nor=run load-uboot-nor write-uboot-nor\0" ++ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ CONFIG_ENV_LANTIQ_DEFAULTS \ ++ CONFIG_ENV_UPDATE_UBOOT_NOR \ ++ "kernel_addr=0xB0060000\0" ++ ++#endif /* __CONFIG_H */ +-- +1.8.3.2 + diff --git a/package/boot/uboot-lantiq/patches/0040-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch b/package/boot/uboot-lantiq/patches/0040-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch new file mode 100644 index 0000000..0b385eb --- /dev/null +++ b/package/boot/uboot-lantiq/patches/0040-Makefile-prepare-u-boot-lantiq-v2013.10-openwrt4.patch @@ -0,0 +1,23 @@ +From 7e2f79bc40b572763a4a1ed69f63aa2eaa6df254 Mon Sep 17 00:00:00 2001 +From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> +Date: Sun, 20 Oct 2013 19:39:17 +0200 +Subject: Makefile: prepare u-boot-lantiq-v2013.10-openwrt4 + +Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> + +diff --git a/Makefile b/Makefile +index 0445035..d5a55f8 100644 +--- a/Makefile ++++ b/Makefile +@@ -8,7 +8,7 @@ + VERSION = 2013 + PATCHLEVEL = 10 + SUBLEVEL = +-EXTRAVERSION = ++EXTRAVERSION = -openwrt4 + ifneq "$(SUBLEVEL)" "" + U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) + else +-- +1.8.3.2 + |