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-rw-r--r--package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch662
1 files changed, 0 insertions, 662 deletions
diff --git a/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch
index ef6eb1a..1f3bf83 100644
--- a/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch
+++ b/package/boot/uboot-lantiq/patches/0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch
@@ -5019,491 +5019,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
board_early_init_f,
timer_init,
env_init, /* initialize environment */
---- /dev/null
-+++ b/board/lantiq/easy50712/Makefile
-@@ -0,0 +1,27 @@
-+#
-+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB = $(obj)lib$(BOARD).o
-+
-+COBJS = $(BOARD).o
-+
-+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-+OBJS := $(addprefix $(obj),$(COBJS))
-+SOBJS := $(addprefix $(obj),$(SOBJS))
-+
-+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-+
-+#########################################################################
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
---- /dev/null
-+++ b/board/lantiq/easy50712/config.mk
-@@ -0,0 +1,7 @@
-+#
-+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
---- /dev/null
-+++ b/board/lantiq/easy50712/ddr_settings.h
-@@ -0,0 +1,54 @@
-+/*
-+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
-+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#define MC_DC00_VALUE 0x1B1B
-+#define MC_DC01_VALUE 0x0
-+#define MC_DC02_VALUE 0x0
-+#define MC_DC03_VALUE 0x0
-+#define MC_DC04_VALUE 0x0
-+#define MC_DC05_VALUE 0x200
-+#define MC_DC06_VALUE 0x605
-+#define MC_DC07_VALUE 0x303
-+#define MC_DC08_VALUE 0x102
-+#define MC_DC09_VALUE 0x70a
-+#define MC_DC10_VALUE 0x203
-+#define MC_DC11_VALUE 0xc02
-+#define MC_DC12_VALUE 0x1C8
-+#define MC_DC13_VALUE 0x1
-+#define MC_DC14_VALUE 0x0
-+#define MC_DC15_VALUE 0x13c
-+#define MC_DC16_VALUE 0xC800
-+#define MC_DC17_VALUE 0xd
-+#define MC_DC18_VALUE 0x300
-+#define MC_DC19_VALUE 0x200
-+#define MC_DC20_VALUE 0xA04
-+#define MC_DC21_VALUE 0xd00
-+#define MC_DC22_VALUE 0xd0d
-+#define MC_DC23_VALUE 0x0
-+#define MC_DC24_VALUE 0x62
-+#define MC_DC25_VALUE 0x0
-+#define MC_DC26_VALUE 0x0
-+#define MC_DC27_VALUE 0x0
-+#define MC_DC28_VALUE 0x510
-+#define MC_DC29_VALUE 0x2d89
-+#define MC_DC30_VALUE 0x8300
-+#define MC_DC31_VALUE 0x0
-+#define MC_DC32_VALUE 0x0
-+#define MC_DC33_VALUE 0x0
-+#define MC_DC34_VALUE 0x0
-+#define MC_DC35_VALUE 0x0
-+#define MC_DC36_VALUE 0x0
-+#define MC_DC37_VALUE 0x0
-+#define MC_DC38_VALUE 0x0
-+#define MC_DC39_VALUE 0x0
-+#define MC_DC40_VALUE 0x0
-+#define MC_DC41_VALUE 0x0
-+#define MC_DC42_VALUE 0x0
-+#define MC_DC43_VALUE 0x0
-+#define MC_DC44_VALUE 0x0
-+#define MC_DC45_VALUE 0x500
-+#define MC_DC46_VALUE 0x0
---- /dev/null
-+++ b/board/lantiq/easy50712/easy50712.c
-@@ -0,0 +1,112 @@
-+/*
-+ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
-+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <switch.h>
-+#include <spi.h>
-+#include <asm/gpio.h>
-+#include <asm/lantiq/eth.h>
-+#include <asm/lantiq/reset.h>
-+#include <asm/lantiq/chipid.h>
-+
-+static void gpio_init(void)
-+{
-+ /* SPI/CS output (low-active) for serial flash */
-+ gpio_direction_output(22, 1);
-+
-+ /* EBU.FL_CS1 as output for NAND CE */
-+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+ /* EBU.FL_A23 as output for NAND CLE */
-+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+ /* EBU.FL_A24 as output for NAND ALE */
-+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+
-+ /* enable CLK_OUT2 for external switch */
-+ gpio_set_altfunc(3, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+}
-+
-+int board_early_init_f(void)
-+{
-+ gpio_init();
-+
-+ return 0;
-+}
-+
-+int checkboard(void)
-+{
-+ puts("Board: " CONFIG_BOARD_NAME "\n");
-+ ltq_chip_print_info();
-+
-+ return 0;
-+}
-+
-+static const struct ltq_eth_port_config eth_port_config[] = {
-+ /* MAC0: Lantiq ADM6996I switch */
-+ { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
-+};
-+
-+static const struct ltq_eth_board_config eth_board_config = {
-+ .ports = eth_port_config,
-+ .num_ports = ARRAY_SIZE(eth_port_config),
-+};
-+
-+int board_eth_init(bd_t *bis)
-+{
-+ return ltq_eth_initialize(&eth_board_config);
-+}
-+
-+static struct switch_device adm6996i_dev = {
-+ .name = "adm6996i",
-+ .cpu_port = 5,
-+ .port_mask = 0xF,
-+};
-+
-+int board_switch_init(void)
-+{
-+ /* Deactivate HRST line to release reset of ADM6996I switch */
-+ ltq_reset_once(LTQ_RESET_HARD, 200000);
-+
-+ /* ADM6996I needs some time to come out of reset */
-+ __udelay(50000);
-+
-+ return switch_device_register(&adm6996i_dev);
-+}
-+
-+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-+{
-+ if (bus)
-+ return 0;
-+
-+ switch (cs) {
-+ case 2:
-+ return 1;
-+ default:
-+ return 0;
-+ }
-+}
-+
-+void spi_cs_activate(struct spi_slave *slave)
-+{
-+ switch (slave->cs) {
-+ case 2:
-+ gpio_set_value(22, 0);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+void spi_cs_deactivate(struct spi_slave *slave)
-+{
-+ switch (slave->cs) {
-+ case 2:
-+ gpio_set_value(22, 1);
-+ break;
-+ default:
-+ break;
-+ }
-+}
---- /dev/null
-+++ b/board/lantiq/easy80920/Makefile
-@@ -0,0 +1,27 @@
-+#
-+# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+include $(TOPDIR)/config.mk
-+
-+LIB = $(obj)lib$(BOARD).o
-+
-+COBJS = $(BOARD).o
-+
-+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-+OBJS := $(addprefix $(obj),$(COBJS))
-+SOBJS := $(addprefix $(obj),$(SOBJS))
-+
-+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
-+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-+
-+#########################################################################
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
---- /dev/null
-+++ b/board/lantiq/easy80920/config.mk
-@@ -0,0 +1,7 @@
-+#
-+# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+#
-+# SPDX-License-Identifier: GPL-2.0+
-+#
-+
-+PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
---- /dev/null
-+++ b/board/lantiq/easy80920/ddr_settings.h
-@@ -0,0 +1,69 @@
-+/*
-+ * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
-+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#define MC_CCR00_VALUE 0x101
-+#define MC_CCR01_VALUE 0x1000100
-+#define MC_CCR02_VALUE 0x1010000
-+#define MC_CCR03_VALUE 0x101
-+#define MC_CCR04_VALUE 0x1000000
-+#define MC_CCR05_VALUE 0x1000101
-+#define MC_CCR06_VALUE 0x1000100
-+#define MC_CCR07_VALUE 0x1010000
-+#define MC_CCR08_VALUE 0x1000101
-+#define MC_CCR09_VALUE 0x0
-+#define MC_CCR10_VALUE 0x2000100
-+#define MC_CCR11_VALUE 0x2000300
-+#define MC_CCR12_VALUE 0x30000
-+#define MC_CCR13_VALUE 0x202
-+#define MC_CCR14_VALUE 0x7080A0F
-+#define MC_CCR15_VALUE 0x2040F
-+#define MC_CCR16_VALUE 0x40000
-+#define MC_CCR17_VALUE 0x70102
-+#define MC_CCR18_VALUE 0x4020002
-+#define MC_CCR19_VALUE 0x30302
-+#define MC_CCR20_VALUE 0x8000700
-+#define MC_CCR21_VALUE 0x40F020A
-+#define MC_CCR22_VALUE 0x0
-+#define MC_CCR23_VALUE 0xC020000
-+#define MC_CCR24_VALUE 0x4401B04
-+#define MC_CCR25_VALUE 0x0
-+#define MC_CCR26_VALUE 0x0
-+#define MC_CCR27_VALUE 0x6420000
-+#define MC_CCR28_VALUE 0x0
-+#define MC_CCR29_VALUE 0x0
-+#define MC_CCR30_VALUE 0x798
-+#define MC_CCR31_VALUE 0x0
-+#define MC_CCR32_VALUE 0x0
-+#define MC_CCR33_VALUE 0x650000
-+#define MC_CCR34_VALUE 0x200C8
-+#define MC_CCR35_VALUE 0x1D445D
-+#define MC_CCR36_VALUE 0xC8
-+#define MC_CCR37_VALUE 0xC351
-+#define MC_CCR38_VALUE 0x0
-+#define MC_CCR39_VALUE 0x141F04
-+#define MC_CCR40_VALUE 0x142704
-+#define MC_CCR41_VALUE 0x141b42
-+#define MC_CCR42_VALUE 0x141b42
-+#define MC_CCR43_VALUE 0x566504
-+#define MC_CCR44_VALUE 0x566504
-+#define MC_CCR45_VALUE 0x565F17
-+#define MC_CCR46_VALUE 0x565F17
-+#define MC_CCR47_VALUE 0x0
-+#define MC_CCR48_VALUE 0x0
-+#define MC_CCR49_VALUE 0x0
-+#define MC_CCR50_VALUE 0x0
-+#define MC_CCR51_VALUE 0x0
-+#define MC_CCR52_VALUE 0x133
-+#define MC_CCR53_VALUE 0xF3014B27
-+#define MC_CCR54_VALUE 0xF3014B27
-+#define MC_CCR55_VALUE 0xF3014B27
-+#define MC_CCR56_VALUE 0xF3014B27
-+#define MC_CCR57_VALUE 0x7800301
-+#define MC_CCR58_VALUE 0x7800301
-+#define MC_CCR59_VALUE 0x7800301
-+#define MC_CCR60_VALUE 0x7800301
-+#define MC_CCR61_VALUE 0x4
---- /dev/null
-+++ b/board/lantiq/easy80920/easy80920.c
-@@ -0,0 +1,138 @@
-+/*
-+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#include <common.h>
-+#include <spi.h>
-+#include <asm/gpio.h>
-+#include <asm/lantiq/eth.h>
-+#include <asm/lantiq/chipid.h>
-+#include <asm/lantiq/cpu.h>
-+#include <asm/arch/gphy.h>
-+
-+#if defined(CONFIG_SPL_BUILD)
-+#define do_gpio_init 1
-+#define do_pll_init 1
-+#define do_dcdc_init 0
-+#elif defined(CONFIG_SYS_BOOT_RAM)
-+#define do_gpio_init 1
-+#define do_pll_init 0
-+#define do_dcdc_init 1
-+#elif defined(CONFIG_SYS_BOOT_NOR)
-+#define do_gpio_init 1
-+#define do_pll_init 1
-+#define do_dcdc_init 1
-+#else
-+#define do_gpio_init 0
-+#define do_pll_init 0
-+#define do_dcdc_init 1
-+#endif
-+
-+static void gpio_init(void)
-+{
-+ /* SPI CS 0.4 to serial flash */
-+ gpio_direction_output(10, 1);
-+
-+ /* EBU.FL_CS1 as output for NAND CE */
-+ gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+ /* EBU.FL_A23 as output for NAND CLE */
-+ gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+ /* EBU.FL_A24 as output for NAND ALE */
-+ gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+ /* GPIO 3.0 as input for NAND Ready Busy */
-+ gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
-+ /* GPIO 3.1 as output for NAND Read */
-+ gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
-+}
-+
-+int board_early_init_f(void)
-+{
-+ if (do_gpio_init)
-+ gpio_init();
-+
-+ if (do_pll_init)
-+ ltq_pll_init();
-+
-+ if (do_dcdc_init)
-+ ltq_dcdc_init(0x7F);
-+
-+ return 0;
-+}
-+
-+int checkboard(void)
-+{
-+ puts("Board: " CONFIG_BOARD_NAME "\n");
-+ ltq_chip_print_info();
-+
-+ return 0;
-+}
-+
-+static const struct ltq_eth_port_config eth_port_config[] = {
-+ /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
-+ { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
-+ /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
-+ { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
-+ /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
-+ { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
-+ /* GMAC3: unused */
-+ { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
-+ /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
-+ { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
-+ /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
-+ { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
-+};
-+
-+static const struct ltq_eth_board_config eth_board_config = {
-+ .ports = eth_port_config,
-+ .num_ports = ARRAY_SIZE(eth_port_config),
-+};
-+
-+int board_eth_init(bd_t * bis)
-+{
-+ const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
-+ const ulong fw_addr = 0x80FF0000;
-+
-+ ltq_gphy_phy11g_a1x_load(fw_addr);
-+
-+ ltq_cgu_gphy_clk_src(clk);
-+
-+ ltq_rcu_gphy_boot(0, fw_addr);
-+ ltq_rcu_gphy_boot(1, fw_addr);
-+
-+ return ltq_eth_initialize(&eth_board_config);
-+}
-+
-+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
-+{
-+ if (bus)
-+ return 0;
-+
-+ if (cs == 4)
-+ return 1;
-+
-+ return 0;
-+}
-+
-+void spi_cs_activate(struct spi_slave *slave)
-+{
-+ switch (slave->cs) {
-+ case 4:
-+ gpio_set_value(10, 0);
-+ break;
-+ default:
-+ break;
-+ }
-+}
-+
-+void spi_cs_deactivate(struct spi_slave *slave)
-+{
-+ switch (slave->cs) {
-+ case 4:
-+ gpio_set_value(10, 1);
-+ break;
-+ default:
-+ break;
-+ }
-+}
---- a/boards.cfg
-+++ b/boards.cfg
-@@ -502,10 +502,17 @@ Active mips mips32 au1x0
- Active mips mips32 au1x00 - dbau1x00 dbau1550 dbau1x00:DBAU1550 Thomas Lange <thomas@corelatus.se>
- Active mips mips32 au1x00 - dbau1x00 dbau1550_el dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN Thomas Lange <thomas@corelatus.se>
- Active mips mips32 au1x00 - pb1x00 pb1000 pb1x00:PB1000 -
-+Active mips mips32 danube lantiq easy50712 easy50712_nor easy50712:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-+Active mips mips32 danube lantiq easy50712 easy50712_norspl easy50712:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-+Active mips mips32 danube lantiq easy50712 easy50712_ram easy50712:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
- Active mips mips32 incaip - incaip incaip - Wolfgang Denk <wd@denx.de>
- Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
- Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
- Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
-+Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-+Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-+Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-+Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
- Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
- Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
- Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -12,6 +12,7 @@ LIB := $(obj)libdma.o
@@ -8782,183 +8297,6 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
+
+ return ret;
+}
---- /dev/null
-+++ b/include/configs/easy50712.h
-@@ -0,0 +1,79 @@
-+/*
-+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#define CONFIG_MACH_TYPE "EASY50712"
-+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
-+#define CONFIG_BOARD_NAME "Lantiq EASY50712 Danube Reference Board"
-+
-+/* Configure SoC */
-+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
-+
-+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
-+
-+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
-+
-+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
-+#define CONFIG_SPI_FLASH_ATMEL /* Have an AT45DB321D serial flash */
-+
-+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
-+
-+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
-+
-+#define CONFIG_LTQ_SPL_COMP_LZO
-+#define CONFIG_LTQ_SPL_CONSOLE
-+
-+/* Switch devices */
-+#define CONFIG_SWITCH_MULTI
-+#define CONFIG_SWITCH_ADM6996I
-+
-+/* Environment */
-+#define CONFIG_ENV_SPI_BUS 0
-+#define CONFIG_ENV_SPI_CS 2
-+#define CONFIG_ENV_SPI_MAX_HZ 20000000
-+#define CONFIG_ENV_SPI_MODE 0
-+
-+#if defined(CONFIG_SYS_BOOT_NOR)
-+#define CONFIG_ENV_IS_IN_FLASH
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_ENV_OFFSET (256 * 1024)
-+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-+#elif defined(CONFIG_SYS_BOOT_NORSPL)
-+#define CONFIG_ENV_IS_IN_FLASH
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_ENV_OFFSET (128 * 1024)
-+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-+#else
-+#define CONFIG_ENV_IS_NOWHERE
-+#endif
-+
-+#define CONFIG_ENV_SIZE (8 * 1024)
-+
-+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-+
-+/* Console */
-+#define CONFIG_LTQ_ADVANCED_CONSOLE
-+#define CONFIG_BAUDRATE 115200
-+#define CONFIG_CONSOLE_ASC 1
-+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
-+
-+/* Commands */
-+#define CONFIG_CMD_PING
-+
-+/* Pull in default board configs for Lantiq XWAY Danube */
-+#include <asm/lantiq/config.h>
-+#include <asm/arch/config.h>
-+
-+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
-+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ CONFIG_ENV_LANTIQ_DEFAULTS \
-+ CONFIG_ENV_UPDATE_UBOOT_NOR
-+
-+#endif /* __CONFIG_H */
---- /dev/null
-+++ b/include/configs/easy80920.h
-@@ -0,0 +1,92 @@
-+/*
-+ * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
-+ *
-+ * SPDX-License-Identifier: GPL-2.0+
-+ */
-+
-+#ifndef __CONFIG_H
-+#define __CONFIG_H
-+
-+#define CONFIG_MACH_TYPE "EASY80920"
-+#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
-+#define CONFIG_BOARD_NAME "Lantiq EASY80920 VRX200 Family Board"
-+
-+/* Configure SoC */
-+#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
-+
-+#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
-+
-+#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
-+
-+#define CONFIG_LTQ_SUPPORT_SPI_FLASH
-+#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
-+
-+#define CONFIG_LTQ_SUPPORT_NAND_FLASH
-+
-+#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
-+#define CONFIG_SPL_SPI_BUS 0
-+#define CONFIG_SPL_SPI_CS 4
-+#define CONFIG_SPL_SPI_MAX_HZ 25000000
-+#define CONFIG_SPL_SPI_MODE 0
-+
-+#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
-+
-+#define CONFIG_LTQ_SPL_COMP_LZO
-+#define CONFIG_LTQ_SPL_CONSOLE
-+
-+#define CONFIG_SYS_DRAM_PROBE
-+
-+/* Environment */
-+#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
-+#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
-+#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
-+#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
-+
-+#if defined(CONFIG_SYS_BOOT_NOR)
-+#define CONFIG_ENV_IS_IN_FLASH
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_ENV_OFFSET (384 * 1024)
-+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-+#elif defined(CONFIG_SYS_BOOT_NORSPL)
-+#define CONFIG_ENV_IS_IN_FLASH
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_ENV_OFFSET (192 * 1024)
-+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-+#elif defined(CONFIG_SYS_BOOT_SFSPL)
-+#define CONFIG_ENV_IS_IN_SPI_FLASH
-+#define CONFIG_ENV_OVERWRITE
-+#define CONFIG_ENV_OFFSET (192 * 1024)
-+#define CONFIG_ENV_SECT_SIZE (64 * 1024)
-+#else
-+#define CONFIG_ENV_IS_NOWHERE
-+#endif
-+
-+#define CONFIG_ENV_SIZE (8 * 1024)
-+
-+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
-+
-+/* Console */
-+#define CONFIG_LTQ_ADVANCED_CONSOLE
-+#define CONFIG_BAUDRATE 115200
-+#define CONFIG_CONSOLE_ASC 1
-+#define CONFIG_CONSOLE_DEV "ttyLTQ1"
-+
-+/* Commands */
-+#define CONFIG_CMD_PING
-+
-+/* Pull in default board configs for Lantiq XWAY VRX200 */
-+#include <asm/lantiq/config.h>
-+#include <asm/arch/config.h>
-+
-+#define CONFIG_ENV_UPDATE_UBOOT_NOR \
-+ "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
-+
-+#define CONFIG_ENV_UPDATE_UBOOT_SF \
-+ "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
-+
-+#define CONFIG_EXTRA_ENV_SETTINGS \
-+ CONFIG_ENV_LANTIQ_DEFAULTS \
-+ CONFIG_ENV_UPDATE_UBOOT_NOR \
-+ CONFIG_ENV_UPDATE_UBOOT_SF
-+
-+#endif /* __CONFIG_H */
--- a/include/phy.h
+++ b/include/phy.h
@@ -214,6 +214,7 @@ int phy_atheros_init(void);
generated by cgit v1.1 at 2025-04-04 15:01:46 +0000