diff options
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch b/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch new file mode 100644 index 0000000..b24bc18 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch @@ -0,0 +1,141 @@ +From 014f9196e18f4157232d0521f3a7502e7dbbb974 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Fri, 13 May 2016 13:28:07 +0800 +Subject: [PATCH 02/93] armv8: SMP support for loading 32-bit OS + +Spin-table method is used for secondary cores to load 32-bit OS. The +architecture information will be got through checking FIT image and +saved in the os_arch element of spin-table, then the secondary cores +will check os_arch and jump to 32-bit OS or 64-bit OS automatically. + +Signed-off-by: Alison Wang <alison.wang@nxp.com> +Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> +--- + arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 21 +++++++++++++++++++++ + arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 ++++++++++ + arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++++ + arch/arm/lib/bootm.c | 5 +++++ + 4 files changed, 42 insertions(+) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +index 9c69ed1..93f4a65 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S ++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +@@ -13,6 +13,7 @@ + #ifdef CONFIG_MP + #include <asm/arch/mp.h> + #endif ++#include <asm/u-boot.h> + + ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ +@@ -320,6 +321,11 @@ ENTRY(secondary_boot_func) + gic_wait_for_interrupt_m x0, w1 + #endif + ++ ldr x5, [x11, #24] ++ ldr x6, =IH_ARCH_DEFAULT ++ cmp x6, x5 ++ b.ne slave_cpu ++ + bl secondary_switch_to_el2 + #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl secondary_switch_to_el1 +@@ -337,6 +343,21 @@ slave_cpu: + tbz x1, #25, cpu_is_le + rev x0, x0 /* BE to LE conversion */ + cpu_is_le: ++ ++ ldr x5, [x11, #24] ++ ldr x6, =IH_ARCH_DEFAULT ++ cmp x6, x5 ++ b.eq 1f ++ ++#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 ++ bl secondary_switch_to_el2 ++ ldr x0, [x11] ++ bl armv8_switch_to_el1_aarch32 ++#else ++ bl armv8_switch_to_el2_aarch32 ++#endif ++ ++1: + br x0 /* branch to the given address */ + ENDPROC(secondary_boot_func) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c +index df7ffb8..dd91550 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c ++++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c +@@ -22,6 +22,16 @@ phys_addr_t determine_mp_bootpg(void) + return (phys_addr_t)&secondary_boot_code; + } + ++void update_os_arch_secondary_cores(uint8_t os_arch) ++{ ++ u64 *table = get_spin_tbl_addr(); ++ int i; ++ ++ for (i = 1; i < CONFIG_MAX_CPUS; i++) ++ table[i * WORDS_PER_SPIN_TABLE_ENTRY + ++ SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch; ++} ++ + int fsl_layerscape_wake_seconday_cores(void) + { + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h +index e46e076..55f0e0c 100644 +--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h ++++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h +@@ -13,6 +13,7 @@ + * uint64_t entry_addr; + * uint64_t status; + * uint64_t lpid; ++* uint64_t os_arch; + * }; + * we pad this struct to 64 bytes so each entry is in its own cacheline + * the actual spin table is an array of these structures +@@ -20,6 +21,7 @@ + #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 + #define SPIN_TABLE_ELEM_STATUS_IDX 1 + #define SPIN_TABLE_ELEM_LPID_IDX 2 ++#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3 + #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ + #define SPIN_TABLE_ELEM_SIZE 64 + +@@ -35,4 +37,8 @@ phys_addr_t determine_mp_bootpg(void); + void secondary_boot_func(void); + int is_core_online(u64 cpu_id); + #endif ++ ++#define IH_ARCH_ARM 2 /* ARM */ ++#define IH_ARCH_ARM64 22 /* ARM64 */ ++ + #endif /* _FSL_LAYERSCAPE_MP_H */ +diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c +index 36f2cb0..aae8c5b 100644 +--- a/arch/arm/lib/bootm.c ++++ b/arch/arm/lib/bootm.c +@@ -258,6 +258,10 @@ bool armv7_boot_nonsec(void) + } + #endif + ++__weak void update_os_arch_secondary_cores(uint8_t os_arch) ++{ ++} ++ + /* Subcommand: GO */ + static void boot_jump_linux(bootm_headers_t *images, int flag) + { +@@ -276,6 +280,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) + announce_and_cleanup(fake); + + if (!fake) { ++ update_os_arch_secondary_cores(images->os.arch); + if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) && + (images->os.arch == IH_ARCH_ARM)) { + smp_kick_all_cpus(); +-- +1.7.9.5 + |