diff options
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch b/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch new file mode 100644 index 0000000..33c3a57 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0012-armv8-LSCH2-early-and-final-mmu-needs-matching-NS-at.patch @@ -0,0 +1,58 @@ +From edc5b23b8dd04980e0fa48fe79ba811b775cd2c2 Mon Sep 17 00:00:00 2001 +From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +Date: Sat, 23 Apr 2016 12:34:59 +0530 +Subject: [PATCH 12/93] armv8: LSCH2 early and final mmu needs matching NS + attribute + +When switching between the early and final mmu tables, the stack will +get corrupted if the Non-Secure attribute is different. For ls1043a, +this issue is currently masked because flush_dcache_all is called +before the switch when CONFIG_SYS_DPAA_FMAN is defined. + +Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com> +Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +--- + arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +index a9dadfa..a7522da 100644 +--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h ++++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +@@ -159,9 +159,11 @@ static const struct sys_mmu_table early_mmu_table[] = { + { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE, + CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE }, + { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1, +- CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE }, ++ CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, ++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, +- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, ++ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, ++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS}, + #endif + }; + +@@ -249,7 +251,8 @@ static const struct sys_mmu_table final_mmu_table[] = { + CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, + { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2, +- CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE }, ++ CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, ++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS}, + { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, + CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, +@@ -260,7 +263,8 @@ static const struct sys_mmu_table final_mmu_table[] = { + CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, + PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN }, + { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3, +- CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE }, ++ CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, ++ PMD_SECT_OUTER_SHARE | PMD_SECT_NS }, + #endif + }; + #endif +-- +1.7.9.5 + |