diff options
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch | 1237 |
1 files changed, 1237 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch b/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch new file mode 100644 index 0000000..4a9ebfa --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0014-armv8-ls1012a-Add-support-of-ls1012aqds-board.patch @@ -0,0 +1,1237 @@ +From faf0aac702a2253471f98687ed40138e514e38ab Mon Sep 17 00:00:00 2001 +From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +Date: Mon, 25 Apr 2016 14:36:16 +0530 +Subject: [PATCH 14/93] armv8: ls1012a: Add support of ls1012aqds board + +QorIQ LS1012A Development System (LS1012AQDS) is a high-performance +development platform, with a complete debugging environment. +The LS1012AQDS board supports the QorIQ LS1012A processor and is +optimized to support the high-bandwidth DDR3L memory and +a full complement of high-speed SerDes ports. + +Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> +Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> +--- + arch/arm/Kconfig | 10 ++ + arch/arm/dts/Makefile | 3 +- + arch/arm/dts/fsl-ls1012a-qds.dts | 14 ++ + arch/arm/dts/fsl-ls1012a-qds.dtsi | 123 +++++++++++++ + arch/arm/dts/fsl-ls1012a.dtsi | 119 ++++++++++++ + board/freescale/ls1012aqds/Kconfig | 15 ++ + board/freescale/ls1012aqds/MAINTAINERS | 6 + + board/freescale/ls1012aqds/Makefile | 7 + + board/freescale/ls1012aqds/README | 94 ++++++++++ + board/freescale/ls1012aqds/ls1012aqds.c | 199 ++++++++++++++++++++ + board/freescale/ls1012aqds/ls1012aqds_qixis.h | 35 ++++ + configs/ls1012aqds_qspi_defconfig | 10 ++ + include/configs/ls1012a_common.h | 239 +++++++++++++++++++++++++ + include/configs/ls1012aqds.h | 133 ++++++++++++++ + include/fsl_mmdc.h | 57 +++++- + 15 files changed, 1055 insertions(+), 9 deletions(-) + create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dts + create mode 100644 arch/arm/dts/fsl-ls1012a-qds.dtsi + create mode 100644 arch/arm/dts/fsl-ls1012a.dtsi + create mode 100644 board/freescale/ls1012aqds/Kconfig + create mode 100644 board/freescale/ls1012aqds/MAINTAINERS + create mode 100644 board/freescale/ls1012aqds/Makefile + create mode 100644 board/freescale/ls1012aqds/README + create mode 100644 board/freescale/ls1012aqds/ls1012aqds.c + create mode 100644 board/freescale/ls1012aqds/ls1012aqds_qixis.h + create mode 100644 configs/ls1012aqds_qspi_defconfig + create mode 100644 include/configs/ls1012a_common.h + create mode 100644 include/configs/ls1012aqds.h + +diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig +index 9bd6cf1..f5033db 100644 +--- a/arch/arm/Kconfig ++++ b/arch/arm/Kconfig +@@ -647,6 +647,15 @@ config TARGET_HIKEY + Support for HiKey 96boards platform. It features a HI6220 + SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. + ++config TARGET_LS1012AQDS ++ bool "Support ls1012aqds" ++ select ARM64 ++ help ++ Support for Freescale LS1012AQDS platform. ++ The LS1012A Development System (QDS) is a high-performance ++ development platform that supports the QorIQ LS1012A ++ Layerscape Architecture processor. ++ + config TARGET_LS1021AQDS + bool "Support ls1021aqds" + select CPU_V7 +@@ -792,6 +801,7 @@ source "board/freescale/ls1021aqds/Kconfig" + source "board/freescale/ls1043aqds/Kconfig" + source "board/freescale/ls1021atwr/Kconfig" + source "board/freescale/ls1043ardb/Kconfig" ++source "board/freescale/ls1012aqds/Kconfig" + source "board/freescale/mx23evk/Kconfig" + source "board/freescale/mx25pdk/Kconfig" + source "board/freescale/mx28evk/Kconfig" +diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile +index c1c81e4..ed5eb38 100644 +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -94,7 +94,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ + fsl-ls2080a-rdb.dtb + dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ + fsl-ls1043a-qds-lpuart.dtb \ +- fsl-ls1043a-rdb.dtb ++ fsl-ls1043a-rdb.dtb \ ++ fsl-ls1012a-qds.dtb + + dtb-$(CONFIG_MACH_SUN4I) += \ + sun4i-a10-a1000.dtb \ +diff --git a/arch/arm/dts/fsl-ls1012a-qds.dts b/arch/arm/dts/fsl-ls1012a-qds.dts +new file mode 100644 +index 0000000..ef6de34 +--- /dev/null ++++ b/arch/arm/dts/fsl-ls1012a-qds.dts +@@ -0,0 +1,14 @@ ++/* ++ * Copyright (C) 2016 Freescale Semiconductor ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++/dts-v1/; ++#include "fsl-ls1012a-qds.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = &duart0; ++ }; ++}; +diff --git a/arch/arm/dts/fsl-ls1012a-qds.dtsi b/arch/arm/dts/fsl-ls1012a-qds.dtsi +new file mode 100644 +index 0000000..a32a84a +--- /dev/null ++++ b/arch/arm/dts/fsl-ls1012a-qds.dtsi +@@ -0,0 +1,123 @@ ++/* ++ * Copyright (C) 2016 Freescale Semiconductor ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++/include/ "fsl-ls1012a.dtsi" ++ ++/ { ++ model = "LS1012A QDS Board"; ++ aliases { ++ spi0 = &qspi; ++ spi1 = &dspi0; ++ }; ++}; ++ ++&dspi0 { ++ bus-num = <0>; ++ status = "okay"; ++ ++ dflash0: n25q128a { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-flash"; ++ reg = <0>; ++ spi-max-frequency = <1000000>; /* input clock */ ++ }; ++ ++ dflash1: sst25wf040b { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-flash"; ++ spi-max-frequency = <3500000>; ++ reg = <1>; ++ }; ++ ++ dflash2: en25s64 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-flash"; ++ spi-max-frequency = <3500000>; ++ reg = <2>; ++ }; ++}; ++ ++&qspi { ++ bus-num = <0>; ++ status = "okay"; ++ ++ qflash0: s25fl128s@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "spi-flash"; ++ spi-max-frequency = <20000000>; ++ reg = <0>; ++ }; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ pca9547@77 { ++ compatible = "philips,pca9547"; ++ reg = <0x77>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; ++ ++ rtc@68 { ++ compatible = "dallas,ds3232"; ++ reg = <0x68>; ++ /* IRQ10_B */ ++ interrupts = <0 150 0x4>; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x2>; ++ ++ ina220@40 { ++ compatible = "ti,ina220"; ++ reg = <0x40>; ++ shunt-resistor = <1000>; ++ }; ++ ++ ina220@41 { ++ compatible = "ti,ina220"; ++ reg = <0x41>; ++ shunt-resistor = <1000>; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x3>; ++ ++ eeprom@56 { ++ compatible = "at24,24c512"; ++ reg = <0x56>; ++ }; ++ ++ eeprom@57 { ++ compatible = "at24,24c512"; ++ reg = <0x57>; ++ }; ++ ++ adt7461a@4c { ++ compatible = "adt7461a"; ++ reg = <0x4c>; ++ }; ++ }; ++ }; ++}; ++ ++&duart0 { ++ status = "okay"; ++}; +diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi +new file mode 100644 +index 0000000..87a287a +--- /dev/null ++++ b/arch/arm/dts/fsl-ls1012a.dtsi +@@ -0,0 +1,119 @@ ++/* ++ * Copyright (C) 2016 Freescale Semiconductor ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++/include/ "skeleton64.dtsi" ++ ++/ { ++ compatible = "fsl,ls1012a"; ++ interrupt-parent = <&gic>; ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a53"; ++ reg = <0x0 0x0>; ++ clocks = <&clockgen 1 0>; ++ }; ++ ++ }; ++ ++ sysclk: sysclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ clock-output-names = "sysclk"; ++ }; ++ ++ gic: interrupt-controller@1400000 { ++ compatible = "arm,gic-400"; ++ #interrupt-cells = <3>; ++ interrupt-controller; ++ reg = <0x0 0x1401000 0 0x1000>, /* GICD */ ++ <0x0 0x1402000 0 0x2000>, /* GICC */ ++ <0x0 0x1404000 0 0x2000>, /* GICH */ ++ <0x0 0x1406000 0 0x2000>; /* GICV */ ++ interrupts = <1 9 0xf08>; ++ }; ++ ++ soc { ++ compatible = "simple-bus"; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ clockgen: clocking@1ee1000 { ++ compatible = "fsl,ls1012a-clockgen"; ++ reg = <0x0 0x1ee1000 0x0 0x1000>; ++ #clock-cells = <2>; ++ clocks = <&sysclk>; ++ }; ++ ++ dspi0: dspi@2100000 { ++ compatible = "fsl,vf610-dspi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2100000 0x0 0x10000>; ++ interrupts = <0 64 0x4>; ++ clock-names = "dspi"; ++ clocks = <&clockgen 4 0>; ++ num-cs = <6>; ++ big-endian; ++ status = "disabled"; ++ }; ++ ++ ++ i2c0: i2c@2180000 { ++ compatible = "fsl,vf610-i2c"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2180000 0x0 0x10000>; ++ interrupts = <0 56 0x4>; ++ clock-names = "i2c"; ++ clocks = <&clockgen 4 0>; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@2190000 { ++ compatible = "fsl,vf610-i2c"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2190000 0x0 0x10000>; ++ interrupts = <0 57 0x4>; ++ clock-names = "i2c"; ++ clocks = <&clockgen 4 0>; ++ status = "disabled"; ++ }; ++ ++ duart0: serial@21c0500 { ++ compatible = "fsl,ns16550", "ns16550a"; ++ reg = <0x00 0x21c0500 0x0 0x100>; ++ interrupts = <0 54 0x4>; ++ clocks = <&clockgen 4 0>; ++ }; ++ ++ duart1: serial@21c0600 { ++ compatible = "fsl,ns16550", "ns16550a"; ++ reg = <0x00 0x21c0600 0x0 0x100>; ++ interrupts = <0 54 0x4>; ++ clocks = <&clockgen 4 0>; ++ }; ++ ++ qspi: quadspi@1550000 { ++ compatible = "fsl,vf610-qspi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x1550000 0x0 0x10000>, ++ <0x0 0x40000000 0x0 0x4000000>; ++ reg-names = "QuadSPI", "QuadSPI-memory"; ++ num-cs = <2>; ++ big-endian; ++ status = "disabled"; ++ }; ++ ++ }; ++}; +diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig +new file mode 100644 +index 0000000..1257ec8 +--- /dev/null ++++ b/board/freescale/ls1012aqds/Kconfig +@@ -0,0 +1,15 @@ ++if TARGET_LS1012AQDS ++ ++config SYS_BOARD ++ default "ls1012aqds" ++ ++config SYS_VENDOR ++ default "freescale" ++ ++config SYS_SOC ++ default "fsl-layerscape" ++ ++config SYS_CONFIG_NAME ++ default "ls1012aqds" ++ ++endif +diff --git a/board/freescale/ls1012aqds/MAINTAINERS b/board/freescale/ls1012aqds/MAINTAINERS +new file mode 100644 +index 0000000..3c01df6 +--- /dev/null ++++ b/board/freescale/ls1012aqds/MAINTAINERS +@@ -0,0 +1,6 @@ ++LS1012AQDS BOARD ++M: ++S: Maintained ++F: board/freescale/ls1012aqds/ ++F: include/configs/ls1012aqds.h ++F: configs/ls1012aqds_defconfig +diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile +new file mode 100644 +index 0000000..0b813f9 +--- /dev/null ++++ b/board/freescale/ls1012aqds/Makefile +@@ -0,0 +1,7 @@ ++# ++# Copyright 2016 Freescale Semiconductor, Inc. ++# ++# SPDX-License-Identifier: GPL-2.0+ ++# ++ ++obj-y += ls1012aqds.o +diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README +new file mode 100644 +index 0000000..e94a267 +--- /dev/null ++++ b/board/freescale/ls1012aqds/README +@@ -0,0 +1,94 @@ ++Overview ++-------- ++The LS1012AQDS power supplies (PS) provide all the voltages necessary ++for the correct operation of the LS1012A processor, DDR3L, QSPI memory, ++and other onboard peripherals. ++ ++LS1012A SoC Overview ++-------------------- ++The LS1012A features an advanced 64-bit ARM v8 Cortex- ++A53 processor, with 32 KB of parity protected L1-I cache, ++32 KB of ECC protected L1-D cache, as well as 256 KB of ++ECC protected L2 cache. ++ ++The LS1012A SoC includes the following function and features: ++ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: ++ - ARM v8 cryptography extensions ++ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports ++ 16-/8-bit operation (no ECC support) ++ - ARM core-link CCI-400 cache coherent interconnect ++ - Packet Forwarding Engine (PFE) ++ - Cryptography acceleration (SEC) ++ - Ethernet interfaces supported by PFE: ++ - One Configurable x3 SerDes: ++ Two Serdes PLLs supported for usage by any SerDes data lane ++ Support for up to 6 GBaud operation ++ - High-speed peripheral interfaces: ++ - One PCI Express Gen2 controller, supporting x1 operation ++ - One serial ATA (SATA Gen 3.0) controller ++ - One USB 3.0/2.0 controller with integrated PHY ++ - One USB 2.0 controller with ULPI interface. . ++ - Additional peripheral interfaces: ++ - One quad serial peripheral interface (QuadSPI) controller ++ - One serial peripheral interface (SPI) controller ++ - Two enhanced secure digital host controllers ++ - Two I2C controllers ++ - One 16550 compliant DUART (two UART interfaces) ++ - Two general purpose IOs (GPIO) ++ - Two FlexTimers ++ - Five synchronous audio interfaces (SAI) ++ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading ++ - Single-source clocking solution enabling generation of core, platform, ++ DDR, SerDes, and USB clocks from a single external crystal and internal ++ crystaloscillator ++ - Thermal monitor unit (TMU) with +/- 3C accuracy ++ - Two WatchDog timers ++ - ARM generic timer ++ - QorIQ platform's trust architecture 2.1 ++ ++ LS1012AQDS board Overview ++ ----------------------- ++ - SERDES Connections, 4 lanes supporting: ++ - PCI Express - 3.0 ++ - SGMII, SGMII 2.5 ++ - SATA 3.0 ++ - DDR Controller ++ - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s ++ - QSPI Controller ++ - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select ++ signals to QSPI NOR flash memory (2 virtual banks) and the QSPI ++ emulator ++ - USB 3.0 ++ - One USB 3.0 controller with integrated PHY ++ - One high-speed USB 3.0 port ++ - USB 2.0 ++ - One USB 2.0 controller with ULPI interface ++ - Two enhanced secure digital host controllers: ++ - SDHC1 controller can be connected to onboard SDHC connector ++ - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices ++ - 2 I2C controllers ++ - One SATA onboard connectors ++ - UART ++ - 5 SAI ++ - One SAI port with audio codec SGTL5000: ++ • Provides MIC bias ++ • Provides headphone and line output ++ - One SAI port terminated at 2x6 header ++ - Three SAI Tx/Rx ports terminated at 2x3 headers ++ - ARM JTAG support ++ ++Booting Options ++--------------- ++a) QSPI Flash Emu Boot ++b) QSPI Flash 1 ++c) QSPI Flash 2 ++ ++QSPI flash map ++-------------- ++Images | Size |QSPI Flash Address ++------------------------------------------ ++RCW + PBI | 1MB | 0x4000_0000 ++U-boot | 1MB | 0x4010_0000 ++U-boot Env | 1MB | 0x4020_0000 ++PPA FIT image | 2MB | 0x4050_0000 ++Linux ITB | ~53MB | 0x40A0_0000 +diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c +new file mode 100644 +index 0000000..ffcd0d8 +--- /dev/null ++++ b/board/freescale/ls1012aqds/ls1012aqds.c +@@ -0,0 +1,199 @@ ++/* ++ * Copyright 2016 Freescale Semiconductor, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#include <common.h> ++#include <i2c.h> ++#include <fdt_support.h> ++#include <asm/io.h> ++#include <asm/arch/clock.h> ++#include <asm/arch/fsl_serdes.h> ++#include <asm/arch/fdt.h> ++#include <asm/arch/soc.h> ++#include <ahci.h> ++#include <hwconfig.h> ++#include <mmc.h> ++#include <scsi.h> ++#include <fm_eth.h> ++#include <fsl_csu.h> ++#include <fsl_esdhc.h> ++#include <fsl_mmdc.h> ++#include <spl.h> ++#include <netdev.h> ++ ++#include "../common/qixis.h" ++#include "ls1012aqds_qixis.h" ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++int checkboard(void) ++{ ++ puts("Board: LS1012AQDS\n"); ++ ++ return 0; ++} ++ ++void mmdc_init(void) ++{ ++ struct mmdc_p_regs *mmdc = ++ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; ++ ++ /* Set MMDC_MDSCR[CON_REQ] */ ++ out_be32(&mmdc->mdscr, 0x00008000); ++ ++ /* configure timing parms */ ++ out_be32(&mmdc->mdotc, 0x12554000); ++ out_be32(&mmdc->mdcfg0, 0xbabf7954); ++ out_be32(&mmdc->mdcfg1, 0xff328f64); ++ out_be32(&mmdc->mdcfg2, 0x01ff00db); ++ ++ /* other parms */ ++ out_be32(&mmdc->mdmisc, 0x00000680); ++ out_be32(&mmdc->mpmur0, 0x00000800); ++ out_be32(&mmdc->mdrwd, 0x00002000); ++ out_be32(&mmdc->mpodtctrl, 0x0000022a); ++ ++ /* out of reset delays */ ++ out_be32(&mmdc->mdor, 0x00bf1023); ++ ++ /* physical parms */ ++ out_be32(&mmdc->mdctl, 0x05180000); ++ out_be32(&mmdc->mdasp, 0x0000007f); ++ ++ /* Enable MMDC */ ++ out_be32(&mmdc->mdctl, 0x85180000); ++ ++ /* dram init sequence: update MRs */ ++ out_be32(&mmdc->mdscr, 0x00088032); ++ out_be32(&mmdc->mdscr, 0x00008033); ++ out_be32(&mmdc->mdscr, 0x00048031); ++ out_be32(&mmdc->mdscr, 0x19308030); ++ ++ /* dram init sequence: ZQCL */ ++ out_be32(&mmdc->mdscr, 0x04008040); ++ out_be32(&mmdc->mpzqhwctrl, 0xa1390003); ++ ++ mdelay(100); ++ ++ /* Calibrations now: wr lvl */ ++ out_be32(&mmdc->mdscr, 0x00848031); ++ out_be32(&mmdc->mdscr, 0x00008200); ++ out_be32(&mmdc->mpwlgcr, 0x00000001); ++ ++ mdelay(100); ++ ++ out_be32(&mmdc->mdscr, 0x00048031); ++ out_be32(&mmdc->mdscr, 0x00008000); ++ ++ /* manual_refresh */ ++ out_be32(&mmdc->mdscr, 0x00008020); ++ ++ mdelay(100); ++ ++ /* Calibrations now: Read DQS gating calibration */ ++ out_be32(&mmdc->mdscr, 0x04008050); ++ out_be32(&mmdc->mdscr, 0x00048033); ++ out_be32(&mmdc->mppdcmpr2, 0x00000001); ++ out_be32(&mmdc->mprddlctl, 0x40404040); ++ out_be32(&mmdc->mpdgctrl0, 0x10000000); ++ ++ mdelay(100); ++ ++ out_be32(&mmdc->mdscr, 0x00008033); ++ ++ /* manual_refresh */ ++ out_be32(&mmdc->mdscr, 0x00008020); ++ ++ mdelay(100); ++ ++ /* Calibrations now: Read calibration */ ++ out_be32(&mmdc->mdscr, 0x04008050); ++ out_be32(&mmdc->mdscr, 0x00048033); ++ out_be32(&mmdc->mppdcmpr2, 0x00000001); ++ out_be32(&mmdc->mprddlhwctl, 0x00000010); ++ ++ mdelay(400); ++ ++ out_be32(&mmdc->mdscr, 0x00008033); ++ ++ /* manual_refresh */ ++ out_be32(&mmdc->mdscr, 0x00008020); ++ ++ mdelay(100); ++ ++ /* PD, SR */ ++ out_be32(&mmdc->mdpdc, 0x00030035); ++ out_be32(&mmdc->mapsr, 0x00001067); ++ ++ /* refresh scheme */ ++ out_be32(&mmdc->mdref, 0x103e8000); ++ ++ mdelay(400); ++ ++ /* disable CON_REQ */ ++ out_be32(&mmdc->mdscr, 0x0); ++ ++ mdelay(50); ++} ++ ++int dram_init(void) ++{ ++ mmdc_init(); ++ ++ gd->ram_size = 0x40000000; ++ ++ return 0; ++} ++ ++int board_early_init_f(void) ++{ ++ fsl_lsch2_early_init_f(); ++ ++ return 0; ++} ++ ++int board_init(void) ++{ ++ struct ccsr_cci400 *cci = (struct ccsr_cci400 *) ++ CONFIG_SYS_CCI400_ADDR; ++ ++ /* Set CCI-400 control override register to enable barrier ++ * transaction */ ++ out_le32(&cci->ctrl_ord, ++ CCI400_CTRLORD_EN_BARRIER); ++ ++#ifdef CONFIG_LAYERSCAPE_NS_ACCESS ++ enable_layerscape_ns_access(); ++#endif ++ ++#ifdef CONFIG_ENV_IS_NOWHERE ++ gd->env_addr = (ulong)&default_environment[0]; ++#endif ++ return 0; ++} ++ ++int board_eth_init(bd_t *bis) ++{ ++ return pci_eth_init(bis); ++} ++ ++#ifdef CONFIG_OF_BOARD_SETUP ++int ft_board_setup(void *blob, bd_t *bd) ++{ ++ u64 base[CONFIG_NR_DRAM_BANKS]; ++ u64 size[CONFIG_NR_DRAM_BANKS]; ++ ++ /* fixup DT for the two DDR banks */ ++ base[0] = gd->bd->bi_dram[0].start; ++ size[0] = gd->bd->bi_dram[0].size; ++ base[1] = gd->bd->bi_dram[1].start; ++ size[1] = gd->bd->bi_dram[1].size; ++ ++ fdt_fixup_memory_banks(blob, base, size, 2); ++ ft_cpu_setup(blob, bd); ++ ++ return 0; ++} ++#endif +diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h +new file mode 100644 +index 0000000..584f604 +--- /dev/null ++++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h +@@ -0,0 +1,35 @@ ++/* ++ * Copyright 2016 Freescale Semiconductor, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __LS1043AQDS_QIXIS_H__ ++#define __LS1043AQDS_QIXIS_H__ ++ ++/* Definitions of QIXIS Registers for LS1043AQDS */ ++ ++/* BRDCFG4[4:7] select EC1 and EC2 as a pair */ ++#define BRDCFG4_EMISEL_MASK 0xe0 ++#define BRDCFG4_EMISEL_SHIFT 5 ++ ++/* SYSCLK */ ++#define QIXIS_SYSCLK_66 0x0 ++#define QIXIS_SYSCLK_83 0x1 ++#define QIXIS_SYSCLK_100 0x2 ++#define QIXIS_SYSCLK_125 0x3 ++#define QIXIS_SYSCLK_133 0x4 ++ ++/* DDRCLK */ ++#define QIXIS_DDRCLK_66 0x0 ++#define QIXIS_DDRCLK_100 0x1 ++#define QIXIS_DDRCLK_125 0x2 ++#define QIXIS_DDRCLK_133 0x3 ++ ++/* BRDCFG2 - SD clock*/ ++#define QIXIS_SDCLK1_100 0x0 ++#define QIXIS_SDCLK1_125 0x1 ++#define QIXIS_SDCLK1_165 0x2 ++#define QIXIS_SDCLK1_100_SP 0x3 ++ ++#endif +diff --git a/configs/ls1012aqds_qspi_defconfig b/configs/ls1012aqds_qspi_defconfig +new file mode 100644 +index 0000000..ef2c0ad +--- /dev/null ++++ b/configs/ls1012aqds_qspi_defconfig +@@ -0,0 +1,10 @@ ++CONFIG_ARM=y ++CONFIG_TARGET_LS1012AQDS=y ++CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" ++# CONFIG_CMD_IMLS is not set ++CONFIG_SYS_NS16550=y ++CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds" ++CONFIG_OF_CONTROL=y ++CONFIG_DM=y ++CONFIG_SPI_FLASH=y ++CONFIG_DM_SPI=y +diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h +new file mode 100644 +index 0000000..9ed04f9 +--- /dev/null ++++ b/include/configs/ls1012a_common.h +@@ -0,0 +1,239 @@ ++/* ++ * Copyright (C) 2015 Freescale Semiconductor ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __LS1012A_COMMON_H ++#define __LS1012A_COMMON_H ++ ++#define CONFIG_FSL_LAYERSCAPE ++#define CONFIG_FSL_LSCH2 ++#define CONFIG_LS1012A ++#define CONFIG_GICV2 ++ ++#define CONFIG_SYS_HAS_SERDES ++ ++#include <asm/arch/config.h> ++#define CONFIG_SYS_NO_FLASH ++ ++#define CONFIG_SUPPORT_RAW_INITRD ++ ++#define CONFIG_DISPLAY_BOARDINFO_LATE ++ ++#define CONFIG_SYS_TEXT_BASE 0x40100000 ++ ++#define CONFIG_SYS_FSL_CLK ++#define CONFIG_SYS_CLK_FREQ 100000000 ++#define CONFIG_DDR_CLK_FREQ 125000000 ++ ++#define CONFIG_SKIP_LOWLEVEL_INIT ++#define CONFIG_BOARD_EARLY_INIT_F 1 ++ ++#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) ++#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) ++ ++#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 ++#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 ++#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE ++ ++/* Generic Timer Definitions */ ++#define COUNTER_FREQUENCY 25000000 /* 12MHz */ ++ ++/* CSU */ ++#define CONFIG_LAYERSCAPE_NS_ACCESS ++ ++/* Size of malloc() pool */ ++#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) ++ ++/*SPI device */ ++#ifdef CONFIG_QSPI_BOOT ++#define CONFIG_SYS_QE_FW_IN_SPIFLASH ++#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000 ++#define CONFIG_ENV_SPI_BUS 0 ++#define CONFIG_ENV_SPI_CS 0 ++#define CONFIG_ENV_SPI_MAX_HZ 1000000 ++#define CONFIG_ENV_SPI_MODE 0x03 ++#define CONFIG_CMD_SF ++#define CONFIG_SPI_FLASH_SPANSION ++#define CONFIG_SPI_FLASH_ATMEL ++#define CONFIG_FSL_SPI_INTERFACE ++#define CONFIG_SF_DATAFLASH ++ ++#define CONFIG_FSL_QSPI ++#define QSPI0_AMBA_BASE 0x40000000 ++#define CONFIG_SPI_FLASH_SPANSION ++#define CONFIG_DM_SPI_FLASH ++#define CONFIG_SPI_FLASH_BAR ++ ++#define FSL_QSPI_FLASH_SIZE (1 << 24) ++#define FSL_QSPI_FLASH_NUM 2 ++ ++/* ++ * Environment ++ */ ++#define CONFIG_ENV_OVERWRITE ++ ++#define CONFIG_ENV_IS_IN_SPI_FLASH ++#define CONFIG_ENV_SIZE 0x40000 /* 256KB */ ++#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */ ++#define CONFIG_ENV_SECT_SIZE 0x40000 ++#endif ++ ++/* I2C */ ++#if !defined(CONFIG_EMU) ++#define CONFIG_CMD_I2C ++#define CONFIG_SYS_I2C ++#define CONFIG_SYS_I2C_MXC ++#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ ++#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ ++#endif /* CONFIG_EMU */ ++ ++/* MMC */ ++#if !defined(CONFIG_EMU) ++#define CONFIG_MMC ++#ifdef CONFIG_MMC ++#define CONFIG_CMD_MMC ++#define CONFIG_FSL_ESDHC ++#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 ++#define CONFIG_GENERIC_MMC ++#define CONFIG_CMD_FAT ++#define CONFIG_DOS_PARTITION ++#endif ++#endif /* CONFIG_EMU */ ++ ++/* SATA */ ++#if !defined(CONFIG_EMU) ++#define CONFIG_LIBATA ++#define CONFIG_SCSI_AHCI ++#define CONFIG_SCSI_AHCI_PLAT ++#define CONFIG_CMD_SCSI ++#define CONFIG_CMD_FAT ++#define CONFIG_CMD_EXT2 ++#define CONFIG_DOS_PARTITION ++#define CONFIG_BOARD_LATE_INIT ++ ++#define CONFIG_SYS_SATA AHCI_BASE_ADDR ++ ++#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1 ++#define CONFIG_SYS_SCSI_MAX_LUN 1 ++#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ ++ CONFIG_SYS_SCSI_MAX_LUN) ++ ++#define CONFIG_PCI /* Enable PCI/PCIE */ ++#define CONFIG_PCIE1 /* PCIE controller 1 */ ++#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ ++#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie" ++ ++#define CONFIG_SYS_PCI_64BIT ++ ++#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 ++#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ ++#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 ++#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ ++ ++#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 ++#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 ++#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ ++ ++#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 ++#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 ++#define CONFIG_SYS_PCIE_MEM_SIZE 0x80000000 /* 128M */ ++ ++#define CONFIG_NET_MULTI ++#define CONFIG_PCI_PNP ++#define CONFIG_E1000 ++#define CONFIG_PCI_SCAN_SHOW ++#define CONFIG_CMD_PCI ++#endif ++ ++#define CONFIG_CONS_INDEX 1 ++#define CONFIG_SYS_NS16550_SERIAL ++#define CONFIG_SYS_NS16550_REG_SIZE 1 ++#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) ++ ++#ifdef CONFIG_EMU ++#define CONFIG_BAUDRATE 3000 ++#else ++#define CONFIG_BAUDRATE 115200 ++#endif ++#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } ++ ++/* Command line configuration */ ++#define CONFIG_CMD_CACHE ++#define CONFIG_CMD_DHCP ++#define CONFIG_CMD_ENV ++#define CONFIG_CMD_GREPENV ++#define CONFIG_CMD_MII ++#define CONFIG_CMD_PING ++#undef CONFIG_CMD_IMLS ++ ++ ++#define CONFIG_ARCH_EARLY_INIT_R ++ ++#define CONFIG_SYS_HZ 1000 ++ ++#define CONFIG_HWCONFIG ++#define HWCONFIG_BUFFER_SIZE 128 ++ ++#define CONFIG_DISPLAY_CPUINFO ++ ++/* Initial environment variables */ ++#define CONFIG_EXTRA_ENV_SETTINGS \ ++ "initrd_high=0xffffffff\0" \ ++ "verify=no\0" \ ++ "hwconfig=fsl_ddr:bank_intlv=auto\0" \ ++ "loadaddr=0x80100000\0" \ ++ "kernel_addr=0x100000\0" \ ++ "ramdisk_addr=0x800000\0" \ ++ "ramdisk_size=0x2000000\0" \ ++ "fdt_high=0xffffffffffffffff\0" \ ++ "initrd_high=0xffffffffffffffff\0" \ ++ "kernel_start=0xa00000\0" \ ++ "kernel_load=0xa0000000\0" \ ++ "kernel_size=0x2800000\0" \ ++ "console=ttyAMA0,38400n8\0" ++ ++#ifdef CONFIG_EMU ++#define CONFIG_BOOTARGS "console=ttyS2,115200 root=/dev/ram0 " \ ++ "earlycon=uart8250,mmio,0x21d0500,115200n8" ++/* Kernel image should be pre-loaded to address kernel_load */ ++#define CONFIG_BOOTCOMMAND "bootm $kernel_load" ++#else ++#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ ++ "earlycon=uart8250,mmio,0x21c0500" ++#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\ ++ "$kernel_start $kernel_size && "\ ++ "bootm $kernel_load" ++#endif ++#define CONFIG_BOOTDELAY 10 ++ ++/* Monitor Command Prompt */ ++#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ ++#define CONFIG_SYS_PROMPT "=> " ++#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ ++ sizeof(CONFIG_SYS_PROMPT) + 16) ++#define CONFIG_SYS_HUSH_PARSER ++#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " ++#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ ++#define CONFIG_SYS_LONGHELP ++#define CONFIG_CMDLINE_EDITING 1 ++#define CONFIG_AUTO_COMPLETE ++#define CONFIG_SYS_MAXARGS 64 /* max command args */ ++ ++#define CONFIG_PANIC_HANG ++#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ ++ ++/* Flat Device Tree Definitions */ ++#define CONFIG_OF_LIBFDT ++#define CONFIG_OF_BOARD_SETUP ++ ++/* new uImage format support */ ++#define CONFIG_FIT ++#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ ++#define CONFIG_CMD_BOOTZ ++#define CONFIG_CMDLINE_TAG ++ ++#include <asm/fsl_secure_boot.h> ++ ++#endif /* __LS1012A_COMMON_H */ +diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h +new file mode 100644 +index 0000000..6346d3e +--- /dev/null ++++ b/include/configs/ls1012aqds.h +@@ -0,0 +1,133 @@ ++/* ++ * Copyright 2016 Freescale Semiconductor, Inc. ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ */ ++ ++#ifndef __LS1012AQDS_H__ ++#define __LS1012AQDS_H__ ++ ++#include "ls1012a_common.h" ++ ++ ++#define CONFIG_DIMM_SLOTS_PER_CTLR 1 ++#define CONFIG_CHIP_SELECTS_PER_CTRL 1 ++#define CONFIG_NR_DRAM_BANKS 2 ++ ++#ifdef CONFIG_SYS_DPAA_FMAN ++#define CONFIG_FMAN_ENET ++#define CONFIG_PHYLIB ++#define CONFIG_PHY_VITESSE ++#define CONFIG_PHY_REALTEK ++#define RGMII_PHY1_ADDR 0x1 ++#define SGMII_CARD_PORT1_PHY_ADDR 0x1C ++#define SGMII_CARD_PORT2_PHY_ADDR 0x1D ++#define SGMII_CARD_PORT3_PHY_ADDR 0x1E ++#define SGMII_CARD_PORT4_PHY_ADDR 0x1F ++#endif ++ ++#define CONFIG_QIXIS_I2C_ACCESS ++ ++/* ++ * I2C bus multiplexer ++ */ ++#define I2C_MUX_PCA_ADDR_PRI 0x77 ++#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */ ++#define I2C_RETIMER_ADDR 0x18 ++#define I2C_MUX_CH_DEFAULT 0x8 ++#define I2C_MUX_CH_CH7301 0xC ++#define I2C_MUX_CH5 0xD ++#define I2C_MUX_CH7 0xF ++ ++#define I2C_MUX_CH_VOL_MONITOR 0xa ++ ++/* ++* RTC configuration ++*/ ++#define RTC ++#define CONFIG_RTC_PCF8563 1 ++#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ ++#define CONFIG_CMD_DATE ++ ++/* EEPROM */ ++#define CONFIG_ID_EEPROM ++#define CONFIG_CMD_EEPROM ++#define CONFIG_SYS_I2C_EEPROM_NXID ++#define CONFIG_SYS_EEPROM_BUS_NUM 0 ++#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 ++#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 ++#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 ++#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 ++ ++ ++/* Voltage monitor on channel 2*/ ++#define I2C_VOL_MONITOR_ADDR 0x40 ++#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2 ++#define I2C_VOL_MONITOR_BUS_V_OVF 0x1 ++#define I2C_VOL_MONITOR_BUS_V_SHIFT 3 ++ ++/* DSPI */ ++#define CONFIG_FSL_DSPI ++#define CONFIG_FSL_DSPI1 ++#define CONFIG_DEFAULT_SPI_BUS 1 ++ ++#define CONFIG_CMD_SPI ++#define MMAP_DSPI DSPI1_BASE_ADDR ++ ++#define CONFIG_SYS_DSPI_CTAR0 1 ++ ++#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ ++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ ++ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ ++ DSPI_CTAR_DT(0)) ++#define CONFIG_SPI_FLASH_SST /* cs1 */ ++ ++#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ ++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ ++ DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \ ++ DSPI_CTAR_DT(0)) ++#define CONFIG_SPI_FLASH_STMICRO /* cs2 */ ++ ++#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\ ++ DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \ ++ DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \ ++ DSPI_CTAR_DT(0)) ++#define CONFIG_SPI_FLASH_EON /* cs3 */ ++ ++#define CONFIG_SF_DEFAULT_SPEED 10000000 ++#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 ++#define CONFIG_SF_DEFAULT_BUS 1 ++#define CONFIG_SF_DEFAULT_CS 0 ++ ++/* ++* USB ++*/ ++/* EHCI Support - disbaled by default */ ++/*#define CONFIG_HAS_FSL_DR_USB*/ ++ ++#ifdef CONFIG_HAS_FSL_DR_USB ++#define CONFIG_USB_EHCI ++#define CONFIG_USB_EHCI_FSL ++#define CONFIG_EHCI_HCD_INIT_AFTER_RESET ++#endif ++ ++/*XHCI Support - enabled by default*/ ++#define CONFIG_HAS_FSL_XHCI_USB ++ ++#ifdef CONFIG_HAS_FSL_XHCI_USB ++#define CONFIG_USB_XHCI ++#define CONFIG_USB_XHCI_FSL ++#define CONFIG_USB_XHCI_DWC3 ++#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 ++#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 ++#define CONFIG_CMD_USB ++#define CONFIG_USB_STORAGE ++#define CONFIG_CMD_EXT2 ++#endif ++ ++#define CONFIG_CMD_MEMINFO ++#define CONFIG_CMD_MEMTEST ++#define CONFIG_SYS_MEMTEST_START 0x80000000 ++#define CONFIG_SYS_MEMTEST_END 0x9fffffff ++ ++#endif /* __LS1012AQDS_H__ */ +diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h +index 3df822e..d47e625 100644 +--- a/include/fsl_mmdc.h ++++ b/include/fsl_mmdc.h +@@ -25,29 +25,70 @@ struct mmdc_p_regs { + u32 mdcfg3lp; + u32 mdmr4; + u32 mdasp; +- u32 res3[239]; ++ u32 res2[239]; + u32 maarcr; + u32 mapsr; +- u32 res4[254]; ++ u32 maexidr0; ++ u32 maexidr1; ++ u32 madpcr0; ++ u32 madpcr1; ++ u32 madpsr0; ++ u32 madpsr1; ++ u32 madpsr2; ++ u32 madpsr3; ++ u32 madpsr4; ++ u32 madpsr5; ++ u32 masbs0; ++ u32 masbs1; ++ u32 res3[2]; ++ u32 magenp; ++ u32 res4[239]; + u32 mpzqhwctrl; +- u32 res5[2]; ++ u32 mpzqswctrl; ++ u32 mpwlgcr; + u32 mpwldectrl0; + u32 mpwldectrl1; +- u32 res6; ++ u32 mpwldlst; + u32 mpodtctrl; + u32 mprddqby0dl; + u32 mprddqby1dl; + u32 mprddqby2dl; + u32 mprddqby3dl; +- u32 res7[4]; ++ u32 res5[4]; + u32 mpdgctrl0; + u32 mpdgctrl1; +- u32 res8; ++ u32 mpdgdlst0; + u32 mprddlctl; +- u32 res9; ++ u32 mprddlst; + u32 mpwrdlctl; +- u32 res10[25]; ++ u32 mpwrdlst; ++ u32 mpsdctrl; ++ u32 mpzqlp2ctl; ++ u32 mprddlhwctl; ++ u32 mpwrdlhwctl; ++ u32 mprddlhwst0; ++ u32 mprddlhwst1; ++ u32 mpwrdlhwst0; ++ u32 mpwrdlhwst1; ++ u32 mpwlhwerr; ++ u32 mpdghwst0; ++ u32 mpdghwst1; ++ u32 mpdghwst2; ++ u32 mpdghwst3; ++ u32 mppdcmpr1; ++ u32 mppdcmpr2; ++ u32 mpswdar0; ++ u32 mpswdrdr0; ++ u32 mpswdrdr1; ++ u32 mpswdrdr2; ++ u32 mpswdrdr3; ++ u32 mpswdrdr4; ++ u32 mpswdrdr5; ++ u32 mpswdrdr6; ++ u32 mpswdrdr7; + u32 mpmur0; ++ u32 mpwrcadl; ++ u32 mpdccr; + }; + + #endif /* FSL_MMDC_H */ +-- +1.7.9.5 + |