diff options
Diffstat (limited to 'package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch')
| -rw-r--r-- | package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch | 634 |
1 files changed, 0 insertions, 634 deletions
diff --git a/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch b/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch deleted file mode 100644 index 1c23602..0000000 --- a/package/boot/uboot-layerscape/patches/0015-armv8-ls1012a-Add-support-of-ls1012ardb-board.patch +++ /dev/null @@ -1,634 +0,0 @@ -From 4bb641f4d28053bd1ff4af73dc0a63be2151f851 Mon Sep 17 00:00:00 2001 -From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> -Date: Mon, 25 Apr 2016 14:37:33 +0530 -Subject: [PATCH 15/93] armv8: ls1012a: Add support of ls1012ardb board - -QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance -development platform, with a complete debugging environment. -The LS1012ARDB board supports the QorIQ LS1012A processor and is -optimized to support the high-bandwidth DDR3L memory and -a full complement of high-speed SerDes ports. - -Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> -Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> ---- - arch/arm/Kconfig | 10 ++ - arch/arm/dts/Makefile | 3 +- - arch/arm/dts/fsl-ls1012a-rdb.dts | 16 +++ - arch/arm/dts/fsl-ls1012a-rdb.dtsi | 39 ++++++ - board/freescale/ls1012ardb/Kconfig | 15 +++ - board/freescale/ls1012ardb/MAINTAINERS | 6 + - board/freescale/ls1012ardb/Makefile | 7 + - board/freescale/ls1012ardb/README | 89 +++++++++++++ - board/freescale/ls1012ardb/ls1012ardb.c | 220 +++++++++++++++++++++++++++++++ - configs/ls1012ardb_qspi_defconfig | 10 ++ - include/configs/ls1012a_common.h | 3 +- - include/configs/ls1012ardb.h | 61 +++++++++ - include/linux/usb/xhci-fsl.h | 2 +- - 13 files changed, 477 insertions(+), 4 deletions(-) - create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dts - create mode 100644 arch/arm/dts/fsl-ls1012a-rdb.dtsi - create mode 100644 board/freescale/ls1012ardb/Kconfig - create mode 100644 board/freescale/ls1012ardb/MAINTAINERS - create mode 100644 board/freescale/ls1012ardb/Makefile - create mode 100644 board/freescale/ls1012ardb/README - create mode 100644 board/freescale/ls1012ardb/ls1012ardb.c - create mode 100644 configs/ls1012ardb_qspi_defconfig - create mode 100644 include/configs/ls1012ardb.h - -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index f5033db..5c20801 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -656,6 +656,15 @@ config TARGET_LS1012AQDS - development platform that supports the QorIQ LS1012A - Layerscape Architecture processor. - -+config TARGET_LS1012ARDB -+ bool "Support ls1012ardb" -+ select ARM64 -+ help -+ Support for Freescale LS1012ARDB platform. -+ The LS1012A Reference design board (RDB) is a high-performance -+ development platform that supports the QorIQ LS1012A -+ Layerscape Architecture processor. -+ - config TARGET_LS1021AQDS - bool "Support ls1021aqds" - select CPU_V7 -@@ -802,6 +811,7 @@ source "board/freescale/ls1043aqds/Kconfig" - source "board/freescale/ls1021atwr/Kconfig" - source "board/freescale/ls1043ardb/Kconfig" - source "board/freescale/ls1012aqds/Kconfig" -+source "board/freescale/ls1012ardb/Kconfig" - source "board/freescale/mx23evk/Kconfig" - source "board/freescale/mx25pdk/Kconfig" - source "board/freescale/mx28evk/Kconfig" -diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index ed5eb38..9e8137b 100644 ---- a/arch/arm/dts/Makefile -+++ b/arch/arm/dts/Makefile -@@ -95,7 +95,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ - dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ - fsl-ls1043a-qds-lpuart.dtb \ - fsl-ls1043a-rdb.dtb \ -- fsl-ls1012a-qds.dtb -+ fsl-ls1012a-qds.dtb \ -+ fsl-ls1012a-rdb.dtb - - dtb-$(CONFIG_MACH_SUN4I) += \ - sun4i-a10-a1000.dtb \ -diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dts b/arch/arm/dts/fsl-ls1012a-rdb.dts -new file mode 100644 -index 0000000..4ec9786 ---- /dev/null -+++ b/arch/arm/dts/fsl-ls1012a-rdb.dts -@@ -0,0 +1,16 @@ -+/* -+ * Device Tree file for Freescale Layerscape-1012A family SoC. -+ * -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+/dts-v1/; -+#include "fsl-ls1012a-rdb.dtsi" -+ -+/ { -+ chosen { -+ stdout-path = &duart0; -+ }; -+}; -diff --git a/arch/arm/dts/fsl-ls1012a-rdb.dtsi b/arch/arm/dts/fsl-ls1012a-rdb.dtsi -new file mode 100644 -index 0000000..71aba78 ---- /dev/null -+++ b/arch/arm/dts/fsl-ls1012a-rdb.dtsi -@@ -0,0 +1,39 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1012A family SoC. -+ * -+ * Copyright (C) 2016, Freescale Semiconductor -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+/include/ "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A RDB Board"; -+ aliases { -+ spi0 = &qspi; -+ }; -+}; -+ -+&qspi { -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fl128s@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spi-flash"; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig -new file mode 100644 -index 0000000..3f67c28 ---- /dev/null -+++ b/board/freescale/ls1012ardb/Kconfig -@@ -0,0 +1,15 @@ -+if TARGET_LS1012ARDB -+ -+config SYS_BOARD -+ default "ls1012ardb" -+ -+config SYS_VENDOR -+ default "freescale" -+ -+config SYS_SOC -+ default "fsl-layerscape" -+ -+config SYS_CONFIG_NAME -+ default "ls1012ardb" -+ -+endif -diff --git a/board/freescale/ls1012ardb/MAINTAINERS b/board/freescale/ls1012ardb/MAINTAINERS -new file mode 100644 -index 0000000..757e810 ---- /dev/null -+++ b/board/freescale/ls1012ardb/MAINTAINERS -@@ -0,0 +1,6 @@ -+LS1012ARDB BOARD -+M: -+S: Maintained -+F: board/freescale/ls1012ardb/ -+F: include/configs/ls1012ardb.h -+F: configs/ls1012ardb_defconfig -diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile -new file mode 100644 -index 0000000..05fa9d9 ---- /dev/null -+++ b/board/freescale/ls1012ardb/Makefile -@@ -0,0 +1,7 @@ -+# -+# Copyright 2016 Freescale Semiconductor, Inc. -+# -+# SPDX-License-Identifier: GPL-2.0+ -+# -+ -+obj-y += ls1012ardb.o -diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README -new file mode 100644 -index 0000000..cda03f6 ---- /dev/null -+++ b/board/freescale/ls1012ardb/README -@@ -0,0 +1,89 @@ -+Overview -+-------- -+The LS1012ARDB power supplies (PS) provide all the voltages necessary -+for the correct operation of the LS1012A processor, DDR3L, QSPI memory, -+and other onboard peripherals. -+ -+LS1012A SoC Overview -+-------------------- -+The LS1012A features an advanced 64-bit ARM v8 Cortex- -+A53 processor, with 32 KB of parity protected L1-I cache, -+32 KB of ECC protected L1-D cache, as well as 256 KB of -+ECC protected L2 cache. -+ -+The LS1012A SoC includes the following function and features: -+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities: -+ - ARM v8 cryptography extensions -+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports -+ 16-/8-bit operation (no ECC support) -+ - ARM core-link CCI-400 cache coherent interconnect -+ - Packet Forwarding Engine (PFE) -+ - Cryptography acceleration (SEC) -+ - Ethernet interfaces supported by PFE: -+ - One Configurable x3 SerDes: -+ Two Serdes PLLs supported for usage by any SerDes data lane -+ Support for up to 6 GBaud operation -+ - High-speed peripheral interfaces: -+ - One PCI Express Gen2 controller, supporting x1 operation -+ - One serial ATA (SATA Gen 3.0) controller -+ - One USB 3.0/2.0 controller with integrated PHY -+ - One USB 2.0 controller with ULPI interface. . -+ - Additional peripheral interfaces: -+ - One quad serial peripheral interface (QuadSPI) controller -+ - One serial peripheral interface (SPI) controller -+ - Two enhanced secure digital host controllers -+ - Two I2C controllers -+ - One 16550 compliant DUART (two UART interfaces) -+ - Two general purpose IOs (GPIO) -+ - Two FlexTimers -+ - Five synchronous audio interfaces (SAI) -+ - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading -+ - Single-source clocking solution enabling generation of core, platform, -+ DDR, SerDes, and USB clocks from a single external crystal and internal -+ crystaloscillator -+ - Thermal monitor unit (TMU) with +/- 3C accuracy -+ - Two WatchDog timers -+ - ARM generic timer -+ - QorIQ platform's trust architecture 2.1 -+ -+ LS1012ARDB board Overview -+ ----------------------- -+ - SERDES Connections, 4 lanes supporting: -+ - PCI Express - 3.0 -+ - SGMII, SGMII 2.5 -+ - SATA 3.0 -+ - DDR Controller -+ - 6-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s -+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select -+ signals to -+ - QSPI NOR flash memory (2 virtual banks) -+ - the QSPI emulator.s -+ - USB 3.0 -+ - one high-speed USB 2.0/3.0 port. -+ - Two enhanced secure digital host controllers: -+ - SDHC1 controller can be connected to onboard SDHC connector -+ - SDHC2 controller: Three dual 1:4 mux/demux devices, -+ 74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC, -+ SDIO WiFi, SPI, and Ardiuno shield -+ - 2 I2C controllers -+ - One SATA onboard connectors -+ - UART -+ - The LS1012A processor consists of two UART controllers, -+ out of which only UART1 is used on RDB. -+ - ARM JTAG support -+ -+Booting Options -+--------------- -+a) QSPI Flash Emu Boot -+b) QSPI Flash 1 -+c) QSPI Flash 2 -+ -+QSPI flash map -+-------------- -+Images | Size |QSPI Flash Address -+------------------------------------------ -+RCW + PBI | 1MB | 0x4000_0000 -+U-boot | 1MB | 0x4010_0000 -+U-boot Env | 1MB | 0x4020_0000 -+PPA FIT image | 2MB | 0x4050_0000 -+Linux ITB | ~53MB | 0x40A0_0000 -diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c -new file mode 100644 -index 0000000..4a7aaaa ---- /dev/null -+++ b/board/freescale/ls1012ardb/ls1012ardb.c -@@ -0,0 +1,220 @@ -+/* -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#include <common.h> -+#include <i2c.h> -+#include <asm/io.h> -+#include <asm/arch/clock.h> -+#include <asm/arch/fsl_serdes.h> -+#include <asm/arch/ppa.h> -+#include <asm/arch/soc.h> -+#include <hwconfig.h> -+#include <ahci.h> -+#include <mmc.h> -+#include <scsi.h> -+#include <fsl_csu.h> -+#include <fsl_esdhc.h> -+#include <environment.h> -+#include <fsl_mmdc.h> -+#include <netdev.h> -+ -+DECLARE_GLOBAL_DATA_PTR; -+ -+int checkboard(void) -+{ -+ u8 in1; -+ -+ puts("Board: LS1012ARDB "); -+ -+ /* Initialize i2c early for Serial flash bank information */ -+ i2c_set_bus_num(0); -+ -+ if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) { -+ printf("Error reading i2c boot information!\n"); -+ return 0; /* Don't want to hang() on this error */ -+ } -+ -+ puts("Version"); -+ if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A) -+ puts(": RevA"); -+ else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B) -+ puts(": RevB"); -+ else -+ puts(": unknown"); -+ -+ printf(", boot from QSPI"); -+ if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU) -+ puts(": emu\n"); -+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1) -+ puts(": bank1\n"); -+ else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2) -+ puts(": bank2\n"); -+ else -+ puts("unknown\n"); -+ -+ return 0; -+} -+ -+void mmdc_init(void) -+{ -+ struct mmdc_p_regs *mmdc = -+ (struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR; -+ -+ /* Set MMDC_MDSCR[CON_REQ] */ -+ out_be32(&mmdc->mdscr, 0x00008000); -+ -+ /* configure timing parms */ -+ out_be32(&mmdc->mdotc, 0x12554000); -+ out_be32(&mmdc->mdcfg0, 0xbabf7954); -+ out_be32(&mmdc->mdcfg1, 0xff328f64); -+ out_be32(&mmdc->mdcfg2, 0x01ff00db); -+ -+ /* other parms */ -+ out_be32(&mmdc->mdmisc, 0x00000680); -+ out_be32(&mmdc->mpmur0, 0x00000800); -+ out_be32(&mmdc->mdrwd, 0x00002000); -+ out_be32(&mmdc->mpodtctrl, 0x0000022a); -+ -+ /* out of reset delays */ -+ out_be32(&mmdc->mdor, 0x00bf1023); -+ -+ /* physical parms */ -+ out_be32(&mmdc->mdctl, 0x05180000); -+ out_be32(&mmdc->mdasp, 0x0000007f); -+ -+ /* Enable MMDC */ -+ out_be32(&mmdc->mdctl, 0x85180000); -+ -+ /* dram init sequence: update MRs */ -+ out_be32(&mmdc->mdscr, 0x00088032); -+ out_be32(&mmdc->mdscr, 0x00008033); -+ out_be32(&mmdc->mdscr, 0x00048031); -+ out_be32(&mmdc->mdscr, 0x19308030); -+ -+ /* dram init sequence: ZQCL */ -+ out_be32(&mmdc->mdscr, 0x04008040); -+ out_be32(&mmdc->mpzqhwctrl, 0xa1390003); -+ -+ mdelay(100); -+ -+ /* Calibrations now: wr lvl */ -+ out_be32(&mmdc->mdscr, 0x00848031); -+ out_be32(&mmdc->mdscr, 0x00008200); -+ out_be32(&mmdc->mpwlgcr, 0x00000001); -+ -+ mdelay(100); -+ -+ out_be32(&mmdc->mdscr, 0x00048031); -+ out_be32(&mmdc->mdscr, 0x00008000); -+ -+ /* manual_refresh */ -+ out_be32(&mmdc->mdscr, 0x00008020); -+ -+ mdelay(100); -+ -+ /* Calibrations now: Read DQS gating calibration */ -+ out_be32(&mmdc->mdscr, 0x04008050); -+ out_be32(&mmdc->mdscr, 0x00048033); -+ out_be32(&mmdc->mppdcmpr2, 0x00000001); -+ out_be32(&mmdc->mprddlctl, 0x40404040); -+ out_be32(&mmdc->mpdgctrl0, 0x10000000); -+ -+ mdelay(100); -+ -+ out_be32(&mmdc->mdscr, 0x00008033); -+ -+ /* manual_refresh */ -+ out_be32(&mmdc->mdscr, 0x00008020); -+ -+ mdelay(100); -+ -+ /* Calibrations now: Read calibration */ -+ out_be32(&mmdc->mdscr, 0x04008050); -+ out_be32(&mmdc->mdscr, 0x00048033); -+ out_be32(&mmdc->mppdcmpr2, 0x00000001); -+ out_be32(&mmdc->mprddlhwctl, 0x00000010); -+ -+ mdelay(400); -+ -+ out_be32(&mmdc->mdscr, 0x00008033); -+ -+ /* manual_refresh */ -+ out_be32(&mmdc->mdscr, 0x00008020); -+ -+ mdelay(100); -+ -+ /* PD, SR */ -+ out_be32(&mmdc->mdpdc, 0x00030035); -+ out_be32(&mmdc->mapsr, 0x00001067); -+ -+ /* refresh scheme */ -+ out_be32(&mmdc->mdref, 0x103e8000); -+ -+ mdelay(400); -+ -+ /* disable CON_REQ */ -+ out_be32(&mmdc->mdscr, 0x0); -+ -+ mdelay(50); -+} -+ -+int dram_init(void) -+{ -+ mmdc_init(); -+ -+ gd->ram_size = 0x40000000; -+ -+ return 0; -+} -+ -+int board_eth_init(bd_t *bis) -+{ -+ return pci_eth_init(bis); -+} -+ -+int board_early_init_f(void) -+{ -+ fsl_lsch2_early_init_f(); -+ -+ return 0; -+} -+ -+int board_init(void) -+{ -+ struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; -+ /* -+ * Set CCI-400 control override register to enable barrier -+ * transaction -+ */ -+ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER); -+ -+#ifdef CONFIG_ENV_IS_NOWHERE -+ gd->env_addr = (ulong)&default_environment[0]; -+#endif -+ -+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS -+ enable_layerscape_ns_access(); -+#endif -+ -+ return 0; -+} -+ -+int ft_board_setup(void *blob, bd_t *bd) -+{ -+ u64 base[CONFIG_NR_DRAM_BANKS]; -+ u64 size[CONFIG_NR_DRAM_BANKS]; -+ -+ /* fixup DT for the two DDR banks */ -+ base[0] = gd->bd->bi_dram[0].start; -+ size[0] = gd->bd->bi_dram[0].size; -+ base[1] = gd->bd->bi_dram[1].start; -+ size[1] = gd->bd->bi_dram[1].size; -+ -+ fdt_fixup_memory_banks(blob, base, size, 2); -+ ft_cpu_setup(blob, bd); -+ -+ return 0; -+} -diff --git a/configs/ls1012ardb_qspi_defconfig b/configs/ls1012ardb_qspi_defconfig -new file mode 100644 -index 0000000..f819038 ---- /dev/null -+++ b/configs/ls1012ardb_qspi_defconfig -@@ -0,0 +1,10 @@ -+CONFIG_ARM=y -+CONFIG_TARGET_LS1012ARDB=y -+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT" -+# CONFIG_CMD_IMLS is not set -+CONFIG_SYS_NS16550=y -+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb" -+CONFIG_OF_CONTROL=y -+CONFIG_DM=y -+CONFIG_SPI_FLASH=y -+CONFIG_DM_SPI=y -diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h -index 9ed04f9..3fd360a 100644 ---- a/include/configs/ls1012a_common.h -+++ b/include/configs/ls1012a_common.h -@@ -12,7 +12,7 @@ - #define CONFIG_LS1012A - #define CONFIG_GICV2 - --#define CONFIG_SYS_HAS_SERDES -+#define CONFIG_SYS_HAS_SERDES - - #include <asm/arch/config.h> - #define CONFIG_SYS_NO_FLASH -@@ -56,7 +56,6 @@ - #define CONFIG_ENV_SPI_MODE 0x03 - #define CONFIG_CMD_SF - #define CONFIG_SPI_FLASH_SPANSION --#define CONFIG_SPI_FLASH_ATMEL - #define CONFIG_FSL_SPI_INTERFACE - #define CONFIG_SF_DATAFLASH - -diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h -new file mode 100644 -index 0000000..9ff5935 ---- /dev/null -+++ b/include/configs/ls1012ardb.h -@@ -0,0 +1,61 @@ -+/* -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ */ -+ -+#ifndef __LS1012ARDB_H__ -+#define __LS1012ARDB_H__ -+ -+#include "ls1012a_common.h" -+ -+ -+#define CONFIG_DIMM_SLOTS_PER_CTLR 1 -+#define CONFIG_CHIP_SELECTS_PER_CTRL 1 -+#define CONFIG_NR_DRAM_BANKS 2 -+ -+#define CONFIG_CMD_MEMINFO -+#define CONFIG_CMD_MEMTEST -+#define CONFIG_SYS_MEMTEST_START 0x80000000 -+#define CONFIG_SYS_MEMTEST_END 0x9fffffff -+ -+#define CONFIG_PHYLIB -+#define CONFIG_PHY_REALTEK -+#define SGMII_PHY1_ADDR 0x0 -+#define RGMII_PHY2_ADDR 0x1 -+ -+/* -+* USB -+*/ -+#define CONFIG_HAS_FSL_XHCI_USB -+ -+#ifdef CONFIG_HAS_FSL_XHCI_USB -+#define CONFIG_USB_XHCI -+#define CONFIG_USB_XHCI_FSL -+#define CONFIG_USB_XHCI_DWC3 -+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 -+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 -+#define CONFIG_CMD_USB -+#define CONFIG_USB_STORAGE -+#define CONFIG_CMD_EXT2 -+#endif -+ -+/* -+ * I2C IO expander -+ */ -+ -+#define I2C_MUX_IO1_ADDR 0x24 -+#define __SW_BOOT_MASK 0xFC -+#define __SW_BOOT_EMU 0x10 -+#define __SW_BOOT_BANK1 0x00 -+#define __SW_BOOT_BANK2 0x01 -+#define __SW_REV_MASK 0x07 -+#define __SW_REV_A 0xF8 -+#define __SW_REV_B 0xF0 -+ -+#define CONFIG_CMD_MEMINFO -+#define CONFIG_CMD_MEMTEST -+#define CONFIG_SYS_MEMTEST_START 0x80000000 -+#define CONFIG_SYS_MEMTEST_END 0x9fffffff -+ -+#endif /* __LS1012ARDB_H__ */ -diff --git a/include/linux/usb/xhci-fsl.h b/include/linux/usb/xhci-fsl.h -index 72a5d5b..7ab88c3 100644 ---- a/include/linux/usb/xhci-fsl.h -+++ b/include/linux/usb/xhci-fsl.h -@@ -62,7 +62,7 @@ struct fsl_xhci { - #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR - #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR - #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0 --#elif defined(CONFIG_LS1043A) -+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A) - #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR - #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR - #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR --- -1.7.9.5 - |