diff options
Diffstat (limited to 'package/boot/uboot-layerscape/patches')
5 files changed, 484 insertions, 0 deletions
diff --git a/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch b/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch new file mode 100644 index 0000000..ace5428 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0001-armv8-Support-loading-32-bit-OS-in-AArch32-execution.patch @@ -0,0 +1,214 @@ +From e03f571b1e9564ca422134b2013d80c8373c9db2 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Fri, 13 May 2016 10:19:24 +0800 +Subject: [PATCH 01/93] armv8: Support loading 32-bit OS in AArch32 execution + state + +To support loading a 32-bit OS, the execution state will change from +AArch64 to AArch32 when jumping to kernel. + +The architecture information will be got through checking FIT +image, then U-Boot will load 32-bit OS or 64-bit OS automatically. + +Signed-off-by: Ebony Zhu <ebony.zhu@nxp.com> +Signed-off-by: Alison Wang <alison.wang@nxp.com> +Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> +--- + arch/arm/cpu/armv8/transition.S | 100 +++++++++++++++++++++++++++++++++++++++ + arch/arm/include/asm/system.h | 2 + + arch/arm/lib/bootm.c | 20 +++++++- + common/image-fit.c | 12 ++++- + 4 files changed, 131 insertions(+), 3 deletions(-) + +diff --git a/arch/arm/cpu/armv8/transition.S b/arch/arm/cpu/armv8/transition.S +index 253a39b..9d7a17a 100644 +--- a/arch/arm/cpu/armv8/transition.S ++++ b/arch/arm/cpu/armv8/transition.S +@@ -21,3 +21,103 @@ ENTRY(armv8_switch_to_el1) + 0: ret + 1: armv8_switch_to_el1_m x0, x1 + ENDPROC(armv8_switch_to_el1) ++ ++/* ++ * x0: kernel entry point ++ * x1: machine nr ++ * x2: fdt address ++ */ ++ENTRY(armv8_switch_to_el2_aarch32) ++ switch_el x3, 1f, 0f, 0f ++0: ret ++1: ++ mov x7, x0 ++ mov x8, x1 ++ mov x9, x2 ++ ++ /* 32bit EL2 | HCE | SMD | RES1 (Bits[5:4]) | Non-secure EL0/EL1 */ ++ mov x1, 0x1b1 ++ msr scr_el3, x1 ++ msr cptr_el3, xzr /* Disable coprocessor traps to EL3 */ ++ mov x1, 0x33ff ++ msr cptr_el2, x1 /* Disable coprocessor traps to EL2 */ ++ ++ /* Initialize Generic Timers */ ++ msr cntvoff_el2, xzr ++ ++ mov x1, #0x0830 ++ movk x1, #0x30c5, lsl #16 ++ msr sctlr_el2, x1 ++ ++ /* Return to AArch32 Hypervisor mode */ ++ mov x1, sp ++ msr sp_el2, x1 ++ mrs x1, vbar_el3 ++ msr vbar_el2, x1 /* Migrate VBAR */ ++ mov x1, #0x1da ++ msr spsr_el3, x1 ++ msr elr_el3, x7 ++ ++ mov x0, #0 ++ mov x1, x8 ++ mov x2, x9 ++ ++ eret ++ENDPROC(armv8_switch_to_el2_aarch32) ++ ++/* ++ * x0: kernel entry point ++ * x1: machine nr ++ * x2: fdt address ++ */ ++ENTRY(armv8_switch_to_el1_aarch32) ++ switch_el x3, 0f, 1f, 0f ++0: ret ++1: ++ mov x7, x0 ++ mov x8, x1 ++ mov x9, x2 ++ ++ /* Initialize Generic Timers */ ++ mrs x0, cnthctl_el2 ++ orr x0, x0, #0x3 /* Enable EL1 access to timers */ ++ msr cnthctl_el2, x0 ++ msr cntvoff_el2, xzr ++ ++ /* Initialize MPID/MPIDR registers */ ++ mrs x0, midr_el1 ++ mrs x1, mpidr_el1 ++ msr vpidr_el2, x0 ++ msr vmpidr_el2, x1 ++ ++ /* Disable coprocessor traps */ ++ mov x0, #0x33ff ++ msr cptr_el2, x0 /* Disable coprocessor traps to EL2 */ ++ msr hstr_el2, xzr /* Disable coprocessor traps to EL2 */ ++ mov x0, #3 << 20 ++ msr cpacr_el1, x0 /* Enable FP/SIMD at EL1 */ ++ ++ /* Initialize HCR_EL2 */ ++ mov x0, #(0 << 31) /* 32bit EL1 */ ++ orr x0, x0, #(1 << 29) /* Disable HVC */ ++ msr hcr_el2, x0 ++ ++ mov x0, #0x0800 ++ movk x0, #0x30d0, lsl #16 ++ msr sctlr_el1, x0 ++ ++ /* Return to AArch32 Supervisor mode */ ++ mov x0, sp ++ msr sp_el1, x0 /* Migrate SP */ ++ mrs x0, vbar_el2 ++ msr vbar_el1, x0 /* Migrate VBAR */ ++ mov x0, #0x1d3 ++ msr spsr_el2, x0 ++ msr elr_el2, x7 ++ ++ mov x0, #0 ++ mov x1, x8 ++ mov x2, x9 ++ ++ eret ++ENDPROC(armv8_switch_to_el1_aarch32) +diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h +index 71b3108..0ecbcf7 100644 +--- a/arch/arm/include/asm/system.h ++++ b/arch/arm/include/asm/system.h +@@ -81,6 +81,8 @@ int __asm_flush_l3_cache(void); + + void armv8_switch_to_el2(void); + void armv8_switch_to_el1(void); ++void armv8_switch_to_el2_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr); ++void armv8_switch_to_el1_aarch32(u64 entry_point, u64 mach_nr, u64 fdt_addr); + void gic_init(void); + void gic_send_sgi(unsigned long sgino); + void wait_for_wakeup(void); +diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c +index a477cae..36f2cb0 100644 +--- a/arch/arm/lib/bootm.c ++++ b/arch/arm/lib/bootm.c +@@ -276,8 +276,24 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) + announce_and_cleanup(fake); + + if (!fake) { +- do_nonsec_virt_switch(); +- kernel_entry(images->ft_addr, NULL, NULL, NULL); ++ if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) && ++ (images->os.arch == IH_ARCH_ARM)) { ++ smp_kick_all_cpus(); ++ dcache_disable(); ++#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 ++ armv8_switch_to_el2(); ++ armv8_switch_to_el1_aarch32((u64)images->ep, ++ (u64)gd->bd->bi_arch_number, ++ (u64)images->ft_addr); ++#else ++ armv8_switch_to_el2_aarch32((u64)images->ep, ++ (u64)gd->bd->bi_arch_number, ++ (u64)images->ft_addr); ++#endif ++ } else { ++ do_nonsec_virt_switch(); ++ kernel_entry(images->ft_addr, NULL, NULL, NULL); ++ } + } + #else + unsigned long machid = gd->bd->bi_arch_number; +diff --git a/common/image-fit.c b/common/image-fit.c +index c531ee7..0d54f71 100644 +--- a/common/image-fit.c ++++ b/common/image-fit.c +@@ -1144,7 +1144,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch) + if (fit_image_get_arch(fit, noffset, &image_arch)) + return 0; + return (arch == image_arch) || +- (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64); ++ (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64) || ++ (arch == IH_ARCH_ARM64 && image_arch == IH_ARCH_ARM); + } + + /** +@@ -1567,6 +1568,9 @@ int fit_image_load(bootm_headers_t *images, ulong addr, + int type_ok, os_ok; + ulong load, data, len; + uint8_t os; ++#ifndef USE_HOSTCC ++ uint8_t os_arch; ++#endif + const char *prop_name; + int ret; + +@@ -1650,6 +1654,12 @@ int fit_image_load(bootm_headers_t *images, ulong addr, + return -ENOEXEC; + } + #endif ++ ++#ifndef USE_HOSTCC ++ fit_image_get_arch(fit, noffset, &os_arch); ++ images->os.arch = os_arch; ++#endif ++ + if (image_type == IH_TYPE_FLATDT && + !fit_image_check_comp(fit, noffset, IH_COMP_NONE)) { + puts("FDT image is compressed"); +-- +1.7.9.5 + diff --git a/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch b/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch new file mode 100644 index 0000000..b24bc18 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0002-armv8-SMP-support-for-loading-32-bit-OS.patch @@ -0,0 +1,141 @@ +From 014f9196e18f4157232d0521f3a7502e7dbbb974 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Fri, 13 May 2016 13:28:07 +0800 +Subject: [PATCH 02/93] armv8: SMP support for loading 32-bit OS + +Spin-table method is used for secondary cores to load 32-bit OS. The +architecture information will be got through checking FIT image and +saved in the os_arch element of spin-table, then the secondary cores +will check os_arch and jump to 32-bit OS or 64-bit OS automatically. + +Signed-off-by: Alison Wang <alison.wang@nxp.com> +Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> +--- + arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 21 +++++++++++++++++++++ + arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 ++++++++++ + arch/arm/include/asm/arch-fsl-layerscape/mp.h | 6 ++++++ + arch/arm/lib/bootm.c | 5 +++++ + 4 files changed, 42 insertions(+) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +index 9c69ed1..93f4a65 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S ++++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +@@ -13,6 +13,7 @@ + #ifdef CONFIG_MP + #include <asm/arch/mp.h> + #endif ++#include <asm/u-boot.h> + + ENTRY(lowlevel_init) + mov x29, lr /* Save LR */ +@@ -320,6 +321,11 @@ ENTRY(secondary_boot_func) + gic_wait_for_interrupt_m x0, w1 + #endif + ++ ldr x5, [x11, #24] ++ ldr x6, =IH_ARCH_DEFAULT ++ cmp x6, x5 ++ b.ne slave_cpu ++ + bl secondary_switch_to_el2 + #ifdef CONFIG_ARMV8_SWITCH_TO_EL1 + bl secondary_switch_to_el1 +@@ -337,6 +343,21 @@ slave_cpu: + tbz x1, #25, cpu_is_le + rev x0, x0 /* BE to LE conversion */ + cpu_is_le: ++ ++ ldr x5, [x11, #24] ++ ldr x6, =IH_ARCH_DEFAULT ++ cmp x6, x5 ++ b.eq 1f ++ ++#ifdef CONFIG_ARMV8_SWITCH_TO_EL1 ++ bl secondary_switch_to_el2 ++ ldr x0, [x11] ++ bl armv8_switch_to_el1_aarch32 ++#else ++ bl armv8_switch_to_el2_aarch32 ++#endif ++ ++1: + br x0 /* branch to the given address */ + ENDPROC(secondary_boot_func) + +diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c +index df7ffb8..dd91550 100644 +--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c ++++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c +@@ -22,6 +22,16 @@ phys_addr_t determine_mp_bootpg(void) + return (phys_addr_t)&secondary_boot_code; + } + ++void update_os_arch_secondary_cores(uint8_t os_arch) ++{ ++ u64 *table = get_spin_tbl_addr(); ++ int i; ++ ++ for (i = 1; i < CONFIG_MAX_CPUS; i++) ++ table[i * WORDS_PER_SPIN_TABLE_ENTRY + ++ SPIN_TABLE_ELEM_OS_ARCH_IDX] = os_arch; ++} ++ + int fsl_layerscape_wake_seconday_cores(void) + { + struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); +diff --git a/arch/arm/include/asm/arch-fsl-layerscape/mp.h b/arch/arm/include/asm/arch-fsl-layerscape/mp.h +index e46e076..55f0e0c 100644 +--- a/arch/arm/include/asm/arch-fsl-layerscape/mp.h ++++ b/arch/arm/include/asm/arch-fsl-layerscape/mp.h +@@ -13,6 +13,7 @@ + * uint64_t entry_addr; + * uint64_t status; + * uint64_t lpid; ++* uint64_t os_arch; + * }; + * we pad this struct to 64 bytes so each entry is in its own cacheline + * the actual spin table is an array of these structures +@@ -20,6 +21,7 @@ + #define SPIN_TABLE_ELEM_ENTRY_ADDR_IDX 0 + #define SPIN_TABLE_ELEM_STATUS_IDX 1 + #define SPIN_TABLE_ELEM_LPID_IDX 2 ++#define SPIN_TABLE_ELEM_OS_ARCH_IDX 3 + #define WORDS_PER_SPIN_TABLE_ENTRY 8 /* pad to 64 bytes */ + #define SPIN_TABLE_ELEM_SIZE 64 + +@@ -35,4 +37,8 @@ phys_addr_t determine_mp_bootpg(void); + void secondary_boot_func(void); + int is_core_online(u64 cpu_id); + #endif ++ ++#define IH_ARCH_ARM 2 /* ARM */ ++#define IH_ARCH_ARM64 22 /* ARM64 */ ++ + #endif /* _FSL_LAYERSCAPE_MP_H */ +diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c +index 36f2cb0..aae8c5b 100644 +--- a/arch/arm/lib/bootm.c ++++ b/arch/arm/lib/bootm.c +@@ -258,6 +258,10 @@ bool armv7_boot_nonsec(void) + } + #endif + ++__weak void update_os_arch_secondary_cores(uint8_t os_arch) ++{ ++} ++ + /* Subcommand: GO */ + static void boot_jump_linux(bootm_headers_t *images, int flag) + { +@@ -276,6 +280,7 @@ static void boot_jump_linux(bootm_headers_t *images, int flag) + announce_and_cleanup(fake); + + if (!fake) { ++ update_os_arch_secondary_cores(images->os.arch); + if ((IH_ARCH_DEFAULT == IH_ARCH_ARM64) && + (images->os.arch == IH_ARCH_ARM)) { + smp_kick_all_cpus(); +-- +1.7.9.5 + diff --git a/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch b/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch new file mode 100644 index 0000000..b309ffe --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0003-armv8-aarch32-Disable-CONFIG_FSL_LS_PPA-for-loading-.patch @@ -0,0 +1,30 @@ +From f9e93719a99120e93628bf39bd997164a01afda2 Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Fri, 13 May 2016 15:23:27 +0800 +Subject: [PATCH 03/93] armv8: aarch32: Disable CONFIG_FSL_LS_PPA for loading + 32-bit OS + +The current U-Boot doesn't support loading 32-bit OS with PPA, so +disable CONFIG_FSL_LS_PPA so far. + +Signed-off-by: Alison Wang <alison.wang@nxp.com> +--- + include/configs/ls1043ardb.h | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h +index c1abc73..af8b441 100644 +--- a/include/configs/ls1043ardb.h ++++ b/include/configs/ls1043ardb.h +@@ -9,7 +9,7 @@ + + #include "ls1043a_common.h" + +-#define CONFIG_FSL_LS_PPA ++#undef CONFIG_FSL_LS_PPA + #if defined(CONFIG_FSL_LS_PPA) + #define CONFIG_ARMV8_PSCI + #define CONFIG_SYS_LS_PPA_DRAM_BLOCK_MIN_SIZE (1UL * 1024 * 1024) +-- +1.7.9.5 + diff --git a/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch b/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch new file mode 100644 index 0000000..8f5dc28 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0004-armv8-Support-loading-32-bit-OS-which-is-not-in-the-.patch @@ -0,0 +1,31 @@ +From cb5a037831053d22ce260dbec6b378f532bd2c6c Mon Sep 17 00:00:00 2001 +From: Alison Wang <b18965@freescale.com> +Date: Tue, 21 Jun 2016 17:14:35 +0800 +Subject: [PATCH 04/93] armv8: Support loading 32-bit OS which is not in the + form of FIT + +As only FIT image is supported now, this patch is to support loading +32-bit uImage, dtb and rootfs separately. + +Signed-off-by: Alison Wang <alison.wang@nxp.com> +--- + include/image.h | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/include/image.h b/include/image.h +index 299d6d2..0ea5f8e 100644 +--- a/include/image.h ++++ b/include/image.h +@@ -694,7 +694,8 @@ static inline int image_check_type(const image_header_t *hdr, uint8_t type) + } + static inline int image_check_arch(const image_header_t *hdr, uint8_t arch) + { +- return (image_get_arch(hdr) == arch); ++ return (image_get_arch(hdr) == arch) || ++ (image_get_arch(hdr) == IH_ARCH_ARM && arch == IH_ARCH_ARM64); + } + static inline int image_check_os(const image_header_t *hdr, uint8_t os) + { +-- +1.7.9.5 + diff --git a/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch b/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch new file mode 100644 index 0000000..2754859 --- /dev/null +++ b/package/boot/uboot-layerscape/patches/0005-armv8-set-openwrt-lede-default-boot-env-for-ls1043ar.patch @@ -0,0 +1,68 @@ +From 3c22f3fcbdb9f919ebdfa87a2ec237ac2abb7e03 Mon Sep 17 00:00:00 2001 +From: Yutang Jiang <yutang.jiang@nxp.com> +Date: Thu, 27 Oct 2016 23:45:45 +0800 +Subject: [PATCH 05/93] armv8: set openwrt/lede default boot env for + ls1043ardb + +Signed-off-by: Yutang Jiang <yutang.jiang@nxp.com> +--- + include/configs/ls1043a_common.h | 28 +++++++++++++++++++++++++--- + 1 file changed, 25 insertions(+), 3 deletions(-) + +diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h +index 68678f3..1db05bb 100644 +--- a/include/configs/ls1043a_common.h ++++ b/include/configs/ls1043a_common.h +@@ -273,6 +273,16 @@ + "5m(kernel),1m(dtb),9m(file_system)" + #endif + ++#define WRTBOOT_DEFAULT "setenv bootargs root=/dev/mtdblock6 " \ ++ "rootfstype=squashfs,jffs2 noinitrd earlycon=uart8250,mmio,0x21c0500 " \ ++ "console=ttyS0,115200 mtdparts=60000000.nor:1M(rcw),1M(u-boot)," \ ++ "1M(u-boot-env),1M(fman),1M(dtb),5M(kernel),54M(rootfs),64M(otherbank)" \ ++ " && cp.b 60400000 $fdtaddr 100000 && cp.b 60500000 $loadaddr 500000" \ ++ " && bootm $loadaddr - $fdtaddr" ++#define WRTUPDATE_DEFAULT "tftp a0000000 <tftp_folder>/" \ ++ "lede-layerscape-64b-ls1043ardb-squashfs-firmware.bin && protect off all" \ ++ " && erase 60000000 +4000000 && cp.b a0000000 60000000 $filesize && reset" ++ + /* Initial environment variables */ + #define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:bank_intlv=auto\0" \ +@@ -286,6 +296,19 @@ + "kernel_load=0xa0000000\0" \ + "kernel_size=0x2800000\0" \ + "console=ttyAMA0,38400n8\0" \ ++ "ethaddr=00:e0:0c:00:77:00\0" \ ++ "eth1addr=00:e0:0c:00:77:01\0" \ ++ "eth2addr=00:e0:0c:00:77:02\0" \ ++ "eth3addr=00:e0:0c:00:77:03\0" \ ++ "eth4addr=00:e0:0c:00:77:04\0" \ ++ "eth5addr=00:e0:0c:00:77:05\0" \ ++ "eth6addr=00:e0:0c:00:77:06\0" \ ++ "ethact=FM1@DTSEC2\0" \ ++ "loadaddr=82000000\0" \ ++ "ramdiskaddr=88000000\0" \ ++ "fdtaddr=8f000000\0" \ ++ "wrtboot=" WRTBOOT_DEFAULT "\0" \ ++ "wrtupdate=" WRTUPDATE_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" + + #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \ +@@ -296,10 +319,9 @@ + #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \ + "e0000 f00000 && bootm $kernel_load" + #else +-#define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \ +- "$kernel_size && bootm $kernel_load" ++#define CONFIG_BOOTCOMMAND "run wrtboot" + #endif +-#define CONFIG_BOOTDELAY 10 ++#define CONFIG_BOOTDELAY 3 + + /* Monitor Command Prompt */ + #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +-- +1.7.9.5 + |