diff options
Diffstat (limited to 'package/uboot-ifxmips/files')
41 files changed, 0 insertions, 8140 deletions
diff --git a/package/uboot-ifxmips/files/board/ifx/danube/Makefile b/package/uboot-ifxmips/files/board/ifx/danube/Makefile deleted file mode 100644 index 5655117..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/Makefile +++ /dev/null @@ -1,44 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).a - -COBJS = $(BOARD).o flash.o -SOBJS = lowlevel_init.o pmuenable.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) -SOBJS := $(addprefix $(obj),$(SOBJS)) - -$(LIB): $(obj).depend $(OBJS) $(SOBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) - -######################################################################### - -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-ifxmips/files/board/ifx/danube/README b/package/uboot-ifxmips/files/board/ifx/danube/README deleted file mode 100644 index d1c5c1e..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/README +++ /dev/null @@ -1,55 +0,0 @@ -/* -** Copyright (C) 2005 Wu Qi Ming <Qi-Ming.Wu@infineon.com> -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** This program is distributed in the hope that it will be useful, -** but WITHOUT ANY WARRANTY; without even the implied warranty of -** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -** GNU General Public License for more details. -** -** You should have received a copy of the GNU General Public License -** along with this program; if not, write to the Free Software -** Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. -*/ - -To build a u-boot for danube board, user need to do the following things: -To configure u-boot for a proper board, user need to modify two files accordingly. - -To configure u-boot for evaluation board, in danube-uboot/include/configs/danube.h, set -#define USE_EVALUATION_BOARD -#undef USE_REFERENCE_BOARD -and vice-versa. - -To let u-boot boot from ebu(flash,e.g), in danube-uboot/include/configus/danube.h, set -#define DANUBE_BOOT_FROM_EBU -Otherwise u-boot will be compiled for booting from RAM. - -To use DDR RAM running at 111M, in danube-uboot/include/configus/danube. -h, set -#define DANUBE_DDR_RAM_111M -#undef DANUBE_DDR_RAM_166M -and vice-versa. - -To define RAM size of RAM, in danube-uboot/include/configus/danube. -h, set -#define RAM_SIZE 0x2000000 /*32M ram*/ -This is an example for a 32M RAM. - - -Besides above settings, user need to change danube-uboot/board/danube/config.mk to set the loading address of u-boot. -If U-Boot is to boot from EBU(flash), user needs to set -TEXT_BASE=0xB0000000 -If u-boot is to boot from RAM, user needs to set -TEXT_BASE=0xa0400000 - -Use the script gct to build a uart downloadable u-boot image: -./gct danube_ref_ddr166.conf u-boot.srec u-boot.asc - - - - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/config.mk b/package/uboot-ifxmips/files/board/ifx/danube/config.mk deleted file mode 100644 index 88680e1..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -# -# Danube board with MIPS 24Kec CPU core -#boot from ebu -#TEXT_BASE = 0xB0000000 -BOOTSTRAP_TEXT_BASE = 0xB0000000 - -#boot from ram -#TEXT_BASE = 0xa0400000 -#TEXT_BASE = 0x807c0000 - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/danube.c b/package/uboot-ifxmips/files/board/ifx/danube/danube.c deleted file mode 100644 index b6174ba..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/danube.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <command.h> -#include <asm/addrspace.h> -#include <asm/danube.h> - -#ifdef DANUBE_USE_DDR_RAM -long int initdram(int board_type) -{ - return (1024*1024*DANUBE_DDR_RAM_SIZE); -} -#else -extern uint danube_get_cpuclk(void); - -static ulong max_sdram_size(void) /* per Chip Select */ -{ - /* The only supported SDRAM data width is 16bit. - */ -#define CFG_DW 4 - - /* The only supported number of SDRAM banks is 4. - */ -#define CFG_NB 4 - - ulong cfgpb0 = *DANUBE_SDRAM_MC_CFGPB0; - int cols = cfgpb0 & 0xF; - int rows = (cfgpb0 & 0xF0) >> 4; - ulong size = (1 << (rows + cols)) * CFG_DW * CFG_NB; - - return size; -} - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. - */ - -static long int dram_size(long int *base, long int maxsize) -{ - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - for (cnt = (maxsize / sizeof (long)) >> 1; cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} - -long int initdram(int board_type) -{ - int rows, cols, best_val = *DANUBE_SDRAM_MC_CFGPB0; - ulong size, max_size = 0; - ulong our_address; - - /* load t9 into our_address */ - asm volatile ("move %0, $25" : "=r" (our_address) :); - - /* Can't probe for RAM size unless we are running from Flash. - * find out whether running from DRAM or Flash. - */ - if (PHYSADDR(our_address) < PHYSADDR(PHYS_FLASH_1)) - { - return max_sdram_size(); - } - - for (cols = 0x8; cols <= 0xC; cols++) - { - for (rows = 0xB; rows <= 0xD; rows++) - { - *DANUBE_SDRAM_MC_CFGPB0 = (0x14 << 8) | - (rows << 4) | cols; - size = dram_size((ulong *)CFG_SDRAM_BASE, - max_sdram_size()); - - if (size > max_size) - { - best_val = *DANUBE_SDRAM_MC_CFGPB0; - max_size = size; - } - } - } - - *DANUBE_SDRAM_MC_CFGPB0 = best_val; - return max_size; -} -#endif - -int checkboard (void) -{ - /* No such register in Amazon */ -#if 0 - unsigned long chipid = *AMAZON_MCD_CHIPID; - int part_num; - - puts ("Board: AMAZON "); - part_num = AMAZON_MCD_CHIPID_PART_NUMBER_GET(chipid); - switch (part_num) { - case AMAZON_CHIPID_STANDARD: - printf ("Standard Version, "); - break; - case AMAZON_CHIPID_YANGTSE: - printf ("Yangtse Version, "); - break; - default: - printf ("Unknown Part Number 0x%x ", part_num); - break; - } - - printf ("Chip V1.%ld, ", AMAZON_MCD_CHIPID_VERSION_GET(chipid)); - - - printf("CPU Speed %d MHz\n", danube_get_cpuclk()/1000000); - -#endif - return 0; -} - - -/* - * Disk On Chip (NAND) Millenium initialization. - * The NAND lives in the CS2* space - */ -#if (CONFIG_COMMANDS & CFG_CMD_NAND) -extern void -nand_probe(ulong physadr); - -#define AT91_SMARTMEDIA_BASE 0x40000000 /* physical address to access memory on NCS3 */ -void -nand_init(void) -{ - int devtype; - /* Configure EBU */ -//TODO: should we keep this? - //Set GPIO23 to be Flash CS1; - *DANUBE_GPIO_P1_ALTSEL0 = *DANUBE_GPIO_P1_ALTSEL0 | (1<<7); - *DANUBE_GPIO_P1_ALTSEL1 = *DANUBE_GPIO_P1_ALTSEL1 & ~(1<<7); - *DANUBE_GPIO_P1_DIR = *DANUBE_GPIO_P1_DIR | (1<<7) ; - *DANUBE_GPIO_P1_OD = *DANUBE_GPIO_P1_OD | (1<<7) ; - - *EBU_ADDR_SEL_1 = (NAND_BASE_ADDRESS&0x1fffff00)|0x31; - /* byte swap;minimum delay*/ - *EBU_CON_1 = 0x40C155; - *EBU_NAND_CON = 0x000005F3; - - /* Set bus signals to inactive */ - NAND_READY_CLEAR; - - NAND_CE_CLEAR; - nand_probe(NAND_BASE_ADDRESS); - - - - //nand_probe(AT91_SMARTMEDIA_BASE); -} -#endif - - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h deleted file mode 100644 index 3a4b135..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 -#define MC_DC21_VALUE 0x1d00 -#define MC_DC22_VALUE 0x1d1d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* was 0x7f */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h deleted file mode 100644 index b655ca2..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h deleted file mode 100644 index b655ca2..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h deleted file mode 100644 index 54bb6c9..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_PROMOSDDR400.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xa02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x0 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h deleted file mode 100644 index 7975c3e..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_Samsung_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Samsung DDR K4H561638H Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1400 -#define MC_DC22_VALUE 0x1414 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x4e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d93 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h deleted file mode 100644 index b655ca2..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h deleted file mode 100644 index b655ca2..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_e166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Eval Board DDR 167 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA03 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1800 -#define MC_DC22_VALUE 0x1818 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h deleted file mode 100644 index 445b7da..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_psc_166.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for PSC DDR A2S56D40CTP for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 27th Nov 2006 */ - -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0x120 /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x301 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1700 -#define MC_DC22_VALUE 0x1717 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x52 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x4e20 -#define MC_DC30_VALUE 0x8235 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h deleted file mode 100644 index fd15597..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r111.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0x1200 -#define MC_DC22_VALUE 0x1212 -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x5e /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h b/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h deleted file mode 100644 index 742d34f..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/ddr_settings_r166.h +++ /dev/null @@ -1,50 +0,0 @@ -/* Settings for Denali DDR SDRAM controller */ -/* Optimise for Danube Ref Board DDR 166 Mhz - by Ng Aik Ann 29th April */ -#define MC_DC0_VALUE 0x1B1B -#define MC_DC1_VALUE 0x0 -#define MC_DC2_VALUE 0x0 -#define MC_DC3_VALUE 0x0 -#define MC_DC4_VALUE 0x0 -#define MC_DC5_VALUE 0x200 -#define MC_DC6_VALUE 0x605 -#define MC_DC7_VALUE 0x303 -#define MC_DC8_VALUE 0x102 -#define MC_DC9_VALUE 0x70a -#define MC_DC10_VALUE 0x203 -#define MC_DC11_VALUE 0xc02 -#define MC_DC12_VALUE 0x1C8 -#define MC_DC13_VALUE 0x1 -#define MC_DC14_VALUE 0x0 -#define MC_DC15_VALUE 0xf3c /* WDQS tuning for clk_wr*/ -#define MC_DC16_VALUE 0xC800 -#define MC_DC17_VALUE 0xd -#define MC_DC18_VALUE 0x300 -#define MC_DC19_VALUE 0x200 -#define MC_DC20_VALUE 0xA04 /* A04 for reference board, A03 for Eval board */ -#define MC_DC21_VALUE 0xd00 -#define MC_DC22_VALUE 0xd0d -#define MC_DC23_VALUE 0x0 -#define MC_DC24_VALUE 0x62 /* WDQS Tuning for DQS */ -#define MC_DC25_VALUE 0x0 -#define MC_DC26_VALUE 0x0 -#define MC_DC27_VALUE 0x0 -#define MC_DC28_VALUE 0x510 -#define MC_DC29_VALUE 0x2d89 -#define MC_DC30_VALUE 0x8300 -#define MC_DC31_VALUE 0x0 -#define MC_DC32_VALUE 0x0 -#define MC_DC33_VALUE 0x0 -#define MC_DC34_VALUE 0x0 -#define MC_DC35_VALUE 0x0 -#define MC_DC36_VALUE 0x0 -#define MC_DC37_VALUE 0x0 -#define MC_DC38_VALUE 0x0 -#define MC_DC39_VALUE 0x0 -#define MC_DC40_VALUE 0x0 -#define MC_DC41_VALUE 0x0 -#define MC_DC42_VALUE 0x0 -#define MC_DC43_VALUE 0x0 -#define MC_DC44_VALUE 0x0 -#define MC_DC45_VALUE 0x500 -//#define MC_DC45_VALUE 0x400 -#define MC_DC46_VALUE 0x0 diff --git a/package/uboot-ifxmips/files/board/ifx/danube/flash.c b/package/uboot-ifxmips/files/board/ifx/danube/flash.c deleted file mode 100644 index d95888f..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/flash.c +++ /dev/null @@ -1,917 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -//joelin 10/07/2004 for MXIC MX29LV320ABTC-90 -#include <common.h> -#include <asm/danube.h> - -/* -#ifdef CONFIG_AMAZON - #define FLASH_DELAY {int i; \ - for(i=0;i<800;i++) \ - *((volatile u32 *)CFG_SDRAM_BASE_UNCACHE); \ - } -#else - #define FLASH_DELAY -#endif -*/ - -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it - * has nothing to do with the flash chip being 8-bit or 16-bit. - */ -#ifdef CONFIG_FLASH_16BIT -typedef unsigned short FLASH_PORT_WIDTH; -typedef volatile unsigned short FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFF -#else -typedef unsigned long FLASH_PORT_WIDTH; -typedef volatile unsigned long FLASH_PORT_WIDTHV; -#define FLASH_ID_MASK 0xFFFFFFFF -#endif - -#define FPW FLASH_PORT_WIDTH -#define FPWV FLASH_PORT_WIDTHV - -#define ORMASK(size) ((-size) & OR_AM_MSK) // 0xffff8000 - -#if 0 -#define FLASH_CYCLE1 0x0555 -#define FLASH_CYCLE2 0x02aa -#else -#define FLASH_CYCLE1 0x0554 //joelin for MX29LV320AT/B 0x0555 -#define FLASH_CYCLE2 0x02ab //joelin for MX29LV320AT/B 0x02aa -#endif - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size(FPWV *addr, flash_info_t *info); -static void flash_reset(flash_info_t *info); -static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data); -static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data); -static void flash_get_offsets(ulong base, flash_info_t *info); -static flash_info_t *flash_get_info(ulong base); - -/*----------------------------------------------------------------------- - * flash_init() - * - * sets up flash_info and returns size of FLASH (bytes) - */ -unsigned long flash_init (void) -{ - unsigned long size = 0; - int i; - - /* Init: no FLASHes known */ - for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) { // 1 bank - ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2; // 0xb0000000, 0xb4000000 - - volatile ulong * buscon = (ulong *) - ((i == 0) ? DANUBE_EBU_BUSCON0 : DANUBE_EBU_BUSCON1); - - /* Disable write protection */ -// *buscon &= ~AMAZON_EBU_BUSCON0_WRDIS; - /* Enable write protection */ - *buscon |= DANUBE_EBU_BUSCON0_WRDIS; - -#if 1 - memset(&flash_info[i], 0, sizeof(flash_info_t)); -#endif - - flash_info[i].size = - flash_get_size((FPW *)flashbase, &flash_info[i]); - - if (flash_info[i].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx\n", - i, flash_info[i].size); - } - - size += flash_info[i].size; - } - -#if CFG_MONITOR_BASE >= CFG_FLASH_BASE // TEXT_BASE >= 0xB3000000 - /* monitor protection ON by default */ /* only use software protection, info->protect[i]=0/1 */ -/* flash_protect(FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - flash_get_info(CFG_MONITOR_BASE)); -*/ - flash_protect(FLAG_PROTECT_CLEAR, // clear protect - CFG_MONITOR_BASE, - CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, - flash_get_info(CFG_MONITOR_BASE)); - -#endif - -#ifdef CFG_ENV_IS_IN_FLASH /* 1 */ - /* ENV protection ON by default */ -/* flash_protect(FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); -*/ - flash_protect(FLAG_PROTECT_CLEAR, - CFG_ENV_ADDR, - CFG_ENV_ADDR+CFG_ENV_SIZE-1, - flash_get_info(CFG_ENV_ADDR)); - -#endif - - - return size; -} - -/*----------------------------------------------------------------------- - */ -static void flash_reset(flash_info_t *info) -{ - FPWV *base = (FPWV *)(info->start[0]); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - /* Put FLASH back in read mode */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL){ - *base = (FPW)0x00FF00FF; /* Intel Read Mode */ - asm("SYNC"); - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD){ - *base = (FPW)0x00F000F0; /* AMD Read Mode */ - asm("SYNC"); //joelin - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX){ - *base = (FPW)0x00F000F0; /* MXIC Read Mode */ - asm("SYNC"); //joelin - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL - && (info->flash_id & FLASH_BTYPE)) { - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD - && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) { - - int sect_size; /* number of bytes/sector */ - - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set up sector start address table (uniform sector type) */ - for( i = 0; i < info->sector_count; i++ ) - info->start[i] = base + (i * sect_size); - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F128J3A)){ - int sect_size; - sect_size = 0x20000; - for(i=0;i < info->sector_count; i++) - info->start[i]= base + (i*sect_size); - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_28F320J3A)){ - int sect_size; - sect_size = 0x20000; - for(i=0;i < info->sector_count; i++) - info->start[i]= base + (i*sect_size); - } -//joelin add for MX29LV320AB-- SA0~SA7:sector size=8K bytes ,SA9~SA70 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV320AB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV320B)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } -//joelin add for MX29LV160BB-- SA0=16K,SA1,SA2=8K,SA3=32K bytes ,SA4~SA34 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV160BB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); -/* set sector offsets for bottom boot block type */ -//MX29LV160BB - info->start[0] = base ; //SA0=16K bytes - info->start[1] = info->start[0] + (1 * 0x00004000 * (sizeof(FPW)/2)); //SA1=8K bytes - info->start[2] = info->start[1] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA2=8K bytes - info->start[3] = info->start[2] + (1 * 0x00002000 * (sizeof(FPW)/2)); //SA3=32K bytes - - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i - 3) * sect_size); - } - } -//liupeng add for MX29LV640BB-- SA0~SA7:sector size=8k bytes ,SA8~SA134 :sector size=64k bytes - else if(((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_MX) - && ((info->flash_id & FLASH_TYPEMASK)==FLASH_29LV640BB)){ - int bootsect_size; /* number of bytes/boot sector */ - int sect_size; /* number of bytes/regular sector */ - - bootsect_size = 0x00002000 * (sizeof(FPW)/2); - sect_size = 0x00010000 * (sizeof(FPW)/2); - - /* set sector offsets for bottom boot block type */ - for (i = 0; i < 8; ++i) { - info->start[i] = base + (i * bootsect_size); - } - for (i = 8; i < info->sector_count; i++) { - info->start[i] = base + ((i - 7) * sect_size); - } - } - else{ - printf("flash get offsets fail\n"); - } -} - -/*----------------------------------------------------------------------- - */ - -static flash_info_t *flash_get_info(ulong base) -{ - int i; - flash_info_t * info; - - for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) { - info = & flash_info[i]; - if (info->start[0] <= base && base < info->start[0] + info->size) - break; - } - - return i == CFG_MAX_FLASH_BANKS ? 0 : info; -} - -/*----------------------------------------------------------------------- - */ - -void flash_print_info (flash_info_t *info) -{ - int i; - uchar *boottype; - uchar *bootletter; - uchar *fmt; - uchar botbootletter[] = "B"; - uchar topbootletter[] = "T"; - uchar botboottype[] = "bottom boot sector"; - uchar topboottype[] = "top boot sector"; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - case FLASH_MAN_SST: printf ("SST "); break; - case FLASH_MAN_STM: printf ("STM "); break; - case FLASH_MAN_INTEL: printf ("INTEL "); break; - case FLASH_MAN_MX: printf ("MXIC "); break; - default: printf ("Unknown Vendor "); break; - } - - /* check for top or bottom boot, if it applies */ - if (info->flash_id & FLASH_BTYPE) { - boottype = botboottype; - bootletter = botbootletter; - } - else { - boottype = topboottype; - bootletter = topbootletter; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM640U: - fmt = "29LV641D (64 Mbit, uniform sectors)\n"; - break; - case FLASH_28F800C3B: - case FLASH_28F800C3T: - fmt = "28F800C3%s (8 Mbit, %s)\n"; - break; - case FLASH_INTEL800B: - case FLASH_INTEL800T: - fmt = "28F800B3%s (8 Mbit, %s)\n"; - break; - case FLASH_28F160C3B: - case FLASH_28F160C3T: - fmt = "28F160C3%s (16 Mbit, %s)\n"; - break; - case FLASH_INTEL160B: - case FLASH_INTEL160T: - fmt = "28F160B3%s (16 Mbit, %s)\n"; - break; - case FLASH_28F320C3B: - case FLASH_28F320C3T: - fmt = "28F320C3%s (32 Mbit, %s)\n"; - break; - case FLASH_INTEL320B: - case FLASH_INTEL320T: - fmt = "28F320B3%s (32 Mbit, %s)\n"; - break; - case FLASH_28F640C3B: - case FLASH_28F640C3T: - fmt = "28F640C3%s (64 Mbit, %s)\n"; - break; - case FLASH_INTEL640B: - case FLASH_INTEL640T: - fmt = "28F640B3%s (64 Mbit, %s)\n"; - break; - case FLASH_28F128J3A: - fmt = "28F128J3A (128 Mbit, 128 uniform sectors)\n"; - break; - case FLASH_28F320J3A: - fmt = "28F320J3A (32 Mbit, 32 uniform sectors)\n"; - break; - case FLASH_29LV640BB: //liupeng for MXIC FLASH_29LV640BB - fmt = "29LV640BB (64 Mbit, boot sector SA0~SA126 size 64k bytes,other sectors SA127~SA135 size 8k bytes)\n"; - break; - case FLASH_29LV320B: //joelin for MXIC FLASH_29LV320AB - case FLASH_29LV320AB: //joelin for MXIC FLASH_29LV320AB - fmt = "29LV320AB (32 Mbit, boot sector SA0~SA7 size 8K bytes,other sectors SA8~SA70 size 64K bytes)\n"; - break; - case FLASH_29LV160BB: //joelin for MXIC FLASH_29LV160BB - fmt = "29LV160BB (16 Mbit, boot sector SA0 size 16K bytes,SA1,SA2 size 8K bytes,SA3 size 32k bytes,other sectors SA4~SA34 size 64K bytes)\n"; - break; - default: - fmt = "Unknown Chip Type\n"; - break; - } - - printf (fmt, bootletter, boottype); - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, - info->sector_count); - - printf (" Sector Start Addresses:"); - - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) { - printf ("\n "); - } - - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - - printf ("\n"); -} - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -ulong flash_get_size (FPWV *addr, flash_info_t *info) -{ - (*DANUBE_EBU_BUSCON0)=0x1d7ff; //value from Aikann, should be used on the real chip - (*EBU_ADDR_SEL_0) = 0x10000031; //starting address from 0xb0000000 - (*EBU_NAND_CON)=0; - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - /* Write auto select command: read Manufacturer ID */ - - /* Write auto select command sequence and test FLASH answer */ - addr[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* for AMD, Intel ignores this */ - asm("SYNC"); - addr[FLASH_CYCLE2] = (FPW)0x00550055; /* for AMD, Intel ignores this */ - asm("SYNC"); - addr[FLASH_CYCLE1] = (FPW)0x00900090; /* selects Intel or AMD */ - asm("SYNC"); - - /* The manufacturer codes are only 1 byte, so just use 1 byte. - * This works for any bus width and any FLASH device width. - */ - - printf("\n type is %08lx", addr[1] & 0xff); //joelin 10/06/2004 flash type - printf("\n type is %08lx", addr[0] & 0xff); //joelin 10/06/2004 flash type -// asm("SYNC"); - switch (addr[1] & 0xff) { - case (uchar)AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - - case (uchar)INTEL_MANUFACT: // 0x0089 - info->flash_id = FLASH_MAN_INTEL; //0x00300000 - break; - -//joelin for MXIC - case (uchar)MX_MANUFACT: // 0x00c2 - info->flash_id = FLASH_MAN_MX ;//0x00030000 - break; - - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - break; -/* default: - info->flash_id = FLASH_MAN_INTEL; //0x00300000 - break;*/ - } - - /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */ - if (info->flash_id != FLASH_UNKNOWN) switch (addr[0]) { - case (FPW)EON_ID_EN29LV320B: - info->flash_id += FLASH_29LV320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; - case (FPW)AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */ - info->flash_id += FLASH_AM640U; - info->sector_count = 128; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F800C3B: - info->flash_id += FLASH_28F800C3B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F800B3B: - info->flash_id += FLASH_INTEL800B; - info->sector_count = 23; - info->size = 0x00100000 * (sizeof(FPW)/2); - break; /* => 1 or 2 MB */ - - case (FPW)INTEL_ID_28F160C3B: - info->flash_id += FLASH_28F160C3B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F160B3B: - info->flash_id += FLASH_INTEL160B; - info->sector_count = 39; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 or 4 MB */ - - case (FPW)INTEL_ID_28F320C3B: - info->flash_id += FLASH_28F320C3B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F320B3B: - info->flash_id += FLASH_INTEL320B; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 or 8 MB */ - - case (FPW)INTEL_ID_28F640C3B: - info->flash_id += FLASH_28F640C3B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F640B3B: - info->flash_id += FLASH_INTEL640B; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 8 or 16 MB */ - - case (FPW)INTEL_ID_28F128J3A: - info->flash_id +=FLASH_28F128J3A; - info->sector_count = 128; - info->size = 0x01000000 * (sizeof(FPW)/2); - break; /* => 16 MB */ - case (FPW)INTEL_ID_28F320J3A: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; -//joelin for MXIC - case (FPW)MX_ID_29LV320AB: - info->flash_id += FLASH_29LV320AB; - info->sector_count = 71; - info->size = 0x00400000 * (sizeof(FPW)/2); - break; /* => 4 MB */ - /* => 4 MB */ -//joelin for MXIC - case (FPW)MX_ID_29LV160BB: - info->flash_id += FLASH_29LV160BB; - info->sector_count = 35; - info->size = 0x00200000 * (sizeof(FPW)/2); - break; /* => 2 MB */ - /* => 2 MB */ - /* liupeng*/ - case (FPW)MX_ID_29LV640BB: - info->flash_id += FLASH_29LV640BB; - info->sector_count = 135; - info->size = 0x00800000 * (sizeof(FPW)/2); - break; /* => 2 MB */ - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* => no or unknown flash */ -/* default: - info->flash_id += FLASH_28F320J3A; - info->sector_count = 32; - info->size = 0x00400000 * (sizeof(FPW)/2); - break;*/ - } - - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - flash_get_offsets((ulong)addr, info); - - /* Put FLASH back in read mode */ - flash_reset(info); - - return (info->size); -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - FPWV *addr; - int flag, prot, sect; - int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL; - ulong start, now, last; - int rcode = 0; - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_INTEL800B: - case FLASH_INTEL160B: - case FLASH_INTEL320B: - case FLASH_INTEL640B: - case FLASH_28F800C3B: - case FLASH_28F160C3B: - case FLASH_28F320C3B: - case FLASH_28F640C3B: - case FLASH_28F128J3A: - case FLASH_28F320J3A: - case FLASH_AM640U: - case FLASH_29LV640BB: //liupeng for MXIC MX29LV640BB - case FLASH_29LV320B: - case FLASH_29LV320AB: //joelin for MXIC MX29LV320AB - case FLASH_29LV160BB: //joelin for MXIC MX29LV160BB - break; - case FLASH_UNKNOWN: - default: - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - last = get_timer(0); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last && rcode == 0; sect++) { - - if (info->protect[sect] != 0) /* protected, skip it */ - continue; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - addr = (FPWV *)(info->start[sect]); - if (intel) { - *addr = (FPW)0x00500050; /* clear status register */ - *addr = (FPW)0x00200020; /* erase setup */ - *addr = (FPW)0x00D000D0; /* erase confirm */ - asm("SYNC"); - } - else { - /* must be AMD style if not Intel */ - FPWV *base; /* first address in bank */ - - base = (FPWV *)(info->start[0]); - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00800080; /* erase mode */ - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - *addr = (FPW)0x00300030; /* erase sector */ - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer(0); - - /* wait at least 50us for AMD, 80us for Intel. - * Let's wait 1 ms. - */ - udelay (1000); - - while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) { - if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { - printf ("Erase Timeout\n"); - - if (intel) { - /* suspend erase */ - *addr = (FPW)0x00B000B0; - } - - flash_reset(info); /* reset to read mode */ - rcode = 1; /* failed */ - break; - } - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) {/* every second */ - putc ('.'); - last = get_timer(0); - } - } - - -//joelin for MXIC - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_MX: //joelin for MXIC - break; - default: - if((*addr & (FPW)0x00200020) != (FPW)0x0) - printf("Erase Error\n"); - break; - } - - - - /* show that we're waiting */ - if ((get_timer(last)) > CFG_HZ) { /* every second */ - putc ('.'); - last = get_timer(0); - } - - //flash_reset(info); /* reset to read mode */ - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - flash_reset(info); /* Homebox Black with JS28F128J3D75 had trouble reading after erase */ - - printf (" done\n"); - return rcode; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */ - int bytes; /* number of bytes to program in current word */ - int left; /* number of bytes left to program */ - int i, res; - - for (left = cnt, res = 0; - left > 0 && res == 0; - addr += sizeof(data), left -= sizeof(data) - bytes) { - - bytes = addr & (sizeof(data) - 1); - addr &= ~(sizeof(data) - 1); - - /* combine source and destination data so can program - * an entire word of 16 or 32 bits - */ - for (i = 0; i < sizeof(data); i++) { - data <<= 8; - if (i < bytes || i - bytes >= left ) - data += *((uchar *)addr + i); - else - data += *src++; - } - - /* write one word to the flash */ - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: - case FLASH_MAN_MX: //joelin for MXIC - res = write_word_amd(info, (FPWV *)addr, data); - break; - case FLASH_MAN_INTEL: - res = write_word_intel(info, (FPWV *)addr, data); - break; - default: - /* unknown flash type, error! */ - printf ("missing or unknown FLASH type\n"); - res = 1; /* not really a timeout, but gives error */ - break; - } - } - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for AMD FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_amd (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - FPWV *base; /* first address in flash bank */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - base = (FPWV *)(info->start[0]); - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - - base[FLASH_CYCLE1] = (FPW)0x00AA00AA; /* unlock */ - base[FLASH_CYCLE2] = (FPW)0x00550055; /* unlock */ - base[FLASH_CYCLE1] = (FPW)0x00A000A0; /* selects program mode */ - - *dest = data; /* start programming the data */ - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - /* data polling for D7 */ - while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00F000F0; /* reset bank */ - res = 1; - } - } - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - return (res); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash for Intel FLASH - * A word is 16 or 32 bits, whichever the bus width of the flash bank - * (not an individual chip) is. - * - * returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word_intel (flash_info_t *info, FPWV *dest, FPW data) -{ - ulong start; - int flag; - int res = 0; /* result, assume success */ - - /* Check if Flash is (sufficiently) erased */ - if ((*dest & data) != data) { - return (2); - } - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - (*DANUBE_EBU_BUSCON0)&=(~0x80000000); // enable writing - (*DANUBE_EBU_BUSCON1)&=(~0x80000000); // enable writing - (*EBU_NAND_CON)=0; - *dest = (FPW)0x00500050; /* clear status register */ - *dest = (FPW)0x00FF00FF; /* make sure in read mode */ - *dest = (FPW)0x00400040; /* program setup */ - *dest = data; /* start programming the data */ - asm("SYNC"); - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - start = get_timer (0); - - while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) { - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { - *dest = (FPW)0x00B000B0; /* Suspend program */ - res = 1; - } - } - - if (res == 0 && (*dest & (FPW)0x00100010)) - res = 1; /* write failed, time out error is close enough */ - - *dest = (FPW)0x00500050; /* clear status register */ - flash_reset(info); - - (*DANUBE_EBU_BUSCON0)|=0x80000000; // disable writing - (*DANUBE_EBU_BUSCON1)|=0x80000000; // disable writing - - return (res); -} diff --git a/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S b/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S deleted file mode 100644 index f5f24a4..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/lowlevel_init.S +++ /dev/null @@ -1,582 +0,0 @@ - -/* - * Memory sub-system initialization code for INCA-IP2 development board. - * Andre Messerschmidt - * Copyright (c) 2005 Infineon Technologies AG - * - * Based on Inca-IP code - * Copyright (c) 2003 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -/* History: - peng liu May 25, 2006, for PLL setting after reset, 05252006 - */ -#include <config.h> -#include <version.h> -#include <asm/regdef.h> -#include <configs/danube.h> - - -#ifdef USE_REFERENCE_BOARD -#ifdef DANUBE_DDR_RAM_111M -#include "ddr_settings_r111.h" -#elif defined(PROMOSDDR400) -#include "ddr_settings_PROMOSDDR400.h" -#elif defined(DDR_SAMSUNG_166M) -#include "ddr_settings_Samsung_166.h" -#elif defined(DDR_PSC_166M) -#include "ddr_settings_psc_166.h" -#else -#include "ddr_settings_r166.h" -#endif -#endif - -#ifdef USE_EVALUATION_BOARD -#ifdef DANUBE_DDR_RAM_111M -#include "ddr_settings_e111.h" -#else -#include "ddr_settings_e166.h" -#endif -#endif - - - -/*TODO: liupeng check !!! */ -#define EBU_MODUL_BASE 0xB4102000 -#define EBU_CLC(value) 0x0000(value) -#define EBU_CON(value) 0x0010(value) -#define EBU_ADDSEL0(value) 0x0020(value) -#define EBU_ADDSEL1(value) 0x0024(value) -#define EBU_ADDSEL2(value) 0x0028(value) -#define EBU_ADDSEL3(value) 0x002C(value) -#define EBU_BUSCON0(value) 0x0060(value) -#define EBU_BUSCON1(value) 0x0064(value) -#define EBU_BUSCON2(value) 0x0068(value) -#define EBU_BUSCON3(value) 0x006C(value) - -#define MC_MODUL_BASE 0xBF800000 -#define MC_ERRCAUSE(value) 0x0010(value) -#define MC_ERRADDR(value) 0x0020(value) -#define MC_CON(value) 0x0060(value) - -#define MC_SRAM_ENABLE 0x00000004 -#define MC_SDRAM_ENABLE 0x00000002 -#define MC_DDRRAM_ENABLE 0x00000001 - -#define MC_SDR_MODUL_BASE 0xBF800200 -#define MC_IOGP(value) 0x0000(value) -#define MC_CTRLENA(value) 0x0010(value) -#define MC_MRSCODE(value) 0x0020(value) -#define MC_CFGDW(value) 0x0030(value) -#define MC_CFGPB0(value) 0x0040(value) -#define MC_LATENCY(value) 0x0080(value) -#define MC_TREFRESH(value) 0x0090(value) -#define MC_SELFRFSH(value) 0x00A0(value) - -#define MC_DDR_MODUL_BASE 0xBF801000 -#define MC_DC00(value) 0x0000(value) -#define MC_DC01(value) 0x0010(value) -#define MC_DC02(value) 0x0020(value) -#define MC_DC03(value) 0x0030(value) -#define MC_DC04(value) 0x0040(value) -#define MC_DC05(value) 0x0050(value) -#define MC_DC06(value) 0x0060(value) -#define MC_DC07(value) 0x0070(value) -#define MC_DC08(value) 0x0080(value) -#define MC_DC09(value) 0x0090(value) -#define MC_DC10(value) 0x00A0(value) -#define MC_DC11(value) 0x00B0(value) -#define MC_DC12(value) 0x00C0(value) -#define MC_DC13(value) 0x00D0(value) -#define MC_DC14(value) 0x00E0(value) -#define MC_DC15(value) 0x00F0(value) -#define MC_DC16(value) 0x0100(value) -#define MC_DC17(value) 0x0110(value) -#define MC_DC18(value) 0x0120(value) -#define MC_DC19(value) 0x0130(value) -#define MC_DC20(value) 0x0140(value) -#define MC_DC21(value) 0x0150(value) -#define MC_DC22(value) 0x0160(value) -#define MC_DC23(value) 0x0170(value) -#define MC_DC24(value) 0x0180(value) -#define MC_DC25(value) 0x0190(value) -#define MC_DC26(value) 0x01A0(value) -#define MC_DC27(value) 0x01B0(value) -#define MC_DC28(value) 0x01C0(value) -#define MC_DC29(value) 0x01D0(value) -#define MC_DC30(value) 0x01E0(value) -#define MC_DC31(value) 0x01F0(value) -#define MC_DC32(value) 0x0200(value) -#define MC_DC33(value) 0x0210(value) -#define MC_DC34(value) 0x0220(value) -#define MC_DC35(value) 0x0230(value) -#define MC_DC36(value) 0x0240(value) -#define MC_DC37(value) 0x0250(value) -#define MC_DC38(value) 0x0260(value) -#define MC_DC39(value) 0x0270(value) -#define MC_DC40(value) 0x0280(value) -#define MC_DC41(value) 0x0290(value) -#define MC_DC42(value) 0x02A0(value) -#define MC_DC43(value) 0x02B0(value) -#define MC_DC44(value) 0x02C0(value) -#define MC_DC45(value) 0x02D0(value) -#define MC_DC46(value) 0x02E0(value) - -#define RCU_OFFSET 0xBF203000 -#define RCU_RST_REQ (RCU_OFFSET + 0x0010) -#define RCU_STS (RCU_OFFSET + 0x0014) - -#define CGU_OFFSET 0xBF103000 -#define PLL0_CFG (CGU_OFFSET + 0x0004) -#define PLL1_CFG (CGU_OFFSET + 0x0008) -#define PLL2_CFG (CGU_OFFSET + 0x000C) -#define CGU_SYS (CGU_OFFSET + 0x0010) -#define CGU_UPDATE (CGU_OFFSET + 0x0014) -#define IF_CLK (CGU_OFFSET + 0x0018) -#define CGU_SMD (CGU_OFFSET + 0x0020) -#define CGU_CT1SR (CGU_OFFSET + 0x0028) -#define CGU_CT2SR (CGU_OFFSET + 0x002C) -#define CGU_PCMCR (CGU_OFFSET + 0x0030) -#define PCI_CR_PCI (CGU_OFFSET + 0x0034) -#define CGU_OSC_CTRL (CGU_OFFSET + 0x001C) -#define CGU_MIPS_PWR_DWN (CGU_OFFSET + 0x0038) -#define CLK_MEASURE (CGU_OFFSET + 0x003C) - -//05252006 -#define pll0_35MHz_CONFIG 0x9D861059 -#define pll1_35MHz_CONFIG 0x1A260CD9 -#define pll2_35MHz_CONFIG 0x8000f1e5 -#define pll0_36MHz_CONFIG 0x1000125D -#define pll1_36MHz_CONFIG 0x1B1E0C99 -#define pll2_36MHz_CONFIG 0x8002f2a1 -//05252006 - -//06063001-joelin disable the PCI CFRAME mask -start -/*CFRAME is an I/O signal, in the chip, the output CFRAME is selected via GPIO altsel pins, so if you select MII1 RXD1, the CFRAME will not come out. -But the CFRAME input still take the signal from the pad and not disabled when altsel choose other function. So when MII1_RXD1 is low from other device, the EBU interface will be disabled. - -The chip function in such a way that disable the CFRAME mask mean EBU not longer check CFRAME to be the device using the bus. -The side effect is the entire PCI block will see CFRAME low all the time meaning PCI cannot use the bus at all so no more PCI function. -*/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CONFIG_SPACE 0xB7000000 -#define CS_CFM (PCI_CONFIG_SPACE + 0x6C) -//06063001-joelin disable the PCI CFRAME mask -end - .set noreorder - - -/* - * void ebu_init(long) - * - * a0 has the clock value we are going to run at - */ - .globl ebu_init - .ent ebu_init -ebu_init: -/*TODO:liupeng */ - j ra - nop - - .end ebu_init - - -/* - * void cgu_init(long) - * - * a0 has the clock value - */ - .globl cgu_init - .ent cgu_init -cgu_init: - li t2, CGU_SYS - lw t2,0(t2) - beq t2,a0,freq_up2date - nop - - li t2, RCU_STS - lw t2, 0(t2) - and t2,0x00020000 - beq t2,0x00020000,boot_36MHZ - nop -//05252006 - li t1, PLL0_CFG - li t2, pll0_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_35MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_35MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) - b wait_reset - nop -boot_36MHZ: - li t1, PLL0_CFG - li t2, pll0_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL1_CFG - li t2, pll1_36MHz_CONFIG - sw t2,0(t1) - li t1, PLL2_CFG - li t2, pll2_36MHz_CONFIG - sw t2,0(t1) - li t1, CGU_SYS - sw a0,0(t1) - li t1, RCU_RST_REQ - li t2, 0x40000008 - sw t2,0(t1) -//05252006 - -wait_reset: - b wait_reset - nop -freq_up2date: - j ra - nop - .end cgu_init - - -/* - * void sdram_init(long) - * - * a0 has the clock value - */ - .globl sdram_init - .ent sdram_init -sdram_init: - - /* SDRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable SDRAM module in memory controller */ - li t3, MC_SDRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_SDR_MODUL_BASE - - /* disable the controller */ - li t2, 0 - sw t2, MC_CTRLENA(t1) - - li t2, 0x822 - sw t2, MC_IOGP(t1) - - li t2, 0x2 - sw t2, MC_CFGDW(t1) - - /* Set CAS Latency */ - li t2, 0x00000020 - sw t2, MC_MRSCODE(t1) - - /* Set CS0 to SDRAM parameters */ - li t2, 0x000014d8 - sw t2, MC_CFGPB0(t1) - - /* Set SDRAM latency parameters */ - li t2, 0x00036325; /* BC PC100 */ - sw t2, MC_LATENCY(t1) - - /* Set SDRAM refresh rate */ - li t2, 0x00000C30 - sw t2, MC_TREFRESH(t1) - - /* Clear Power-down registers */ - sw zero, MC_SELFRFSH(t1) - - /* Finally enable the controller */ - li t2, 1 - sw t2, MC_CTRLENA(t1) - - - j ra - nop - - - .end sdram_init - -/* - * void ddrram_init(long) - * - * a0 has the clock value - */ - .globl ddrram_init - .ent ddrram_init -ddrram_init: - - /* DDR-DRAM Initialization - */ - li t1, MC_MODUL_BASE - - /* Clear Error log registers */ - sw zero, MC_ERRCAUSE(t1) - sw zero, MC_ERRADDR(t1) - - /* Enable DDR module in memory controller */ - li t3, MC_DDRRAM_ENABLE - lw t2, MC_CON(t1) - or t3, t2, t3 - sw t3, MC_CON(t1) - - li t1, MC_DDR_MODUL_BASE - - /* Write configuration to DDR controller registers */ - li t2, MC_DC0_VALUE - sw t2, MC_DC00(t1) - - li t2, MC_DC1_VALUE - sw t2, MC_DC01(t1) - - li t2, MC_DC2_VALUE - sw t2, MC_DC02(t1) - - li t2, MC_DC3_VALUE - sw t2, MC_DC03(t1) - - li t2, MC_DC4_VALUE - sw t2, MC_DC04(t1) - - li t2, MC_DC5_VALUE - sw t2, MC_DC05(t1) - - li t2, MC_DC6_VALUE - sw t2, MC_DC06(t1) - - li t2, MC_DC7_VALUE - sw t2, MC_DC07(t1) - - li t2, MC_DC8_VALUE - sw t2, MC_DC08(t1) - - li t2, MC_DC9_VALUE - sw t2, MC_DC09(t1) - - li t2, MC_DC10_VALUE - sw t2, MC_DC10(t1) - - li t2, MC_DC11_VALUE - sw t2, MC_DC11(t1) - - li t2, MC_DC12_VALUE - sw t2, MC_DC12(t1) - - li t2, MC_DC13_VALUE - sw t2, MC_DC13(t1) - - li t2, MC_DC14_VALUE - sw t2, MC_DC14(t1) - - li t2, MC_DC15_VALUE - sw t2, MC_DC15(t1) - - li t2, MC_DC16_VALUE - sw t2, MC_DC16(t1) - - li t2, MC_DC17_VALUE - sw t2, MC_DC17(t1) - - li t2, MC_DC18_VALUE - sw t2, MC_DC18(t1) - - li t2, MC_DC19_VALUE - sw t2, MC_DC19(t1) - - li t2, MC_DC20_VALUE - sw t2, MC_DC20(t1) - - li t2, MC_DC21_VALUE - sw t2, MC_DC21(t1) - - li t2, MC_DC22_VALUE - sw t2, MC_DC22(t1) - - li t2, MC_DC23_VALUE - sw t2, MC_DC23(t1) - - li t2, MC_DC24_VALUE - sw t2, MC_DC24(t1) - - li t2, MC_DC25_VALUE - sw t2, MC_DC25(t1) - - li t2, MC_DC26_VALUE - sw t2, MC_DC26(t1) - - li t2, MC_DC27_VALUE - sw t2, MC_DC27(t1) - - li t2, MC_DC28_VALUE - sw t2, MC_DC28(t1) - - li t2, MC_DC29_VALUE - sw t2, MC_DC29(t1) - - li t2, MC_DC30_VALUE - sw t2, MC_DC30(t1) - - li t2, MC_DC31_VALUE - sw t2, MC_DC31(t1) - - li t2, MC_DC32_VALUE - sw t2, MC_DC32(t1) - - li t2, MC_DC33_VALUE - sw t2, MC_DC33(t1) - - li t2, MC_DC34_VALUE - sw t2, MC_DC34(t1) - - li t2, MC_DC35_VALUE - sw t2, MC_DC35(t1) - - li t2, MC_DC36_VALUE - sw t2, MC_DC36(t1) - - li t2, MC_DC37_VALUE - sw t2, MC_DC37(t1) - - li t2, MC_DC38_VALUE - sw t2, MC_DC38(t1) - - li t2, MC_DC39_VALUE - sw t2, MC_DC39(t1) - - li t2, MC_DC40_VALUE - sw t2, MC_DC40(t1) - - li t2, MC_DC41_VALUE - sw t2, MC_DC41(t1) - - li t2, MC_DC42_VALUE - sw t2, MC_DC42(t1) - - li t2, MC_DC43_VALUE - sw t2, MC_DC43(t1) - - li t2, MC_DC44_VALUE - sw t2, MC_DC44(t1) - - li t2, MC_DC45_VALUE - sw t2, MC_DC45(t1) - - li t2, MC_DC46_VALUE - sw t2, MC_DC46(t1) - - li t2, 0x00000100 - sw t2, MC_DC03(t1) - - j ra - nop - - - .end ddrram_init - - .globl lowlevel_init - .ent lowlevel_init -lowlevel_init: - /* EBU, CGU and SDRAM/DDR-RAM Initialization. - */ - move t0, ra - /* We rely on the fact that neither cgu_init() nor sdram_init() - * modify t0 - */ -#ifdef DANUBE_BOOT_FROM_EBU -#ifdef DANUBE_DDR_RAM_166M -//05252006 - /* 0xe8 means CPU0/CPU1 333M, DDR 167M, FPI 83M, PPE 240M */ - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef PROMOSDDR400 - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DDR_SAMSUNG_166M - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DDR_PSC_166M - li a0,0xe8 - bal cgu_init - nop -#endif -#ifdef DANUBE_DDR_RAM_133M - li a0,0xe9 -//05252006 - bal cgu_init - nop -#endif -#endif -/*TODO:liupeng add this define !!!! */ -/* - #define DANUBE_BOOT_FROM_EBU - #define DANUBE_USE_DDR_RAM -*/ - -//06063001-joelin disable the PCI CFRAME mask-start -#ifdef DISABLE_CFRAME - li t1, PCI_CR_PCI //mw bf103034 80000000 - li t2, 0x80000000 - sw t2,0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x103 - sw t2,0(t1) - - li t1, CS_CFM //mw b700006c 0 - li t2, 0x00 - sw t2, 0(t1) - - li t1, PCI_CR_PCI_MOD_REG //mw be105430 103 - li t2, 0x1000103 - sw t2, 0(t1) -#endif -//06063001-joelin disable the PCI CFRAME mask-end - -#ifdef DANUBE_BOOT_FROM_EBU -#ifdef DANUBE_USE_DDR_RAM - bal ddrram_init - nop -#else - bal sdram_init - nop -#endif -#endif - - move ra, t0 - j ra - nop - - .end lowlevel_init diff --git a/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S b/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S deleted file mode 100644 index e0d7971..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/pmuenable.S +++ /dev/null @@ -1,48 +0,0 @@ -/* - * Power Management unit initialization code for AMAZON development board. - * - * Copyright (c) 2003 Ou Ke, Infineon. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> -#include <version.h> -#include <asm/regdef.h> - -#define PMU_PWDCR 0xBF10201C -#define PMU_SR 0xBF102020 - - .globl pmuenable - -pmuenable: - li t0, PMU_PWDCR - li t1, 0x2 /* enable everything */ - sw t1, 0(t0) -#if 0 -1: - li t0, PMU_SR - lw t2, 0(t0) - bne t1, t2, 1b - nop -#endif - j ra - nop - - diff --git a/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds b/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds deleted file mode 100644 index 36c658b..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/u-boot-bootstrap.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start_bootstrap) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start_bootstrap = .; - .got : { *(.got) } - __got_end_bootstrap = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start_bootstrap = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end_bootstrap = .; - - uboot_end_data_bootstrap = .; - num_got_entries = (__got_end_bootstrap - __got_start_bootstrap) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end_bootstrap = .; -} diff --git a/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds b/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds deleted file mode 100644 index 4064516..0000000 --- a/package/uboot-ifxmips/files/board/ifx/danube/u-boot.lds +++ /dev/null @@ -1,69 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk Engineering, <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* -OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips") -*/ -OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradbigmips") -OUTPUT_ARCH(mips) -ENTRY(_start) -SECTIONS -{ - . = 0x00000000; - - . = ALIGN(4); - .text : - { - *(.text) - } - - . = ALIGN(4); - .rodata : { *(.rodata*) } - - . = ALIGN(4); - .data : { *(.data*) } - - . = ALIGN(4); - .sdata : { *(.sdata) } - - _gp = ALIGN(16); - - __got_start = .; - .got : { *(.got) } - __got_end = .; - - .sdata : { *(.sdata) } - - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; - - uboot_end_data = .; - num_got_entries = (__got_end - __got_start) >> 2; - - . = ALIGN(4); - .sbss : { *(.sbss) } - .bss : { *(.bss) } - uboot_end = .; -} diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/Makefile b/package/uboot-ifxmips/files/cpu/mips/danube/Makefile deleted file mode 100644 index 6f7b5dc..0000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/Makefile +++ /dev/null @@ -1,46 +0,0 @@ -######################################################################### -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(SOC).a - -COBJS = ifx_asc.o ifx_clock.o - -SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) - -all: $(obj).depend $(LIB) - -$(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c deleted file mode 100644 index 52c6cb2..0000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_asc.c +++ /dev/null @@ -1,257 +0,0 @@ -/***************************************************************************** - * DANUBE BootROM - * Copyright (c) 2005, Infineon Technologies AG, All rights reserved - * IFAP DC COM SD - *****************************************************************************/ - -#include <config.h> -//#include <lib.h> -#include <asm/danube.h> -#include <asm/addrspace.h> -#include <asm/ifx_asc.h> - - -#define ASC_FIFO_PRESENT -#define SET_BIT(reg, mask) reg |= (mask) -#define CLEAR_BIT(reg, mask) reg &= (~mask) -#define CLEAR_BITS(reg, mask) CLEAR_BIT(reg, mask) -#define SET_BITS(reg, mask) SET_BIT(reg, mask) -#define SET_BITFIELD(reg, mask, off, val) {reg &= (~mask); reg |= (val << off);} - - -typedef unsigned char u8; -typedef unsigned short u16; -typedef unsigned long u32; -typedef signed long s32; -typedef unsigned int uint; -typedef unsigned long ulong; -typedef volatile unsigned short vuint; - - - -void serial_setbrg (void); - -/*TODO: undefine this !!!*/ -#undef DEBUG_ASC_RAW -#ifdef DEBUG_ASC_RAW -#define DEBUG_ASC_RAW_RX_BUF 0xA0800000 -#define DEBUG_ASC_RAW_TX_BUF 0xA0900000 -#endif - -static volatile DanubeAsc_t *pAsc = (DanubeAsc_t *)DANUBE_ASC1; - -typedef struct{ - u16 fdv; /* 0~511 fractional divider value*/ - u16 reload; /* 13 bit reload value*/ -} ifx_asc_baud_reg_t; - -#ifdef ON_VENUS -/*9600 @1.25M rel 00.08*/ -//#define FDV 503 -//#define RELOAD 7 -/*9600 @0.625M rel final00.01 & rtl_freeze*/ -#define FDV 503 -#define RELOAD 3 -/* first index is DDR_SEL, second index is FPI_SEL */ -#endif -static ifx_asc_baud_reg_t g_danube_asc_baud[4][2] = -{ -#ifdef ON_VENUS - {{503,3},{503,3}}, /* 1152000 @ 166.67M and half*/ - {{503,3},{503,3}}, /* 1152000 @ 133.3M and half*/ - {{503,3},{503,3}}, /* 1152000 @ 111.11M and half*/ - {{503.3},{503,3}} /* 1152000 @ 83.33M and half*/ -#else -/* TAPEOUT table */ - {{436,76},{419,36}}, /* 1152000 @ 166.67M and half*/ - {{453,63},{453,31}}, /* 1152000 @ 133.3M and half*/ - {{501,58},{510,29}}, /* 1152000 @ 111.11M and half*/ - {{419.36},{453,19}} /* 1152000 @ 83.33M and half*/ -#endif -}; -/****************************************************************************** -* -* asc_init - initialize a Danube ASC channel -* -* This routine initializes the number of data bits, parity -* and set the selected baud rate. Interrupts are disabled. -* Set the modem control signals if the option is selected. -* -* RETURNS: N/A -*/ - -int serial_init (void) -{ - - /* and we have to set CLC register*/ - CLEAR_BIT(pAsc->asc_clc, ASCCLC_DISS); - SET_BITFIELD(pAsc->asc_clc, ASCCLC_RMCMASK, ASCCLC_RMCOFFSET, 0x0001); - - /* initialy we are in async mode */ - pAsc->asc_con = ASCCON_M_8ASYNC; - - /* select input port */ - pAsc->asc_pisel = (CONSOLE_TTY & 0x1); - - /* TXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCTXFCON_TXFITLMASK, - ASCTXFCON_TXFITLOFF, DANUBEASC_TXFIFO_FL); - /* enable TXFIFO */ - SET_BIT(pAsc->asc_txfcon, ASCTXFCON_TXFEN); - - /* RXFIFO's filling level */ - SET_BITFIELD(pAsc->asc_txfcon, ASCRXFCON_RXFITLMASK, - ASCRXFCON_RXFITLOFF, DANUBEASC_RXFIFO_FL); - /* enable RXFIFO */ - SET_BIT(pAsc->asc_rxfcon, ASCRXFCON_RXFEN); - - /* set baud rate */ - serial_setbrg(); - - /* enable error signals & Receiver enable */ - SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_SETREN|ASCCON_FEN|ASCCON_TOEN|ASCCON_ROEN); - - return 0; -} - -void serial_setbrg (void) -{ - u32 uiReloadValue, fdv; - -#if defined(ON_IKOS) - /*1200 @77K */ - fdv=472; - uiReloadValue=5; -#else - /*venus & tapeout */ - u32 ddr_sel,fpi_sel; - ddr_sel = (* DANUBE_CGU_SYS) & 0x3; - fpi_sel = ((* DANUBE_CGU_SYS) & 0x40)?1:0; - fdv= g_danube_asc_baud[ddr_sel][fpi_sel].fdv; - uiReloadValue=g_danube_asc_baud[ddr_sel][fpi_sel].reload; -#endif //ON_IKOS - /* Disable Baud Rate Generator; BG should only be written when R=0 */ - CLEAR_BIT(pAsc->asc_con, ASCCON_R); - - /* Enable Fractional Divider */ - SET_BIT(pAsc->asc_con, ASCCON_FDE); /* FDE = 1 */ - - /* Set fractional divider value */ - pAsc->asc_fdv = fdv & ASCFDV_VALUE_MASK; - - /* Set reload value in BG */ - pAsc->asc_bg = uiReloadValue; - - /* Enable Baud Rate Generator */ - SET_BIT(pAsc->asc_con, ASCCON_R); /* R = 1 */ -} - - -void serial_putc (const char c) -{ - u32 txFl = 0; -#ifdef DEBUG_ASC_RAW - static u8 * debug = (u8 *) DEBUG_ASC_RAW_TX_BUF; - *debug++=c; -#endif - if (c == '\n') - serial_putc ('\r'); - /* check do we have a free space in the TX FIFO */ - /* get current filling level */ - do - { - txFl = ( pAsc->asc_fstat & ASCFSTAT_TXFFLMASK ) >> ASCFSTAT_TXFFLOFF; - } - while ( txFl == DANUBEASC_TXFIFO_FULL ); - - pAsc->asc_tbuf = c; /* write char to Transmit Buffer Register */ - - /* check for errors */ - if ( pAsc->asc_state & ASCSTATE_TOE ) - { - SET_BIT(pAsc->asc_whbstate, ASCWHBSTATE_CLRTOE); - return; - } -} - -void serial_puts (const char *s) -{ - while (*s) - { - serial_putc (*s++); - } -} - -int asc_inb(int timeout) -{ - u32 symbol_mask; - char c; - while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) { - } - symbol_mask = ((ASC_OPTIONS & ASCOPT_CSIZE) == ASCOPT_CS7) ? (0x7f) : (0xff); - c = (char)(pAsc->asc_rbuf & symbol_mask); - return (c); -} - -int serial_getc (void) -{ - char c; - while ((pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ); - c = (char)(pAsc->asc_rbuf & 0xff); - -#ifdef DEBUG_ASC_RAW - static u8* debug=(u8*)(DEBUG_ASC_RAW_RX_BUF); - *debug++=c; -#endif - return c; -} - - - -int serial_tstc (void) -{ - int res = 1; - -#ifdef ASC_FIFO_PRESENT - if ( (pAsc->asc_fstat & ASCFSTAT_RXFFLMASK) == 0 ) - { - res = 0; - } -#else - if (!(*(volatile unsigned long*)(SFPI_INTCON_BASEADDR + FBS_ISR) & - FBS_ISR_AR)) - - { - res = 0; - } -#endif -#if 0 - else if ( pAsc->asc_con & ASCCON_FE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRFE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_PE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLRPE); - res = 0; - } - else if ( pAsc->asc_con & ASCCON_OE ) - { - SET_BIT(pAsc->asc_whbcon, ASCWHBCON_CLROE); - res = 0; - } -#endif - return res; -} - - -int serial_start(void) -{ - return 1; -} - -int serial_stop(void) -{ - return 1; -} diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S deleted file mode 100644 index fc482dc..0000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cache.S +++ /dev/null @@ -1,60 +0,0 @@ - -#define IFX_CACHE_EXTRA_INVALID_TAG \ - mtc0 zero, CP0_TAGLO, 1; \ - mtc0 zero, CP0_TAGLO, 2; \ - mtc0 zero, CP0_TAGLO, 3; \ - mtc0 zero, CP0_TAGLO, 4; - -#define IFX_CACHE_EXTRA_OPERATION \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t2; /* icacheSize */ \ - move a3, t4; /* icacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_I)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - /* 1: initialise dcache tags. */ \ - \ - /* cache line size */ \ - li a2, CFG_CACHELINE_SIZE; \ - /* kseg0 mem address */ \ - li a1, 0; \ - li a3, CFG_CACHE_SETS * CFG_CACHE_WAYS; \ -1: \ - /* store tag (invalid, not locked) */ \ - cache 0x8, 0(a1); \ - cache 0x9, 0(a1); \ - \ - add a3, -1; \ - bne a3, zero, 1b; \ - add a1, a2; \ - \ - /* set WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ECCF_WST; \ - or a0, a1; \ - mtc0 a0, CP0_ECC; \ - \ - li a0, K0BASE; \ - move a2, t3; /* dcacheSize */ \ - move a3, t5; /* dcacheLineSize */ \ - move a1, a2; \ - icacheop(a0,a1,a2,a3,(Index_Store_Tag_D)); \ - \ - /* clear WST bit */ \ - mfc0 a0, CP0_ECC; \ - li a1, ~ECCF_WST; \ - and a0, a1; \ - mtc0 a0, CP0_ECC; - diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c deleted file mode 100644 index c67cf15..0000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_clock.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm-mips/danube.h> - - - -/******************************************************************************* -* -* get_cpuclk - returns the frequency of the CPU. -* -* NOTE: -* This functions should be used by the hardware driver to get the correct -* frequency of the CPU. -*/ - -unsigned int danube_get_ddr_hz(void) -{ - switch((*DANUBE_CGU_SYS) & 0x3){ - case 0: - default: - return 166666667; - case 1: - return 133333333; - case 2: - return 111111111; - case 3: - return 83333333; - } -} - - -uint danube_get_cpuclk(void) -{ -#ifdef CONFIG_USE_EMULATOR - return EMULATOR_CPU_SPEED; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=danube_get_ddr_hz(); - switch((*DANUBE_CGU_SYS) & 0xc){ - case 0: - default: - return 333333333; - case 4: - return ddr_clock; - case 8: - return ddr_clock << 1; - } -#endif -} - - -uint danube_get_fpiclk(void) -{ -#ifdef CONFIG_USE_EMULATOR - unsigned int clkCPU; - clkCPU = danube_get_cpu_hz(); - return clkCPU >> 2; -#else //NOT CONFIG_USE_EMULATOR - unsigned int ddr_clock=danube_get_ddr_hz(); - if ((*DANUBE_CGU_SYS) & 0x40){ - return ddr_clock >> 1; - } - return ddr_clock; -#endif -} - - diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c deleted file mode 100644 index 49355de..0000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_cpu.c +++ /dev/null @@ -1,5 +0,0 @@ - -#define IFX_CPU_RESET \ -{ *DANUBE_RCU_RST_REQ |=1<<30; \ -} - diff --git a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S b/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S deleted file mode 100644 index 17c0b0a..0000000 --- a/package/uboot-ifxmips/files/cpu/mips/danube/ifx_start.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * IFX Platform Dependent CPU Initializations - * - for Danube - */ - -#define IFX_EBU_BOOTCFG_DWORD \ - .word INFINEON_EBU_BOOTCFG; /* EBU init code, fetched during booting */ \ - .word 0x00000000; /* phases of the flash */ - -#define IFX_MORE_RESERVED_VECTORS \ - XVECENT(romExcHandle,0x400); /* Int, CauseIV=1 */ \ - RVECENT(romReserved,129); \ - RVECENT(romReserved,130); \ - RVECENT(romReserved,131); \ - RVECENT(romReserved,132); \ - RVECENT(romReserved,133); \ - RVECENT(romReserved,134); \ - RVECENT(romReserved,135); \ - RVECENT(romReserved,136); \ - RVECENT(romReserved,137); \ - RVECENT(romReserved,138); \ - RVECENT(romReserved,139); \ - RVECENT(romReserved,140); \ - RVECENT(romReserved,141); \ - RVECENT(romReserved,142); \ - RVECENT(romReserved,143); \ - RVECENT(romExcHandle,0x480); /* EJTAG debug exception */ - -#define IFX_RESET_PRECHECK \ - mfc0 k0, CP0_EBASE; \ - and k0, EBASEF_CPUNUM; \ - bne k0, zero, ifx_mips_handler_1; \ - nop; - -#define IFX_CPU_EXTRA_INIT \ - mfc0 k0, CP0_CONFIG, 7; \ - li k1, 0x04; \ - or k0, k1; \ - mtc0 k0, CP0_CONFIG, 7; - -#define IFX_CACHE_OPER_MODE \ - li t0, CONF_CM_CACHABLE_NO_WA; - -/* - * Stop VCPU - */ -#define IFX_MIPS_HANDLER_1 \ - wait; \ - b ifx_mips_handler_1; \ - nop; - diff --git a/package/uboot-ifxmips/files/danube_ref_ddr166.conf b/package/uboot-ifxmips/files/danube_ref_ddr166.conf deleted file mode 100755 index 351d6a1..0000000 --- a/package/uboot-ifxmips/files/danube_ref_ddr166.conf +++ /dev/null @@ -1,134 +0,0 @@ - 0xbf800060 0x7 - 0xbf800010 0x0 - 0xbf800020 0x0 - 0xbf800200 0x02 - 0xbf800210 0x0 - -;REG32(MC_DC0) = 0x00001B1B; - 0xbf801000 0x1b1b -;REG32(MC_DC1) = 0x00000000; - 0xbf801010 0x0 -;REG32(MC_DC2) = 0x00000000; - 0xbf801020 0x0 -;REG32(MC_DC3) = 0x00000000; - 0xbf801030 0x0 -;REG32(MC_DC4) = 0x00000000; - 0xbf801040 0x0 -;REG32(MC_DC5) = 0x00000200; - 0xbf801050 0x200 -;REG32(MC_DC6) = 0x00000306; -; 0xbf801060 0x0306 - 0xbf801060 0x0605 -;REG32(MC_DC7) = 0x00000303; - 0xbf801070 0x302 -; 0xbf801070 0x0203 -;REG32(MC_DC8) = 0x00000102; - 0xbf801080 0x102 -;REG32(MC_DC9) = 0x0000070A; - 0xbf801090 0x70a -; 0xbf801090 0x608 -;REG32(MC_DC10) = 0x00000203; - 0xbf8010a0 0x203 -;REG32(MC_DC11) = 0x00000C02; - 0xbf8010b0 0xc02 -; 0xbf8010b0 0x0a02 -;REG32(MC_DC12) = 0x000001C8; - 0xbf8010c0 0x1c8 -;REG32(MC_DC13) = 0x00000001; - 0xbf8010d0 0x1 -;REG32(MC_DC14) = 0x00000000; - 0xbf8010e0 0x0 -;REG32(MC_DC15) = 0x00000F5F; -; 0xbf8010f0 0xf5f - 0xbf8010f0 0xf3c -;REG32(MC_DC16) = 0x0000C800; - 0xbf801100 0xc800 -;REG32(MC_DC17) = 0x0000000D; -; 0xbf801110 0xd - 0xbf801110 0xd -;REG32(MC_DC18) = 0x00000300; - 0xbf801120 0x300 -;REG32(MC_DC19) = 0x00000300; -; 0xbf801130 0x300 - 0xbf801130 0x200 -;REG32(MC_DC20) = 0x00000A04; -; 0xbf801140 0xa04 - 0xbf801140 0xa04 -;REG32(MC_DC21) = 0x00001c00; - 0xbf801150 0xd00 -; 0xbf801150 0x1f00 -;REG32(MC_DC22) = 0x00001E1E; - 0xbf801160 0xd0d -; 0xbf801160 0x1f1f -;REG32(MC_DC23) = 0x00000000; - 0xbf801170 0x0 -;//Disable ECC -;REG32(MC_DC24) = 0x0000007F; -; 0xbf801180 0x7f - 0xbf801180 0x062 -; 0xbf801180 0x37f -;REG32(MC_DC25) = 0x00000000; - 0xbf801190 0x0 -;REG32(MC_DC26) = 0x00000000; - 0xbf8011a0 0x0 -;REG32(MC_DC27) = 0x00000000; - 0xbf8011b0 0x0 -;REG32(MC_DC28) = 0x00000A24; -; 0xbf8011c0 0xa24 - 0xbf8011c0 0x510 -;REG32(MC_DC29) = 0x00002D89; - 0xbf8011d0 0x2d89 -; 0xbf8011d0 0x2d92 -;REG32(MC_DC30) = 0x00000022; - 0xbf8011e0 0x8300 -; 0xbf8011e0 0x8235 -;REG32(MC_DC31) = 0x00000000; - 0xbf8011f0 0x0 -;REG32(MC_DC32) = 0x00000000; - 0xbf801200 0x0 -;REG32(MC_DC33) = 0x00000000; - 0xbf801210 0x0 -;REG32(MC_DC34) = 0x00000000; - 0xbf801220 0x0 -;REG32(MC_DC35) = 0x00000000; - 0xbf801230 0x0 -;REG32(MC_DC36) = 0x00000000; - 0xbf801240 0x0 -;REG32(MC_DC37) = 0x00000000; - 0xbf801250 0x0 -;REG32(MC_DC38) = 0x00000000; - 0xbf801260 0x0 -;REG32(MC_DC39) = 0x00000000; - 0xbf801270 0x0 -;REG32(MC_DC40) = 0x00000000; - 0xbf801280 0x0 -;REG32(MC_DC41) = 0x00000000; - 0xbf801290 0x0 -;REG32(MC_DC42) = 0x00000000; - 0xbf8012a0 0x0 -;REG32(MC_DC43) = 0x00000000; - 0xbf8012b0 0x0 -;REG32(MC_DC44) = 0x00000000; - 0xbf8012c0 0x0 -;REG32(MC_DC45) = 0x00000600; - 0xbf8012d0 0x500 -;REG32(MC_DC46) = 0x00000000; - 0xbf8012e0 0x0 - - 0xbf800060 0x05 - 0xbf801030 0x100 - - - - - - - - - - - - - - - diff --git a/package/uboot-ifxmips/files/drivers/ifx_sw.c b/package/uboot-ifxmips/files/drivers/ifx_sw.c deleted file mode 100644 index ac0415a..0000000 --- a/package/uboot-ifxmips/files/drivers/ifx_sw.c +++ /dev/null @@ -1,459 +0,0 @@ -/* - * DANUBE internal switch ethernet driver. - * - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - - -#include <common.h> - -#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) \ - && defined(CONFIG_DANUBE_SWITCH) - -#include <malloc.h> -#include <net.h> -#include <asm/danube.h> -#include <asm/addrspace.h> -#include <asm/pinstrap.h> - -#define MII_MODE 1 -#define REV_MII_MODE 2 - -#define TX_CHAN_NO 7 -#define RX_CHAN_NO 6 - -#define NUM_RX_DESC PKTBUFSRX -#define NUM_TX_DESC 8 -#define MAX_PACKET_SIZE 1536 -#define TOUT_LOOP 100 -#define PHY0_ADDR 1 /*fixme: set the correct value here*/ - -#define DMA_WRITE_REG(reg, value) *((volatile u32 *)reg) = (u32)value -#define DMA_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) - -#define SW_WRITE_REG(reg, value) *((volatile u32*)reg) = (u32)value -#define SW_READ_REG(reg, value) value = (u32)*((volatile u32*)reg) - -#define TANTOS_CHIP_ID 0x2599 - -typedef struct -{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 reserved :3; - volatile u32 Byteoffset :2; - volatile u32 reserve :7; - volatile u32 DataLen :16; - }field; - - volatile u32 word; - }status; - - volatile u32 DataPtr; -} danube_rx_descriptor_t; - -typedef struct -{ - union - { - struct - { - volatile u32 OWN :1; - volatile u32 C :1; - volatile u32 Sop :1; - volatile u32 Eop :1; - volatile u32 Byteoffset :5; - volatile u32 reserved :7; - volatile u32 DataLen :16; - }field; - - volatile u32 word; - }status; - - volatile u32 DataPtr; -} danube_tx_descriptor_t; - - - - -static danube_rx_descriptor_t rx_des_ring[NUM_RX_DESC] __attribute__ ((aligned(8))); -static danube_tx_descriptor_t tx_des_ring[NUM_TX_DESC] __attribute__ ((aligned(8))); -static int tx_num, rx_num; - -int danube_switch_init(struct eth_device *dev, bd_t * bis); -int danube_switch_send(struct eth_device *dev, volatile void *packet,int length); -int danube_switch_recv(struct eth_device *dev); -void danube_switch_halt(struct eth_device *dev); -static void danube_init_switch_chip(int mode); -static void danube_dma_init(void); - - - -int danube_switch_initialize(bd_t * bis) -{ - struct eth_device *dev; - unsigned short chipid; - -#if 0 - printf("Entered danube_switch_initialize()\n"); -#endif - - if (!(dev = (struct eth_device *) malloc (sizeof *dev))) - { - printf("Failed to allocate memory\n"); - return 0; - } - memset(dev, 0, sizeof(*dev)); - - danube_dma_init(); - danube_init_switch_chip(REV_MII_MODE); - -#ifdef CLK_OUT2_25MHZ - *DANUBE_GPIO_P0_DIR=0x0000ae78; - *DANUBE_GPIO_P0_ALTSEL0=0x00008078; - //joelin for Mii-1 *DANUBE_GPIO_P0_ALTSEL1=0x80000080; - *DANUBE_GPIO_P0_ALTSEL1=0x80000000; //joelin for Mii-1 - *DANUBE_CGU_IFCCR=0x00400010; - *DANUBE_GPIO_P0_OD=0x0000ae78; -#endif - - /*patch for 6996*/ - - *DANUBE_RCU_RST_REQ |=1; - mdelay(200); - *DANUBE_RCU_RST_REQ &=(unsigned long)~1; - mdelay(1); - /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602; - */ - /*while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602; - */ - /***************/ - sprintf(dev->name, "danube Switch"); - dev->init = danube_switch_init; - dev->halt = danube_switch_halt; - dev->send = danube_switch_send; - dev->recv = danube_switch_recv; - - eth_register(dev); - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0xc1010000; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - chipid = (unsigned short)(*DANUBE_PPE_ETOP_MDIO_ACC & 0xffff); - - if (chipid != TANTOS_CHIP_ID) // not tantos switch. - { - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F; - while((*DANUBE_PPE_ETOP_MDIO_ACC)&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8003840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8005840F; - //while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - //*DANUBE_PPE_ETOP_MDIO_ACC =0x8006840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8007840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8008840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x8001840F; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80123602; -#ifdef CLK_OUT2_25MHZ - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80334000; -#endif - } - else // Tantos switch chip - { - //printf("Tantos Switch detected!!\n\r"); - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80a10004; - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80c10004; - - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - *DANUBE_PPE_ETOP_MDIO_ACC =0x80f50773; - - /* Software workaround. */ - /* PHY reset from P0 to P4. */ - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - - mdelay(1); - *DANUBE_PPE_ETOP_MDIO_ACC =0x81218000; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P0 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200400; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P1 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200420; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P2 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200440; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* P3 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200460; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - /* p4 */ - *DANUBE_PPE_ETOP_MDIO_ACC =0x81200480; - while(*DANUBE_PPE_ETOP_MDIO_ACC&0x80000000); - mdelay(1); - } - - return 1; -} - -int danube_switch_init(struct eth_device *dev, bd_t * bis) -{ - int i; - - tx_num=0; - rx_num=0; - - /* Reset DMA */ -// serial_puts("i \n\0"); - - *DANUBE_DMA_CS=RX_CHAN_NO; - *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/ - *DANUBE_DMA_CPOLL= 0x80000040; - /*set descriptor base*/ - *DANUBE_DMA_CDBA=(u32)rx_des_ring; - *DANUBE_DMA_CDLEN=NUM_RX_DESC; - *DANUBE_DMA_CIE = 0; - *DANUBE_DMA_CCTRL=0x30000; - - *DANUBE_DMA_CS=TX_CHAN_NO; - *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/ - *DANUBE_DMA_CPOLL= 0x80000040; - *DANUBE_DMA_CDBA=(u32)tx_des_ring; - *DANUBE_DMA_CDLEN=NUM_TX_DESC; - *DANUBE_DMA_CIE = 0; - *DANUBE_DMA_CCTRL=0x30100; - - for(i=0;i < NUM_RX_DESC; i++) - { - danube_rx_descriptor_t * rx_desc = KSEG1ADDR(&rx_des_ring[i]); - rx_desc->status.word=0; - rx_desc->status.field.OWN=1; - rx_desc->status.field.DataLen=PKTSIZE_ALIGN; /* 1536 */ - rx_desc->DataPtr=(u32)KSEG1ADDR(NetRxPackets[i]); - } - - for(i=0;i < NUM_TX_DESC; i++) - { - danube_tx_descriptor_t * tx_desc = KSEG1ADDR(&tx_des_ring[i]); - memset(tx_desc, 0, sizeof(tx_des_ring[0])); - } - /* turn on DMA rx & tx channel - */ - *DANUBE_DMA_CS=RX_CHAN_NO; - *DANUBE_DMA_CCTRL|=1;/*reset and turn on the channel*/ - - return 0; -} - -void danube_switch_halt(struct eth_device *dev) -{ - int i; - for(i=0;i<8;i++) - { - *DANUBE_DMA_CS=i; - *DANUBE_DMA_CCTRL&=~1;/*stop the dma channel*/ - } -// udelay(1000000); -} - -int danube_switch_send(struct eth_device *dev, volatile void *packet,int length) -{ - - int i; - int res = -1; - - danube_tx_descriptor_t * tx_desc= KSEG1ADDR(&tx_des_ring[tx_num]); - - if (length <= 0) - { - printf ("%s: bad packet size: %d\n", dev->name, length); - goto Done; - } - - for(i=0; tx_desc->status.field.OWN==1; i++) - { - if(i>=TOUT_LOOP) - { - printf("NO Tx Descriptor..."); - goto Done; - } - } - - //serial_putc('s'); - - tx_desc->status.field.Sop=1; - tx_desc->status.field.Eop=1; - tx_desc->status.field.C=0; - tx_desc->DataPtr = (u32)KSEG1ADDR(packet); - if(length<60) - tx_desc->status.field.DataLen = 60; - else - tx_desc->status.field.DataLen = (u32)length; - - asm("SYNC"); - tx_desc->status.field.OWN=1; - - res=length; - tx_num++; - if(tx_num==NUM_TX_DESC) tx_num=0; - *DANUBE_DMA_CS=TX_CHAN_NO; - - if(!(*DANUBE_DMA_CCTRL & 1)) - *DANUBE_DMA_CCTRL|=1; - -Done: - return res; -} - -int danube_switch_recv(struct eth_device *dev) -{ - int length = 0; - danube_rx_descriptor_t * rx_desc; - - for (;;) - { - rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]); - - if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1)) - { - break; - } - - length = rx_desc->status.field.DataLen; - if (length) - { - NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_num]), length - 4); - // serial_putc('*'); - } - else - { - printf("Zero length!!!\n"); - } - - rx_desc->status.field.Sop=0; - rx_desc->status.field.Eop=0; - rx_desc->status.field.C=0; - rx_desc->status.field.DataLen=PKTSIZE_ALIGN; - rx_desc->status.field.OWN=1; - rx_num++; - if(rx_num==NUM_RX_DESC) rx_num=0; - - } - - return length; -} - - -static void danube_init_switch_chip(int mode) -{ - /*get and set mac address for MAC*/ - char *tmp; - tmp = getenv ("ethaddr"); - if (NULL == tmp) { - printf("Can't get environment ethaddr!!!\n"); - // return NULL; - } else { - printf("ethaddr=%s\n", tmp); - } - *DANUBE_PMU_PWDCR = *DANUBE_PMU_PWDCR & 0xFFFFEFDF; - *DANUBE_PPE32_ETOP_MDIO_CFG &= ~0x6; - *DANUBE_PPE32_ENET_MAC_CFG = 0x187; - - // turn on port0, set to rmii and turn off port1. - if (mode==REV_MII_MODE) - { - *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x0000000a; - } - else if (mode == MII_MODE) - { - *DANUBE_PPE32_ETOP_CFG = (*DANUBE_PPE32_ETOP_CFG & 0xfffffffc) | 0x00000008; - } - - *DANUBE_PPE32_ETOP_IG_PLEN_CTRL = 0x4005ee; // set packetlen. - *ENET_MAC_CFG |= 1<<11; /*enable the crc*/ - return; -} - - -static void danube_dma_init(void) -{ -// serial_puts("d \n\0"); - - *DANUBE_PMU_PWDCR &=~(1<<DANUBE_PMU_DMA_SHIFT);/*enable DMA from PMU*/ - /* Reset DMA */ - *DANUBE_DMA_CTRL|=1; - *DANUBE_DMA_IRNEN=0;/*disable all the interrupts first*/ - - /* Clear Interrupt Status Register */ - *DANUBE_DMA_IRNCR=0xfffff; - /*disable all the dma interrupts*/ - *DANUBE_DMA_IRNEN=0; - /*disable channel 0 and channel 1 interrupts*/ - - *DANUBE_DMA_CS=RX_CHAN_NO; - *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/ - *DANUBE_DMA_CPOLL= 0x80000040; - /*set descriptor base*/ - *DANUBE_DMA_CDBA=(u32)rx_des_ring; - *DANUBE_DMA_CDLEN=NUM_RX_DESC; - *DANUBE_DMA_CIE = 0; - *DANUBE_DMA_CCTRL=0x30000; - - *DANUBE_DMA_CS=TX_CHAN_NO; - *DANUBE_DMA_CCTRL=0x2;/*fix me, need to reset this channel first?*/ - *DANUBE_DMA_CPOLL= 0x80000040; - *DANUBE_DMA_CDBA=(u32)tx_des_ring; - *DANUBE_DMA_CDLEN=NUM_TX_DESC; - *DANUBE_DMA_CIE = 0; - *DANUBE_DMA_CCTRL=0x30100; - /*enable the poll function and set the poll counter*/ - //*DANUBE_DMA_CPOLL=DANUBE_DMA_POLL_EN | (DANUBE_DMA_POLL_COUNT<<4); - /*set port properties, enable endian conversion for switch*/ - *DANUBE_DMA_PS=0; - *DANUBE_DMA_PCTRL|=0xf<<8;/*enable 32 bit endian conversion*/ - - return; -} - -#endif diff --git a/package/uboot-ifxmips/files/gct b/package/uboot-ifxmips/files/gct deleted file mode 100755 index 09b1261..0000000 --- a/package/uboot-ifxmips/files/gct +++ /dev/null @@ -1,157 +0,0 @@ -#!/usr/bin/perl -my $aline; -my $lineid; -my $length; -my $address; -my @bytes; -my $addstr; -my $chsum=0; -my $count=0; -my $firstime=1; -my $i; -my $currentaddr; -my $tmp; -my $holder=""; -my $loadaddr; - -if(@ARGV < 2){ - print "\n not enough arguments"; - print "\n Syntax: ./program_SDRAM input output\n"; -} - -open(INFILE1, "<$ARGV[0]") || die("\ninput open fail\n"); -open(INFILE2, "<$ARGV[1]") || die("\ninput open fail\n"); -open(OUTFILE, ">$ARGV[2]") || die("\nOutput file open fail\n"); - -$i=0; -while ($line = <INFILE1>){ - if($line=~/\w/){ - if($line!~/[;#\*]/){ - if($i eq 0){ - printf OUTFILE ("33333333"); - } - chomp($line); - $line=~s/\t//; - @array=split(/ +/,$line); - $j=0; - while(@array[$j]!~/\w/) - { - $j=$j+1; - - } - $addr=@array[$j]; - $regval=@array[$j+1]; - $addr=~s/0x//; - $regval=~s/0x//; - printf OUTFILE ("%08x%08x",hex($addr),hex($regval)); - $i=$i+1; - if($i eq 8) - { - $i=0; - printf OUTFILE ("\n"); - } - - } - } - - } - - while($i lt 8 && $i gt 0){ - printf OUTFILE "00"x8; - $i=$i+1; - } - if($i eq 8){ - printf OUTFILE ("\n"); - } - -while($aline=<INFILE2>){ - $aline=uc($aline); - chomp($aline); - next if(($aline=~/^S0/) || ($aline=~/^S7/)); - ($lineid, $length, $address, @bytes) = unpack"A2A2A8"."A2"x300, $aline; - $length = hex($length); - $address = hex($address); - $length -=5; - $i=0; - - while($length>0){ - if($firstime==1){ - $addstr = sprintf("%x", $address); - $addstr = "0"x(8-length($addstr)).$addstr; - print OUTFILE $addstr; - addchsum($addstr); - $firstime=0; - $currentaddr=$address; - $loadaddr = $addstr; - } - else{ - if($count==64){ - $addstr = sprintf("%x", $currentaddr); - $addstr = "0"x(8-length($addstr)).$addstr; - print OUTFILE $addstr; - addchsum($addstr); - $count=0; - } - } - while($count<64){ - $bytes[$i]=~tr/ABCDEF/abcdef/; - print OUTFILE "$bytes[$i]"; - addchsum($bytes[$i]); - $i++; - $count++; - $length--; - last if($length==0); - } - if($count==64){ - print OUTFILE "\n"; - #print OUTFILE "\r"; - $currentaddr+=64; - } - } -} -if($count != 64){ - $tmp = "00"; - for($i=0;$i<(64-$count);$i++){ - print OUTFILE "00"; - addchsum($tmp); - } - print OUTFILE "\n"; - #print OUTFILE "\r"; -} - - -print OUTFILE "11"x4; -use integer; -$chsum=$chsum & 0xffffffff; -$chsum = sprintf("%X", $chsum); -$chsum = "0"x(8-length($chsum)).$chsum; -$chsum =~tr/ABCDEF/abcdef/; -print OUTFILE $chsum; -print OUTFILE "00"x60; -print OUTFILE "\n"; -#print OUTFILE "\r"; - -print OUTFILE "99"x4; -print OUTFILE $loadaddr; -print OUTFILE "00"x60; -print OUTFILE "\n"; -#print OUTFILE "\r"; - - -close OUTFILE; -#END of Program - - - -sub addchsum{ - my $cc=$_[0]; - $holder=$holder.$cc; - if(length($holder)==8){ - $holder = hex($holder); - $chsum+=$holder; - $holder=""; - } -} -#END - - diff --git a/package/uboot-ifxmips/files/include/LzmaDecode.h b/package/uboot-ifxmips/files/include/LzmaDecode.h deleted file mode 100644 index 2870eeb..0000000 --- a/package/uboot-ifxmips/files/include/LzmaDecode.h +++ /dev/null @@ -1,113 +0,0 @@ -/* - LzmaDecode.h - LZMA Decoder interface - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this code, expressly permits you to - statically or dynamically link your code (or bind by name) to the - interfaces of this file without subjecting your linked code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#ifndef __LZMADECODE_H -#define __LZMADECODE_H - -#include "LzmaTypes.h" - -/* #define _LZMA_IN_CB */ -/* Use callback for input data */ - -/* #define _LZMA_OUT_READ */ -/* Use read function for output data */ - -/* #define _LZMA_PROB32 */ -/* It can increase speed on some 32-bit CPUs, - but memory usage will be doubled in that case */ - -/* #define _LZMA_LOC_OPT */ -/* Enable local speed optimizations inside code */ - -#ifdef _LZMA_PROB32 -#define CProb UInt32 -#else -#define CProb UInt16 -#endif - -#define LZMA_RESULT_OK 0 -#define LZMA_RESULT_DATA_ERROR 1 - -#ifdef _LZMA_IN_CB -typedef struct _ILzmaInCallback -{ - int (*Read)(void *object, const unsigned char **buffer, SizeT *bufferSize); -} ILzmaInCallback; -#endif - -#define LZMA_BASE_SIZE 1846 -#define LZMA_LIT_SIZE 768 - -#define LZMA_PROPERTIES_SIZE 5 - -typedef struct _CLzmaProperties -{ - int lc; - int lp; - int pb; - #ifdef _LZMA_OUT_READ - UInt32 DictionarySize; - #endif -}CLzmaProperties; - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size); - -#define LzmaGetNumProbs(Properties) (LZMA_BASE_SIZE + (LZMA_LIT_SIZE << ((Properties)->lc + (Properties)->lp))) - -#define kLzmaNeedInitId (-2) - -typedef struct _CLzmaDecoderState -{ - CLzmaProperties Properties; - CProb *Probs; - - #ifdef _LZMA_IN_CB - const unsigned char *Buffer; - const unsigned char *BufferLim; - #endif - - #ifdef _LZMA_OUT_READ - unsigned char *Dictionary; - UInt32 Range; - UInt32 Code; - UInt32 DictionaryPos; - UInt32 GlobalPos; - UInt32 DistanceLimit; - UInt32 Reps[4]; - int State; - int RemainLen; - unsigned char TempDictionary[4]; - #endif -} CLzmaDecoderState; - -#ifdef _LZMA_OUT_READ -#define LzmaDecoderInit(vs) { (vs)->RemainLen = kLzmaNeedInitId; } -#endif - -int LzmaDecode(CLzmaDecoderState *vs, - #ifdef _LZMA_IN_CB - ILzmaInCallback *inCallback, - #else - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - #endif - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed); - -#endif diff --git a/package/uboot-ifxmips/files/include/LzmaTypes.h b/package/uboot-ifxmips/files/include/LzmaTypes.h deleted file mode 100644 index 288c5e4..0000000 --- a/package/uboot-ifxmips/files/include/LzmaTypes.h +++ /dev/null @@ -1,45 +0,0 @@ -/* -LzmaTypes.h - -Types for LZMA Decoder - -This file written and distributed to public domain by Igor Pavlov. -This file is part of LZMA SDK 4.40 (2006-05-01) -*/ - -#ifndef __LZMATYPES_H -#define __LZMATYPES_H - -#ifndef _7ZIP_BYTE_DEFINED -#define _7ZIP_BYTE_DEFINED -typedef unsigned char Byte; -#endif - -#ifndef _7ZIP_UINT16_DEFINED -#define _7ZIP_UINT16_DEFINED -typedef unsigned short UInt16; -#endif - -#ifndef _7ZIP_UINT32_DEFINED -#define _7ZIP_UINT32_DEFINED -#ifdef _LZMA_UINT32_IS_ULONG -typedef unsigned long UInt32; -#else -typedef unsigned int UInt32; -#endif -#endif - -/* #define _LZMA_SYSTEM_SIZE_T */ -/* Use system's size_t. You can use it to enable 64-bit sizes supporting */ - -#ifndef _7ZIP_SIZET_DEFINED -#define _7ZIP_SIZET_DEFINED -#ifdef _LZMA_SYSTEM_SIZE_T -#include <stddef.h> -typedef size_t SizeT; -#else -typedef UInt32 SizeT; -#endif -#endif - -#endif diff --git a/package/uboot-ifxmips/files/include/LzmaWrapper.h b/package/uboot-ifxmips/files/include/LzmaWrapper.h deleted file mode 100644 index 2f9a3ff..0000000 --- a/package/uboot-ifxmips/files/include/LzmaWrapper.h +++ /dev/null @@ -1,36 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : LzmaWrapper.h -** PROJECT : bootloader -** MODULES : U-boot -** -** DATE : 2 Nov 2006 -** AUTHOR : Lin Mars -** DESCRIPTION : LZMA decoder support for U-boot 1.1.5 -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from -** LZMA v4.43 SDK -*******************************************************************************/ -#ifndef __LZMA_WRAPPER_H__ -#define __LZMA_WRAPPER_H__ - -#ifndef LZMA_RESULT_OK -#define LZMA_RESULT_OK 0 -#endif -#ifndef LZMA_RESULT_DATA_ERROR -#define LZMA_RESULT_DATA_ERROR 1 -#endif - -extern int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len); - -#endif /*__LZMA_WRAPPER_H__*/ diff --git a/package/uboot-ifxmips/files/include/asm-mips/danube.h b/package/uboot-ifxmips/files/include/asm-mips/danube.h deleted file mode 100644 index c0be9fb..0000000 --- a/package/uboot-ifxmips/files/include/asm-mips/danube.h +++ /dev/null @@ -1,2033 +0,0 @@ -#ifndef DANUBE_H -#define DANUBE_H -/****************************************************************************** - Copyright (c) 2002, Infineon Technologies. All rights reserved. - - No Warranty - Because the program is licensed free of charge, there is no warranty for - the program, to the extent permitted by applicable law. Except when - otherwise stated in writing the copyright holders and/or other parties - provide the program "as is" without warranty of any kind, either - expressed or implied, including, but not limited to, the implied - warranties of merchantability and fitness for a particular purpose. The - entire risk as to the quality and performance of the program is with - you. should the program prove defective, you assume the cost of all - necessary servicing, repair or correction. - - In no event unless required by applicable law or agreed to in writing - will any copyright holder, or any other party who may modify and/or - redistribute the program as permitted above, be liable to you for - damages, including any general, special, incidental or consequential - damages arising out of the use or inability to use the program - (including but not limited to loss of data or data being rendered - inaccurate or losses sustained by you or third parties or a failure of - the program to operate with any other programs), even if such holder or - other party has been advised of the possibility of such damages. -******************************************************************************/ - -/***********************************************************************/ -/* Module : MEI register address and bits */ -/***********************************************************************/ -#define MEI_SPACE_ACCESS 0xB0100C00 -#define MEI_DATA_XFR (0x0000 + MEI_SPACE_ACCESS) -#define MEI_VERSION (0x0200 + MEI_SPACE_ACCESS) -#define ARC_GP_STAT (0x0204 + MEI_SPACE_ACCESS) -#define MEI_XFR_ADDR (0x020C + MEI_SPACE_ACCESS) -#define MEI_TO_ARC_INT (0x021C + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT (0x0220 + MEI_SPACE_ACCESS) -#define ARC_TO_MEI_INT_MASK (0x0224 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_WAD (0x0228 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_RAD (0x022C + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DATA (0x0230 + MEI_SPACE_ACCESS) -#define MEI_DEBUG_DEC (0x0234 + MEI_SPACE_ACCESS) -#define MEI_CONTROL (0x0238 + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC0 (0x023C + MEI_SPACE_ACCESS) -#define AT_CELLRDY_BC1 (0x0240 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC0 (0x0244 + MEI_SPACE_ACCESS) -#define AR_CELLRDY_BC1 (0x0248 + MEI_SPACE_ACCESS) -#define AAI_ACCESS (0x024C + MEI_SPACE_ACCESS) -#define AAITXCB0 (0x0300 + MEI_SPACE_ACCESS) -#define AAITXCB1 (0x0304 + MEI_SPACE_ACCESS) -#define AAIRXCB0 (0x0308 + MEI_SPACE_ACCESS) -#define AAIRXCB1 (0x030C + MEI_SPACE_ACCESS) - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ -#define DANUBE_BIU_WDT_BASE (0xBf8803F0) -#define DANUBE_BIU_WDT_CR (0x0000 + DANUBE_BIU_WDT_BASE) -#define DANUBE_BIU_WDT_SR (0x0008 + DANUBE_BIU_WDT_BASE) - - -/***********************************************************************/ -/* Module : PMU register address and bits */ -/***********************************************************************/ -#define DANUBE_PMU_BASE_ADDR (KSEG1+0x1F102000) - -/***PM Control Register***/ -#define DANUBE_PMU_CR ((volatile u32*)(0x001C + DANUBE_PMU_BASE_ADDR)) -#define DANUBE_PMU_PWDCR DANUBE_PMU_CR -#define DANUBE_PMU_SR ((volatile u32*)(0x0020 + DANUBE_PMU_BASE_ADDR)) - -#define DANUBE_PMU_DMA_SHIFT 5 -#define DANUBE_PMU_PPE_SHIFT 13 -#define DANUBE_PMU_ETOP_SHIFT 22 -#define DANUBE_PMU_ENET0_SHIFT 24 -#define DANUBE_PMU_ENET1_SHIFT 25 - - -#define DANUBE_PMU DANUBE_PMU_BASE_ADDR -/***PM Global Enable Register***/ -#define DANUBE_PMU_PM_GEN ((volatile u32*)(DANUBE_PMU+ 0x0000)) -#define DANUBE_PMU_PM_GEN_EN16 (1 << 16) -#define DANUBE_PMU_PM_GEN_EN15 (1 << 15) -#define DANUBE_PMU_PM_GEN_EN14 (1 << 14) -#define DANUBE_PMU_PM_GEN_EN13 (1 << 13) -#define DANUBE_PMU_PM_GEN_EN12 (1 << 12) -#define DANUBE_PMU_PM_GEN_EN11 (1 << 11) -#define DANUBE_PMU_PM_GEN_EN10 (1 << 10) -#define DANUBE_PMU_PM_GEN_EN9 (1 << 9) -#define DANUBE_PMU_PM_GEN_EN8 (1 << 8) -#define DANUBE_PMU_PM_GEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_GEN_EN6 (1 << 6) -#define DANUBE_PMU_PM_GEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_GEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_GEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_GEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_GEN_EN0 (1 << 0) - -/***PM Power Down Enable Register***/ -#define DANUBE_PMU_PM_PDEN ((volatile u32*)(DANUBE_PMU+ 0x0008)) -#define DANUBE_PMU_PM_PDEN_EN16 (1 << 16) -#define DANUBE_PMU_PM_PDEN_EN15 (1 << 15) -#define DANUBE_PMU_PM_PDEN_EN14 (1 << 14) -#define DANUBE_PMU_PM_PDEN_EN13 (1 << 13) -#define DANUBE_PMU_PM_PDEN_EN12 (1 << 12) -#define DANUBE_PMU_PM_PDEN_EN11 (1 << 11) -#define DANUBE_PMU_PM_PDEN_EN10 (1 << 10) -#define DANUBE_PMU_PM_PDEN_EN9 (1 << 9) -#define DANUBE_PMU_PM_PDEN_EN8 (1 << 8) -#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010)) -#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16) -#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15) -#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14) -#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13) -#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12) -#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11) -#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10) -#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9) -#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8) -#define DANUBE_PMU_PM_PDEN_EN7 (1 << 7) -#define DANUBE_PMU_PM_PDEN_EN5 (1 << 5) -#define DANUBE_PMU_PM_PDEN_EN4 (1 << 4) -#define DANUBE_PMU_PM_PDEN_EN3 (1 << 3) -#define DANUBE_PMU_PM_PDEN_EN2 (1 << 2) -#define DANUBE_PMU_PM_PDEN_EN0 (1 << 0) - -/***PM Wake-Up from Power Down Register***/ -#define DANUBE_PMU_PM_WUP ((volatile u32*)(DANUBE_PMU+ 0x0010)) -#define DANUBE_PMU_PM_WUP_WUP16 (1 << 16) -#define DANUBE_PMU_PM_WUP_WUP15 (1 << 15) -#define DANUBE_PMU_PM_WUP_WUP14 (1 << 14) -#define DANUBE_PMU_PM_WUP_WUP13 (1 << 13) -#define DANUBE_PMU_PM_WUP_WUP12 (1 << 12) -#define DANUBE_PMU_PM_WUP_WUP11 (1 << 11) -#define DANUBE_PMU_PM_WUP_WUP10 (1 << 10) -#define DANUBE_PMU_PM_WUP_WUP9 (1 << 9) -#define DANUBE_PMU_PM_WUP_WUP8 (1 << 8) -#define DANUBE_PMU_PM_WUP_WUP7 (1 << 7) -#define DANUBE_PMU_PM_WUP_WUP5 (1 << 5) -#define DANUBE_PMU_PM_WUP_WUP4 (1 << 4) -#define DANUBE_PMU_PM_WUP_WUP3 (1 << 3) -#define DANUBE_PMU_PM_WUP_WUP2 (1 << 2) -#define DANUBE_PMU_PM_WUP_WUP0 (1 << 0) - -/***PM Control Register***/ -#define DANUBE_PMU_PM_CR ((volatile u32*)(DANUBE_PMU+ 0x0014)) -#define DANUBE_PMU_PM_CR_AWEN (1 << 31) -#define DANUBE_PMU_PM_CR_SWRST (1 << 30) -#define DANUBE_PMU_PM_CR_SWCR (1 << 2) -#define DANUBE_PMU_PM_CR_CRD (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ -#define DANUBE_RCU_BASE_ADDR (0xBF203000) - -#define DANUBE_RCU_REQ (0x0010 + DANUBE_RCU_BASE_ADDR) -#define DANUBE_RCU_RST_REQ ((volatile u32*)(DANUBE_RCU_REQ)) -#define DANUBE_RCU_STAT (0x0014 + DANUBE_RCU_BASE_ADDR) -#define DANUBE_RCU_RST_SR ( (volatile u32 *)(DANUBE_RCU_STAT)) -#define DANUBE_RCU_PCI_RDY ( (volatile u32 *)(DANUBE_RCU_BASE_ADDR+0x28)) -#define DANUBE_RCU_MON (0x0030 + DANUBE_RCU_BASE_ADDR) - - -/***********************************************************************/ -/* Module : BCU register address and bits */ -/***********************************************************************/ -#define DANUBE_BCU_BASE_ADDR (0xB0100000) -/***BCU Control Register (0010H)***/ -#define DANUBE_BCU_CON (0x0010 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_BCU_CON_SPC (value) (((( 1 << 8) - 1) & (value)) << 24) -#define DANUBE_BCU_BCU_CON_SPE (1 << 19) -#define DANUBE_BCU_BCU_CON_PSE (1 << 18) -#define DANUBE_BCU_BCU_CON_DBG (1 << 16) -#define DANUBE_BCU_BCU_CON_TOUT (value) (((( 1 << 16) - 1) & (value)) << 0) - - -/***BCU Error Control Capture Register (0020H)***/ -#define DANUBE_BCU_ECON (0x0020 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_BCU_ECON_TAG (value) (((( 1 << 4) - 1) & (value)) << 24) -#define DANUBE_BCU_BCU_ECON_RDN (1 << 23) -#define DANUBE_BCU_BCU_ECON_WRN (1 << 22) -#define DANUBE_BCU_BCU_ECON_SVM (1 << 21) -#define DANUBE_BCU_BCU_ECON_ACK (value) (((( 1 << 2) - 1) & (value)) << 19) -#define DANUBE_BCU_BCU_ECON_ABT (1 << 18) -#define DANUBE_BCU_BCU_ECON_RDY (1 << 17) -#define DANUBE_BCU_BCU_ECON_TOUT (1 << 16) -#define DANUBE_BCU_BCU_ECON_ERRCNT (value) (((( 1 << 16) - 1) & (value)) << 0) -#define DANUBE_BCU_BCU_ECON_OPC (value) (((( 1 << 4) - 1) & (value)) << 28) - -/***BCU Error Address Capture Register (0024 H)***/ -#define DANUBE_BCU_EADD (0x0024 + DANUBE_BCU_BASE_ADDR) - -/***BCU Error Data Capture Register (0028H)***/ -#define DANUBE_BCU_EDAT (0x0028 + DANUBE_BCU_BASE_ADDR) - -#define DANUBE_BCU_IRNEN (0x00F4 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_IRNICR (0x00F8 + DANUBE_BCU_BASE_ADDR) -#define DANUBE_BCU_IRNCR (0x00FC + DANUBE_BCU_BASE_ADDR) - - -/***********************************************************************/ -/* Module : MBC register address and bits */ -/***********************************************************************/ - -#define DANUBE_MBC (0xBF103000) -/***********************************************************************/ - - -/***Mailbox CPU Configuration Register***/ -#define DANUBE_MBC_MBC_CFG ((volatile u32*)(DANUBE_MBC+ 0x0080)) -#define DANUBE_MBC_MBC_CFG_SWAP (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_MBC_MBC_CFG_RES (1 << 5) -#define DANUBE_MBC_MBC_CFG_FWID (value) (((( 1 << 4) - 1) & (value)) << 1) -#define DANUBE_MBC_MBC_CFG_SIZE (1 << 0) - -/***Mailbox CPU Interrupt Status Register***/ -#define DANUBE_MBC_MBC_ISR ((volatile u32*)(DANUBE_MBC+ 0x0084)) -#define DANUBE_MBC_MBC_ISR_B3DA (1 << 31) -#define DANUBE_MBC_MBC_ISR_B2DA (1 << 30) -#define DANUBE_MBC_MBC_ISR_B1E (1 << 29) -#define DANUBE_MBC_MBC_ISR_B0E (1 << 28) -#define DANUBE_MBC_MBC_ISR_WDT (1 << 27) -#define DANUBE_MBC_MBC_ISR_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask Register***/ -#define DANUBE_MBC_MBC_MSK ((volatile u32*)(DANUBE_MBC+ 0x0088)) -#define DANUBE_MBC_MBC_MSK_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 01 Register***/ -#define DANUBE_MBC_MBC_MSK01 ((volatile u32*)(DANUBE_MBC+ 0x008C)) -#define DANUBE_MBC_MBC_MSK01_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK01_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK01_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK01_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK01_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK01_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Mask 10 Register***/ -#define DANUBE_MBC_MBC_MSK10 ((volatile u32*)(DANUBE_MBC+ 0x0090)) -#define DANUBE_MBC_MBC_MSK10_B3DA (1 << 31) -#define DANUBE_MBC_MBC_MSK10_B2DA (1 << 30) -#define DANUBE_MBC_MBC_MSK10_B1E (1 << 29) -#define DANUBE_MBC_MBC_MSK10_B0E (1 << 28) -#define DANUBE_MBC_MBC_MSK10_WDT (1 << 27) -#define DANUBE_MBC_MBC_MSK10_DS260 (value) (((( 1 << 27) - 1) & (value)) << 0) - -/***Mailbox CPU Short Command Register***/ -#define DANUBE_MBC_MBC_CMD ((volatile u32*)(DANUBE_MBC+ 0x0094)) -#define DANUBE_MBC_MBC_CMD_CS270 (value) (((( 1 << 28) - 1) & (value)) << 0) - -/***Mailbox CPU Input Data of Buffer 0***/ -#define DANUBE_MBC_MBC_ID0 ((volatile u32*)(DANUBE_MBC+ 0x0000)) -#define DANUBE_MBC_MBC_ID0_INDATA - -/***Mailbox CPU Input Data of Buffer 1***/ -#define DANUBE_MBC_MBC_ID1 ((volatile u32*)(DANUBE_MBC+ 0x0020)) -#define DANUBE_MBC_MBC_ID1_INDATA - -/***Mailbox CPU Output Data of Buffer 2***/ -#define DANUBE_MBC_MBC_OD2 ((volatile u32*)(DANUBE_MBC+ 0x0040)) -#define DANUBE_MBC_MBC_OD2_OUTDATA - -/***Mailbox CPU Output Data of Buffer 3***/ -#define DANUBE_MBC_MBC_OD3 ((volatile u32*)(DANUBE_MBC+ 0x0060)) -#define DANUBE_MBC_MBC_OD3_OUTDATA - -/***Mailbox CPU Control Register of Buffer 0***/ -#define DANUBE_MBC_MBC_CR0 ((volatile u32*)(DANUBE_MBC+ 0x0004)) -#define DANUBE_MBC_MBC_CR0_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 1***/ -#define DANUBE_MBC_MBC_CR1 ((volatile u32*)(DANUBE_MBC+ 0x0024)) -#define DANUBE_MBC_MBC_CR1_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 2***/ -#define DANUBE_MBC_MBC_CR2 ((volatile u32*)(DANUBE_MBC+ 0x0044)) -#define DANUBE_MBC_MBC_CR2_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Control Register of Buffer 3***/ -#define DANUBE_MBC_MBC_CR3 ((volatile u32*)(DANUBE_MBC+ 0x0064)) -#define DANUBE_MBC_MBC_CR3_RDYABTFLS (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***Mailbox CPU Free Space of Buffer 0***/ -#define DANUBE_MBC_MBC_FS0 ((volatile u32*)(DANUBE_MBC+ 0x0008)) -#define DANUBE_MBC_MBC_FS0_FS - -/***Mailbox CPU Free Space of Buffer 1***/ -#define DANUBE_MBC_MBC_FS1 ((volatile u32*)(DANUBE_MBC+ 0x0028)) -#define DANUBE_MBC_MBC_FS1_FS - -/***Mailbox CPU Free Space of Buffer 2***/ -#define DANUBE_MBC_MBC_FS2 ((volatile u32*)(DANUBE_MBC+ 0x0048)) -#define DANUBE_MBC_MBC_FS2_FS - -/***Mailbox CPU Free Space of Buffer 3***/ -#define DANUBE_MBC_MBC_FS3 ((volatile u32*)(DANUBE_MBC+ 0x0068)) -#define DANUBE_MBC_MBC_FS3_FS - -/***Mailbox CPU Data Available in Buffer 0***/ -#define DANUBE_MBC_MBC_DA0 ((volatile u32*)(DANUBE_MBC+ 0x000C)) -#define DANUBE_MBC_MBC_DA0_DA - -/***Mailbox CPU Data Available in Buffer 1***/ -#define DANUBE_MBC_MBC_DA1 ((volatile u32*)(DANUBE_MBC+ 0x002C)) -#define DANUBE_MBC_MBC_DA1_DA - -/***Mailbox CPU Data Available in Buffer 2***/ -#define DANUBE_MBC_MBC_DA2 ((volatile u32*)(DANUBE_MBC+ 0x004C)) -#define DANUBE_MBC_MBC_DA2_DA - -/***Mailbox CPU Data Available in Buffer 3***/ -#define DANUBE_MBC_MBC_DA3 ((volatile u32*)(DANUBE_MBC+ 0x006C)) -#define DANUBE_MBC_MBC_DA3_DA - -/***Mailbox CPU Input Absolute Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_IABS0 ((volatile u32*)(DANUBE_MBC+ 0x0010)) -#define DANUBE_MBC_MBC_IABS0_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_IABS1 ((volatile u32*)(DANUBE_MBC+ 0x0030)) -#define DANUBE_MBC_MBC_IABS1_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_IABS2 ((volatile u32*)(DANUBE_MBC+ 0x0050)) -#define DANUBE_MBC_MBC_IABS2_IABS - -/***Mailbox CPU Input Absolute Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_IABS3 ((volatile u32*)(DANUBE_MBC+ 0x0070)) -#define DANUBE_MBC_MBC_IABS3_IABS - -/***Mailbox CPU Input Temporary Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_ITMP0 ((volatile u32*)(DANUBE_MBC+ 0x0014)) -#define DANUBE_MBC_MBC_ITMP0_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_ITMP1 ((volatile u32*)(DANUBE_MBC+ 0x0034)) -#define DANUBE_MBC_MBC_ITMP1_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_ITMP2 ((volatile u32*)(DANUBE_MBC+ 0x0054)) -#define DANUBE_MBC_MBC_ITMP2_ITMP - -/***Mailbox CPU Input Temporary Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_ITMP3 ((volatile u32*)(DANUBE_MBC+ 0x0074)) -#define DANUBE_MBC_MBC_ITMP3_ITMP - -/***Mailbox CPU Output Absolute Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_OABS0 ((volatile u32*)(DANUBE_MBC+ 0x0018)) -#define DANUBE_MBC_MBC_OABS0_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_OABS1 ((volatile u32*)(DANUBE_MBC+ 0x0038)) -#define DANUBE_MBC_MBC_OABS1_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_OABS2 ((volatile u32*)(DANUBE_MBC+ 0x0058)) -#define DANUBE_MBC_MBC_OABS2_OABS - -/***Mailbox CPU Output Absolute Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_OABS3 ((volatile u32*)(DANUBE_MBC+ 0x0078)) -#define DANUBE_MBC_MBC_OABS3_OABS - -/***Mailbox CPU Output Temporary Pointer of Buffer 0***/ -#define DANUBE_MBC_MBC_OTMP0 ((volatile u32*)(DANUBE_MBC+ 0x001C)) -#define DANUBE_MBC_MBC_OTMP0_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 1***/ -#define DANUBE_MBC_MBC_OTMP1 ((volatile u32*)(DANUBE_MBC+ 0x003C)) -#define DANUBE_MBC_MBC_OTMP1_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 2***/ -#define DANUBE_MBC_MBC_OTMP2 ((volatile u32*)(DANUBE_MBC+ 0x005C)) -#define DANUBE_MBC_MBC_OTMP2_OTMP - -/***Mailbox CPU Output Temporary Pointer of Buffer 3***/ -#define DANUBE_MBC_MBC_OTMP3 ((volatile u32*)(DANUBE_MBC+ 0x007C)) -#define DANUBE_MBC_MBC_OTMP3_OTMP - -/***DSP Control Register***/ -#define DANUBE_MBC_DCTRL ((volatile u32*)(DANUBE_MBC+ 0x00A0)) -#define DANUBE_MBC_DCTRL_BA (1 << 0) -#define DANUBE_MBC_DCTRL_BMOD (value) (((( 1 << 3) - 1) & (value)) << 1) -#define DANUBE_MBC_DCTRL_IDL (1 << 4) -#define DANUBE_MBC_DCTRL_RES (1 << 15) - -/***DSP Status Register***/ -#define DANUBE_MBC_DSTA ((volatile u32*)(DANUBE_MBC+ 0x00A4)) -#define DANUBE_MBC_DSTA_IDLE (1 << 0) -#define DANUBE_MBC_DSTA_PD (1 << 1) - -/***DSP Test 1 Register***/ -#define DANUBE_MBC_DTST1 ((volatile u32*)(DANUBE_MBC+ 0x00A8)) -#define DANUBE_MBC_DTST1_ABORT (1 << 0) -#define DANUBE_MBC_DTST1_HWF32 (1 << 1) -#define DANUBE_MBC_DTST1_HWF4M (1 << 2) -#define DANUBE_MBC_DTST1_HWFOP (1 << 3) - - -/***********************************************************************/ -/* Module : SSC1 register address and bits */ -/***********************************************************************/ -#define DANUBE_SSC1 (KSEG1+0x1e100800) -/***********************************************************************/ -/***SSC Clock Control Register***/ -#define DANUBE_SSC_CLC (0x0000) -#define DANUBE_SSC_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_SSC_CLC_DISS (1 << 1) -#define DANUBE_SSC_CLC_DISR (1 << 0) -/***SSC Port Input Selection Register***/ -#define DANUBE_SSC_PISEL (0x0004) -/***SSC Identification Register***/ -#define DANUBE_SSC_ID (0x0008) -/***Control Register (Programming Mode)***/ -#define DANUBE_SSC_CON (0x0010) -#define DANUBE_SSC_CON_RUEN (1 << 12) -#define DANUBE_SSC_CON_TUEN (1 << 11) -#define DANUBE_SSC_CON_AEN (1 << 10) -#define DANUBE_SSC_CON_REN (1 << 9) -#define DANUBE_SSC_CON_TEN (1 << 8) -#define DANUBE_SSC_CON_LB (1 << 7) -#define DANUBE_SSC_CON_PO (1 << 6) -#define DANUBE_SSC_CON_PH (1 << 5) -#define DANUBE_SSC_CON_HB (1 << 4) -#define DANUBE_SSC_CON_BM(value) (((( 1 << 5) - 1) & (value)) << 16) -#define DANUBE_SSC_CON_RX_OFF (1 << 1) -#define DANUBE_SSC_CON_TX_OFF (1 << 0) -/***SCC Status Register***/ -#define DANUBE_SSC_STATE (0x0014) -#define DANUBE_SSC_STATE_EN (1 << 0) -#define DANUBE_SSC_STATE_MS (1 << 1) -#define DANUBE_SSC_STATE_BSY (1 << 13) -#define DANUBE_SSC_STATE_RUE (1 << 12) -#define DANUBE_SSC_STATE_TUE (1 << 11) -#define DANUBE_SSC_STATE_AE (1 << 10) -#define DANUBE_SSC_STATE_RE (1 << 9) -#define DANUBE_SSC_STATE_TE (1 << 8) -#define DANUBE_SSC_STATE_BC(value) (((( 1 << 5) - 1) & (value)) << 16) -/***SSC Write Hardware Modified Control Register***/ -#define DANUBE_SSC_WHBSTATE ( 0x0018) -#define DANUBE_SSC_WHBSTATE_SETBE (1 << 15) -#define DANUBE_SSC_WHBSTATE_SETPE (1 << 14) -#define DANUBE_SSC_WHBSTATE_SETRE (1 << 13) -#define DANUBE_SSC_WHBSTATE_SETTE (1 << 12) -#define DANUBE_SSC_WHBSTATE_CLRBE (1 << 11) -#define DANUBE_SSC_WHBSTATE_CLRPE (1 << 10) -#define DANUBE_SSC_WHBSTATE_CLRRE (1 << 9) -#define DANUBE_SSC_WHBSTATE_CLRTE (1 << 8) -/***SSC Transmitter Buffer Register***/ -#define DANUBE_SSC_TB (0x0020) -#define DANUBE_SSC_TB_TB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -/***SSC Receiver Buffer Register***/ -#define DANUBE_SSC_RB (0x0024) -#define DANUBE_SSC_RB_RB_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -/***SSC Receive FIFO Control Register***/ -#define DANUBE_SSC_RXFCON (0x0030) -#define DANUBE_SSC_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_RXFCON_RXTMEN (1 << 2) -#define DANUBE_SSC_RXFCON_RXFLU (1 << 1) -#define DANUBE_SSC_RXFCON_RXFEN (1 << 0) -/***SSC Transmit FIFO Control Register***/ -#define DANUBE_SSC_TXFCON ( 0x0034) -#define DANUBE_SSC_TXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_TXFCON_TXTMEN (1 << 2) -#define DANUBE_SSC_TXFCON_TXFLU (1 << 1) -#define DANUBE_SSC_TXFCON_TXFEN (1 << 0) -/***SSC FIFO Status Register***/ -#define DANUBE_SSC_FSTAT (0x0038) -#define DANUBE_SSC_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_SSC_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -/***SSC Baudrate Timer Reload Register***/ -#define DANUBE_SSC_BR (0x0040) -#define DANUBE_SSC_BR_BR_VALUE(value) (((( 1 << 16) - 1) & (value)) << 0) -#define DANUBE_SSC_BRSTAT (0x0044) -#define DANUBE_SSC_SFCON (0x0060) -#define DANUBE_SSC_SFSTAT (0x0064) -#define DANUBE_SSC_GPOCON (0x0070) -#define DANUBE_SSC_GPOSTAT (0x0074) -#define DANUBE_SSC_WHBGPOSTAT (0x0078) -#define DANUBE_SSC_RXREQ (0x0080) -#define DANUBE_SSC_RXCNT (0x0084) -/*DMA Registers in Bus Clock Domain*/ -#define DANUBE_SSC_DMA_CON (0x00EC) -/*interrupt Node Registers in Bus Clock Domain*/ -#define DANUBE_SSC_IRNEN (0x00F4) -#define DANUBE_SSC_IRNCR (0x00F8) -#define DANUBE_SSC_IRNICR (0x00FC) -#define DANUBE_SSC_IRN_FIR 0x8 -#define DANUBE_SSC_IRN_EIR 0x4 -#define DANUBE_SSC_IRN_RIR 0x2 -#define DANUBE_SSC_IRN_TIR 0x1 - - -#define DANUBE_SSC1_CLC ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CLC)) -#define DANUBE_SSC1_ID ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_ID)) -#define DANUBE_SSC1_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_CON)) -#define DANUBE_SSC1_STATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_STATE)) -#define DANUBE_SSC1_WHBSTATE ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBSTATE)) -#define DANUBE_SSC1_TB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TB)) -#define DANUBE_SSC1_RB ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RB)) -#define DANUBE_SSC1_FSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_FSTAT)) -#define DANUBE_SSC1_PISEL ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_PISEL)) -#define DANUBE_SSC1_RXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXFCON)) -#define DANUBE_SSC1_TXFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_TXFCON)) -#define DANUBE_SSC1_BR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BR)) -#define DANUBE_SSC1_BRSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_BRSTAT)) -#define DANUBE_SSC1_SFCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFCON)) -#define DANUBE_SSC1_SFSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_SFSTAT)) -#define DANUBE_SSC1_GPOCON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOCON)) -#define DANUBE_SSC1_GPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_GPOSTAT)) -#define DANUBE_SSC1_WHBGPOSTAT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_WHBGPOSTAT)) -#define DANUBE_SSC1_RXREQ ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXREQ)) -#define DANUBE_SSC1_RXCNT ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_RXCNT)) -#define DANUBE_SSC1_DMA_CON ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_DMA_CON)) -#define DANUBE_SSC1_IRNEN ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNEN)) -#define DANUBE_SSC1_IRNICR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNICR)) -#define DANUBE_SSC1_IRNCR ((volatile u32*)(DANUBE_SSC1+DANUBE_SSC_IRNCR)) - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ -#define DANUBE_GPIO (0xBE100B00) -/***Port 0 Data Output Register (0010H)***/ -#define DANUBE_GPIO_P0_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0010)) -/***Port 1 Data Output Register (0040H)***/ -#define DANUBE_GPIO_P1_OUT ((volatile u32 *)(DANUBE_GPIO+ 0x0040)) -/***Port 0 Data Input Register (0014H)***/ -#define DANUBE_GPIO_P0_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0014)) -/***Port 1 Data Input Register (0044H)***/ -#define DANUBE_GPIO_P1_IN ((volatile u32 *)(DANUBE_GPIO+ 0x0044)) -/***Port 0 Direction Register (0018H)***/ -#define DANUBE_GPIO_P0_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0018)) -/***Port 1 Direction Register (0048H)***/ -#define DANUBE_GPIO_P1_DIR ((volatile u32 *)(DANUBE_GPIO+ 0x0048)) -/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -#define DANUBE_GPIO_P0_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x001C)) -/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -#define DANUBE_GPIO_P1_ALTSEL0 ((volatile u32 *)(DANUBE_GPIO+ 0x004C)) -/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -#define DANUBE_GPIO_P0_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0020)) -/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -#define DANUBE_GPIO_P1_ALTSEL1 ((volatile u32 *)(DANUBE_GPIO+ 0x0050)) -/***Port 0 Open Drain Control Register (0024H)***/ -#define DANUBE_GPIO_P0_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0024)) -/***Port 1 Open Drain Control Register (0054H)***/ -#define DANUBE_GPIO_P1_OD ((volatile u32 *)(DANUBE_GPIO+ 0x0054)) -/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -#define DANUBE_GPIO_P0_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0028)) -/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -#define DANUBE_GPIO_P1_STOFF ((volatile u32 *)(DANUBE_GPIO+ 0x0058)) -/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -#define DANUBE_GPIO_P0_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x002C)) -/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -#define DANUBE_GPIO_P1_PUDSEL ((volatile u32 *)(DANUBE_GPIO+ 0x005C)) -/***Port 0 Pull Up Device Enable Register (0030 H)***/ -#define DANUBE_GPIO_P0_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0030)) -/***Port 1 Pull Up Device Enable Register (0060 H)***/ -#define DANUBE_GPIO_P1_PUDEN ((volatile u32 *)(DANUBE_GPIO+ 0x0060)) -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define DANUBE_CGU (0xBF103000) -/***********************************************************************/ - -/***CGU Clock PLL0 ***/ -#define DANUBE_CGU_PLL0_CFG ((volatile u32*)(DANUBE_CGU+ 0x0004)) -/***CGU Clock PLL1 ***/ -#define DANUBE_CGU_PLL1_CFG ((volatile u32*)(DANUBE_CGU+ 0x0008)) -/***CGU Clock SYS Mux Register***/ -#define DANUBE_CGU_SYS ((volatile u32*)(DANUBE_CGU+ 0x0010)) -/***CGU Interface Clock Control Register***/ -#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018)) -/***CGU PCI Clock Control Register**/ -#define DANUBE_CGU_PCICR ((volatile u32*)(DANUBE_CGU+ 0x0034)) - - -/***********************************************************************/ -/* Module : PCI register address and bits */ -/***********************************************************************/ -#define PCI_CR_PR_OFFSET 0xBE105400 -#define PCI_CR_CLK_CTRL_REG (PCI_CR_PR_OFFSET + 0x0000) - -#define PCI_CR_PCI_ID_REG (PCI_CR_PR_OFFSET + 0x0004) -#define PCI_CR_SFT_RST_REG (PCI_CR_PR_OFFSET + 0x0010) -#define PCI_CR_PCI_FPI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0014) -#define PCI_CR_FCI_PCI_ERR_ADDR_REG (PCI_CR_PR_OFFSET + 0x0018) -#define PCI_CR_FPI_ERR_TAG_REG (PCI_CR_PR_OFFSET + 0x001C) -#define PCI_CR_PCI_IRR_REG (PCI_CR_PR_OFFSET + 0x0020) -#define PCI_CR_PCI_IRA_REG (PCI_CR_PR_OFFSET + 0x0024) -#define PCI_CR_PCI_IRM_REG (PCI_CR_PR_OFFSET + 0x0028) -#define PCI_CR_PCI_EOI_REG (PCI_CR_PR_OFFSET + 0x002C) -#define PCI_CR_PCI_MOD_REG (PCI_CR_PR_OFFSET + 0x0030) -#define PCI_CR_DV_ID_REG (PCI_CR_PR_OFFSET + 0x0034) -#define PCI_CR_SUBSYS_ID_REG (PCI_CR_PR_OFFSET + 0x0038) -#define PCI_CR_PCI_PM_REG (PCI_CR_PR_OFFSET + 0x003C) -#define PCI_CR_CLASS_CODE1_REG (PCI_CR_PR_OFFSET + 0x0040) -#define PCI_CR_BAR11MASK_REG (PCI_CR_PR_OFFSET + 0x0044) -#define PCI_CR_BAR12MASK_REG (PCI_CR_PR_OFFSET + 0x0048) -#define PCI_CR_BAR13MASK_REG (PCI_CR_PR_OFFSET + 0x004C) -#define PCI_CR_BAR14MASK_REG (PCI_CR_PR_OFFSET + 0x0050) -#define PCI_CR_BAR15MASK_REG (PCI_CR_PR_OFFSET + 0x0054) -#define PCI_CR_BAR16MASK_REG (PCI_CR_PR_OFFSET + 0x0058) -#define PCI_CR_CIS_PT1_REG (PCI_CR_PR_OFFSET + 0x005C) -#define PCI_CR_SUBSYS_ID1_REG (PCI_CR_PR_OFFSET + 0x0060) -#define PCI_CR_PCI_ADDR_MAP11_REG (PCI_CR_PR_OFFSET + 0x0064) -#define PCI_CR_PCI_ADDR_MAP12_REG (PCI_CR_PR_OFFSET + 0x0068) -#define PCI_CR_PCI_ADDR_MAP13_REG (PCI_CR_PR_OFFSET + 0x006C) -#define PCI_CR_PCI_ADDR_MAP14_REG (PCI_CR_PR_OFFSET + 0x0070) -#define PCI_CR_PCI_ADDR_MAP15_REG (PCI_CR_PR_OFFSET + 0x0074) -#define PCI_CR_PCI_ADDR_MAP16_REG (PCI_CR_PR_OFFSET + 0x0078) -#define PCI_CR_FPI_SEG_EN_REG (PCI_CR_PR_OFFSET + 0x007C) -#define PCI_CR_PC_ARB_REG (PCI_CR_PR_OFFSET + 0x0080) -#define PCI_CR_BAR21MASK_REG (PCI_CR_PR_OFFSET + 0x0084) -#define PCI_CR_BAR22MASK_REG (PCI_CR_PR_OFFSET + 0x0088) -#define PCI_CR_BAR23MASK_REG (PCI_CR_PR_OFFSET + 0x008C) -#define PCI_CR_BAR24MASK_REG (PCI_CR_PR_OFFSET + 0x0090) -#define PCI_CR_BAR25MASK_REG (PCI_CR_PR_OFFSET + 0x0094) -#define PCI_CR_BAR26MASK_REG (PCI_CR_PR_OFFSET + 0x0098) -#define PCI_CR_CIS_PT2_REG (PCI_CR_PR_OFFSET + 0x009C) -#define PCI_CR_SUBSYS_ID2_REG (PCI_CR_PR_OFFSET + 0x00A0) -#define PCI_CR_PCI_ADDR_MAP21_REG (PCI_CR_PR_OFFSET + 0x00A4) -#define PCI_CR_PCI_ADDR_MAP22_REG (PCI_CR_PR_OFFSET + 0x00A8) -#define PCI_CR_PCI_ADDR_MAP23_REG (PCI_CR_PR_OFFSET + 0x00AC) - - -/***********************************************************************/ -/* Module : MCD register address and bits */ -/***********************************************************************/ -#define DANUBE_MCD (KSEG1+0x1F106000) - -/***Manufacturer Identification Register***/ -#define DANUBE_MCD_MANID ((volatile u32*)(DANUBE_MCD+ 0x0024)) -#define DANUBE_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) - -/***Chip Identification Register***/ -#define DANUBE_MCD_CHIPID ((volatile u32*)(DANUBE_MCD+ 0x0028)) -#define DANUBE_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define DANUBE_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define DANUBE_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define DANUBE_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -#define DANUBE_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) - -#define DANUBE_CHIPID_STANDARD 0x00EB -#define DANUBE_CHIPID_YANGTSE 0x00ED - -/***Redesign Tracing Identification Register***/ -#define DANUBE_MCD_RTID ((volatile u32*)(DANUBE_MCD+ 0x002C)) -#define DANUBE_MCD_RTID_LC (1 << 15) -#define DANUBE_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define DANUBE_EBU (0xBE105300) -#define EBU_ADDR_SEL_0 (volatile u32*)(DANUBE_EBU + 0x20) -#define EBU_ADDR_SEL_1 (volatile u32*)(DANUBE_EBU + 0x24) -#define EBU_CON_0 (volatile u32*)(DANUBE_EBU + 0x60) -#define EBU_CON_1 (volatile u32*)(DANUBE_EBU + 0x64) -#define EBU_NAND_CON (volatile u32*)(DANUBE_EBU + 0xB0) -#define EBU_NAND_WAIT (volatile u32*)(DANUBE_EBU + 0xB4) -#define EBU_NAND_ECC0 (volatile u32*)(DANUBE_EBU + 0xB8) -#define EBU_NAND_ECC_AC (volatile u32*)(DANUBE_EBU + 0xBC) - -/***********************************************************************/ - - -/***EBU Clock Control Register***/ -#define DANUBE_EBU_CLC ((volatile u32*)(DANUBE_EBU+ 0x0000)) -#define DANUBE_EBU_CLC_DISS (1 << 1) -#define DANUBE_EBU_CLC_DISR (1 << 0) - -/***EBU Global Control Register***/ -#define DANUBE_EBU_CON ((volatile u32*)(DANUBE_EBU+ 0x0010)) -#define DANUBE_EBU_CON_DTACS (value) (((( 1 << 3) - 1) & (value)) << 20) -#define DANUBE_EBU_CON_DTARW (value) (((( 1 << 3) - 1) & (value)) << 16) -#define DANUBE_EBU_CON_TOUTC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_EBU_CON_ARBMODE (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_EBU_CON_ARBSYNC (1 << 5) -#define DANUBE_EBU_CON_1 (1 << 3) - -/***EBU Address Select Register 0***/ -#define DANUBE_EBU_ADDSEL0 ((volatile u32*)(DANUBE_EBU+ 0x0020)) -#define DANUBE_EBU_ADDSEL0_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL0_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL0_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL0_REGEN (1 << 0) - -/***EBU Address Select Register 1***/ -#define DANUBE_EBU_ADDSEL1 ((volatile u32*)(DANUBE_EBU+ 0x0024)) -#define DANUBE_EBU_ADDSEL1_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL1_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL1_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL1_REGEN (1 << 0) - -/***EBU Address Select Register 2***/ -#define DANUBE_EBU_ADDSEL2 ((volatile u32*)(DANUBE_EBU+ 0x0028)) -#define DANUBE_EBU_ADDSEL2_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL2_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL2_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL2_REGEN (1 << 0) - -/***EBU Address Select Register 3***/ -#define DANUBE_EBU_ADDSEL3 ((volatile u32*)(DANUBE_EBU+ 0x0028)) -#define DANUBE_EBU_ADDSEL3_BASE (value) (((( 1 << 20) - 1) & (value)) << 12) -#define DANUBE_EBU_ADDSEL3_MASK (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_EBU_ADDSEL3_MIRRORE (1 << 1) -#define DANUBE_EBU_ADDSEL3_REGEN (1 << 0) - -/***EBU Bus Configuration Register 0***/ -#define DANUBE_EBU_BUSCON0 ((volatile u32*)(DANUBE_EBU+ 0x0060)) -#define DANUBE_EBU_BUSCON0_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON0_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON0_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON0_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON0_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON0_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON0_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON0_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON0_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON0_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON0_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON0_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON0_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON0_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 1***/ -#define DANUBE_EBU_BUSCON1 ((volatile u32*)(DANUBE_EBU+ 0x0064)) -#define DANUBE_EBU_BUSCON1_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON1_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON1_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***EBU Bus Configuration Register 2***/ -#define DANUBE_EBU_BUSCON2 ((volatile u32*)(DANUBE_EBU+ 0x0068)) -#define DANUBE_EBU_BUSCON2_WRDIS (1 << 31) -#define DANUBE_EBU_BUSCON2_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -#define DANUBE_EBU_BUSCON2_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -#define DANUBE_EBU_BUSCON2_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -#define DANUBE_EBU_BUSCON2_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -#define DANUBE_EBU_BUSCON2_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -#define DANUBE_EBU_BUSCON2_WAITINV (1 << 19) -#define DANUBE_EBU_BUSCON2_SETUP (1 << 18) -#define DANUBE_EBU_BUSCON2_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -#define DANUBE_EBU_BUSCON2_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -#define DANUBE_EBU_BUSCON2_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -#define DANUBE_EBU_BUSCON2_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_EBU_BUSCON2_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_EBU_BUSCON2_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : SDRAM register address and bits */ -/***********************************************************************/ - -#define DANUBE_SDRAM (0xBF800000) -/***********************************************************************/ - - -/***MC Access Error Cause Register***/ -#define DANUBE_SDRAM_MC_ERRCAUSE ((volatile u32*)(DANUBE_SDRAM+ 0x0100)) -#define DANUBE_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -#define DANUBE_SDRAM_MC_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_ERRCAUSE_Res (value) (((( 1 << NaN) - 1) & (value)) << NaN) - -/***MC Access Error Address Register***/ -#define DANUBE_SDRAM_MC_ERRADDR ((volatile u32*)(DANUBE_SDRAM+ 0x0108)) -#define DANUBE_SDRAM_MC_ERRADDR_ADDR - -/***MC I/O General Purpose Register***/ -#define DANUBE_SDRAM_MC_IOGP ((volatile u32*)(DANUBE_SDRAM+ 0x0800)) -#define DANUBE_SDRAM_MC_IOGP_GPR6 (value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_SDRAM_MC_IOGP_GPR5 (value) (((( 1 << 4) - 1) & (value)) << 24) -#define DANUBE_SDRAM_MC_IOGP_GPR4 (value) (((( 1 << 4) - 1) & (value)) << 20) -#define DANUBE_SDRAM_MC_IOGP_GPR3 (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_IOGP_GPR2 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_IOGP_CPS (1 << 11) -#define DANUBE_SDRAM_MC_IOGP_CLKDELAY (value) (((( 1 << 3) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_IOGP_CLKRAT (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_IOGP_RDDEL (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***MC Self Refresh Register***/ -#define DANUBE_SDRAM_MC_SELFRFSH ((volatile u32*)(DANUBE_SDRAM+ 0x0A00)) -#define DANUBE_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -#define DANUBE_SDRAM_MC_SELFRFSH_PWD (1 << 0) -#define DANUBE_SDRAM_MC_SELFRFSH_Res (value) (((( 1 << 30) - 1) & (value)) << 2) - -/***MC Enable Register***/ -#define DANUBE_SDRAM_MC_CTRLENA ((volatile u32*)(DANUBE_SDRAM+ 0x1000)) -#define DANUBE_SDRAM_MC_CTRLENA_ENA (1 << 0) -#define DANUBE_SDRAM_MC_CTRLENA_Res (value) (((( 1 << 31) - 1) & (value)) << 1) - -/***MC Mode Register Setup Code***/ -#define DANUBE_SDRAM_MC_MRSCODE ((volatile u32*)(DANUBE_SDRAM+ 0x1008)) -#define DANUBE_SDRAM_MC_MRSCODE_UMC (value) (((( 1 << 5) - 1) & (value)) << 7) -#define DANUBE_SDRAM_MC_MRSCODE_CL (value) (((( 1 << 3) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_MRSCODE_WT (1 << 3) -#define DANUBE_SDRAM_MC_MRSCODE_BL (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***MC Configuration Data-word Width Register***/ -#define DANUBE_SDRAM_MC_CFGDW ((volatile u32*)(DANUBE_SDRAM+ 0x1010)) -#define DANUBE_SDRAM_MC_CFGDW_DW (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_CFGDW_Res (value) (((( 1 << 28) - 1) & (value)) << 4) - -/***MC Configuration Physical Bank 0 Register***/ -#define DANUBE_SDRAM_MC_CFGPB0 ((volatile u32*)(DANUBE_SDRAM+ 0x1018)) -#define DANUBE_SDRAM_MC_CFGPB0_MCSEN0 (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_CFGPB0_BANKN0 (value) (((( 1 << 4) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_CFGPB0_ROWW0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_CFGPB0_COLW0 (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_CFGPB0_Res (value) (((( 1 << 16) - 1) & (value)) << 16) - -/***MC Latency Register***/ -#define DANUBE_SDRAM_MC_LATENCY ((volatile u32*)(DANUBE_SDRAM+ 0x1038)) -#define DANUBE_SDRAM_MC_LATENCY_TRP (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_SDRAM_MC_LATENCY_TRAS (value) (((( 1 << 4) - 1) & (value)) << 12) -#define DANUBE_SDRAM_MC_LATENCY_TRCD (value) (((( 1 << 4) - 1) & (value)) << 8) -#define DANUBE_SDRAM_MC_LATENCY_TDPL (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_SDRAM_MC_LATENCY_TDAL (value) (((( 1 << 4) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_LATENCY_Res (value) (((( 1 << 12) - 1) & (value)) << 20) - -/***MC Refresh Cycle Time Register***/ -#define DANUBE_SDRAM_MC_TREFRESH ((volatile u32*)(DANUBE_SDRAM+ 0x1040)) -#define DANUBE_SDRAM_MC_TREFRESH_TREF (value) (((( 1 << 13) - 1) & (value)) << 0) -#define DANUBE_SDRAM_MC_TREFRESH_Res (value) (((( 1 << 19) - 1) & (value)) << 13) - - -/***********************************************************************/ -/* Module : GPTU register address and bits */ -/***********************************************************************/ - -#define DANUBE_GPTU (0xB8000300) -/***********************************************************************/ - - -/***GPT Clock Control Register***/ -#define DANUBE_GPTU_GPT_CLC ((volatile u32*)(DANUBE_GPTU+ 0x0000)) -#define DANUBE_GPTU_GPT_CLC_RMC (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_GPTU_GPT_CLC_DISS (1 << 1) -#define DANUBE_GPTU_GPT_CLC_DISR (1 << 0) - -/***GPT Timer 3 Control Register***/ -#define DANUBE_GPTU_GPT_T3CON ((volatile u32*)(DANUBE_GPTU+ 0x0014)) -#define DANUBE_GPTU_GPT_T3CON_T3RDIR (1 << 15) -#define DANUBE_GPTU_GPT_T3CON_T3CHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T3CON_T3EDGE (1 << 13) -#define DANUBE_GPTU_GPT_T3CON_BPS1 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define DANUBE_GPTU_GPT_T3CON_T3OTL (1 << 10) -#define DANUBE_GPTU_GPT_T3CON_T3UD (1 << 7) -#define DANUBE_GPTU_GPT_T3CON_T3R (1 << 6) -#define DANUBE_GPTU_GPT_T3CON_T3M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T3CON_T3I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write Hardware Modified Timer 3 Control Register -If set and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT3CON ((volatile u32*)(DANUBE_GPTU+ 0x004C)) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3CHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3CHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3EDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3EDGE (1 << 12) -#define DANUBE_GPTU_GPT_WHBT3CON_SETT3OTL (1 << 11) -#define DANUBE_GPTU_GPT_WHBT3CON_CLRT3OTL (1 << 10) - -/***GPT Timer 2 Control Register***/ -#define DANUBE_GPTU_GPT_T2CON ((volatile u32*)(DANUBE_GPTU+ 0x0010)) -#define DANUBE_GPTU_GPT_T2CON_TxRDIR (1 << 15) -#define DANUBE_GPTU_GPT_T2CON_TxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T2CON_TxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_T2CON_TxIRDIS (1 << 12) -#define DANUBE_GPTU_GPT_T2CON_TxRC (1 << 9) -#define DANUBE_GPTU_GPT_T2CON_TxUD (1 << 7) -#define DANUBE_GPTU_GPT_T2CON_TxR (1 << 6) -#define DANUBE_GPTU_GPT_T2CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T2CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Timer 4 Control Register***/ -#define DANUBE_GPTU_GPT_T4CON ((volatile u32*)(DANUBE_GPTU+ 0x0018)) -#define DANUBE_GPTU_GPT_T4CON_TxRDIR (1 << 15) -#define DANUBE_GPTU_GPT_T4CON_TxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_T4CON_TxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_T4CON_TxIRDIS (1 << 12) -#define DANUBE_GPTU_GPT_T4CON_TxRC (1 << 9) -#define DANUBE_GPTU_GPT_T4CON_TxUD (1 << 7) -#define DANUBE_GPTU_GPT_T4CON_TxR (1 << 6) -#define DANUBE_GPTU_GPT_T4CON_TxM (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T4CON_TxI (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 2 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT2CON ((volatile u32*)(DANUBE_GPTU+ 0x0048)) -#define DANUBE_GPTU_GPT_WHBT2CON_SETTxCHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT2CON_SETTxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT2CON_CLRTxEDGE (1 << 12) - -/***GPT Write HW Modified Timer 4 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT4CON ((volatile u32*)(DANUBE_GPTU+ 0x0050)) -#define DANUBE_GPTU_GPT_WHBT4CON_SETTxCHDIR (1 << 15) -#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxCHDIR (1 << 14) -#define DANUBE_GPTU_GPT_WHBT4CON_SETTxEDGE (1 << 13) -#define DANUBE_GPTU_GPT_WHBT4CON_CLRTxEDGE (1 << 12) - -/***GPT Capture Reload Register***/ -#define DANUBE_GPTU_GPT_CAPREL ((volatile u32*)(DANUBE_GPTU+ 0x0030)) -#define DANUBE_GPTU_GPT_CAPREL_CAPREL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 2 Register***/ -#define DANUBE_GPTU_GPT_T2 ((volatile u32*)(DANUBE_GPTU+ 0x0034)) -#define DANUBE_GPTU_GPT_T2_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 3 Register***/ -#define DANUBE_GPTU_GPT_T3 ((volatile u32*)(DANUBE_GPTU+ 0x0038)) -#define DANUBE_GPTU_GPT_T3_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 4 Register***/ -#define DANUBE_GPTU_GPT_T4 ((volatile u32*)(DANUBE_GPTU+ 0x003C)) -#define DANUBE_GPTU_GPT_T4_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 5 Register***/ -#define DANUBE_GPTU_GPT_T5 ((volatile u32*)(DANUBE_GPTU+ 0x0040)) -#define DANUBE_GPTU_GPT_T5_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Register***/ -#define DANUBE_GPTU_GPT_T6 ((volatile u32*)(DANUBE_GPTU+ 0x0044)) -#define DANUBE_GPTU_GPT_T6_TVAL (value) (((( 1 << 16) - 1) & (value)) << 0) - -/***GPT Timer 6 Control Register***/ -#define DANUBE_GPTU_GPT_T6CON ((volatile u32*)(DANUBE_GPTU+ 0x0020)) -#define DANUBE_GPTU_GPT_T6CON_T6SR (1 << 15) -#define DANUBE_GPTU_GPT_T6CON_T6CLR (1 << 14) -#define DANUBE_GPTU_GPT_T6CON_BPS2 (value) (((( 1 << 2) - 1) & (value)) << 11) -#define DANUBE_GPTU_GPT_T6CON_T6OTL (1 << 10) -#define DANUBE_GPTU_GPT_T6CON_T6UD (1 << 7) -#define DANUBE_GPTU_GPT_T6CON_T6R (1 << 6) -#define DANUBE_GPTU_GPT_T6CON_T6M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T6CON_T6I (value) (((( 1 << 3) - 1) & (value)) << 0) - -/***GPT Write HW Modified Timer 6 Control Register If set - and clear bit are written concurrently with 1, the associated bit is not changed.***/ -#define DANUBE_GPTU_GPT_WHBT6CON ((volatile u32*)(DANUBE_GPTU+ 0x0054)) -#define DANUBE_GPTU_GPT_WHBT6CON_SETT6OTL (1 << 11) -#define DANUBE_GPTU_GPT_WHBT6CON_CLRT6OTL (1 << 10) - -/***GPT Timer 5 Control Register***/ -#define DANUBE_GPTU_GPT_T5CON ((volatile u32*)(DANUBE_GPTU+ 0x001C)) -#define DANUBE_GPTU_GPT_T5CON_T5SC (1 << 15) -#define DANUBE_GPTU_GPT_T5CON_T5CLR (1 << 14) -#define DANUBE_GPTU_GPT_T5CON_CI (value) (((( 1 << 2) - 1) & (value)) << 12) -#define DANUBE_GPTU_GPT_T5CON_T5CC (1 << 11) -#define DANUBE_GPTU_GPT_T5CON_CT3 (1 << 10) -#define DANUBE_GPTU_GPT_T5CON_T5RC (1 << 9) -#define DANUBE_GPTU_GPT_T5CON_T5UDE (1 << 8) -#define DANUBE_GPTU_GPT_T5CON_T5UD (1 << 7) -#define DANUBE_GPTU_GPT_T5CON_T5R (1 << 6) -#define DANUBE_GPTU_GPT_T5CON_T5M (value) (((( 1 << 3) - 1) & (value)) << 3) -#define DANUBE_GPTU_GPT_T5CON_T5I (value) (((( 1 << 3) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : IOM register address and bits */ -/***********************************************************************/ - -#define DANUBE_IOM (0xBF105000) -/***********************************************************************/ - - -/***Receive FIFO***/ -#define DANUBE_IOM_RFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) -#define DANUBE_IOM_RFIFO_RXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Transmit FIFO***/ -#define DANUBE_IOM_XFIFO ((volatile u32*)(DANUBE_IOM+ 0x0000)) -#define DANUBE_IOM_XFIFO_TXD (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Interrupt Status Register HDLC***/ -#define DANUBE_IOM_ISTAH ((volatile u32*)(DANUBE_IOM+ 0x0080)) -#define DANUBE_IOM_ISTAH_RME (1 << 7) -#define DANUBE_IOM_ISTAH_RPF (1 << 6) -#define DANUBE_IOM_ISTAH_RFO (1 << 5) -#define DANUBE_IOM_ISTAH_XPR (1 << 4) -#define DANUBE_IOM_ISTAH_XMR (1 << 3) -#define DANUBE_IOM_ISTAH_XDU (1 << 2) - -/***Interrupt Mask Register HDLC***/ -#define DANUBE_IOM_MASKH ((volatile u32*)(DANUBE_IOM+ 0x0080)) -#define DANUBE_IOM_MASKH_RME (1 << 7) -#define DANUBE_IOM_MASKH_RPF (1 << 6) -#define DANUBE_IOM_MASKH_RFO (1 << 5) -#define DANUBE_IOM_MASKH_XPR (1 << 4) -#define DANUBE_IOM_MASKH_XMR (1 << 3) -#define DANUBE_IOM_MASKH_XDU (1 << 2) - -/***Status Register***/ -#define DANUBE_IOM_STAR ((volatile u32*)(DANUBE_IOM+ 0x0084)) -#define DANUBE_IOM_STAR_XDOV (1 << 7) -#define DANUBE_IOM_STAR_XFW (1 << 6) -#define DANUBE_IOM_STAR_RACI (1 << 3) -#define DANUBE_IOM_STAR_XACI (1 << 1) - -/***Command Register***/ -#define DANUBE_IOM_CMDR ((volatile u32*)(DANUBE_IOM+ 0x0084)) -#define DANUBE_IOM_CMDR_RMC (1 << 7) -#define DANUBE_IOM_CMDR_RRES (1 << 6) -#define DANUBE_IOM_CMDR_XTF (1 << 3) -#define DANUBE_IOM_CMDR_XME (1 << 1) -#define DANUBE_IOM_CMDR_XRES (1 << 0) - -/***Mode Register***/ -#define DANUBE_IOM_MODEH ((volatile u32*)(DANUBE_IOM+ 0x0088)) -#define DANUBE_IOM_MODEH_MDS2 (1 << 7) -#define DANUBE_IOM_MODEH_MDS1 (1 << 6) -#define DANUBE_IOM_MODEH_MDS0 (1 << 5) -#define DANUBE_IOM_MODEH_RAC (1 << 3) -#define DANUBE_IOM_MODEH_DIM2 (1 << 2) -#define DANUBE_IOM_MODEH_DIM1 (1 << 1) -#define DANUBE_IOM_MODEH_DIM0 (1 << 0) - -/***Extended Mode Register***/ -#define DANUBE_IOM_EXMR ((volatile u32*)(DANUBE_IOM+ 0x008C)) -#define DANUBE_IOM_EXMR_XFBS (1 << 7) -#define DANUBE_IOM_EXMR_RFBS (value) (((( 1 << 2) - 1) & (value)) << 5) -#define DANUBE_IOM_EXMR_SRA (1 << 4) -#define DANUBE_IOM_EXMR_XCRC (1 << 3) -#define DANUBE_IOM_EXMR_RCRC (1 << 2) -#define DANUBE_IOM_EXMR_ITF (1 << 0) - -/***SAPI1 Register***/ -#define DANUBE_IOM_SAP1 ((volatile u32*)(DANUBE_IOM+ 0x0094)) -#define DANUBE_IOM_SAP1_SAPI1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_SAP1_MHA (1 << 0) - -/***Receive Frame Byte Count Low***/ -#define DANUBE_IOM_RBCL ((volatile u32*)(DANUBE_IOM+ 0x0098)) -#define DANUBE_IOM_RBCL_RBC(value) (1 << value) - - -/***SAPI2 Register***/ -#define DANUBE_IOM_SAP2 ((volatile u32*)(DANUBE_IOM+ 0x0098)) -#define DANUBE_IOM_SAP2_SAPI2 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_SAP2_MLA (1 << 0) - -/***Receive Frame Byte Count High***/ -#define DANUBE_IOM_RBCH ((volatile u32*)(DANUBE_IOM+ 0x009C)) -#define DANUBE_IOM_RBCH_OV (1 << 4) -#define DANUBE_IOM_RBCH_RBC11 (1 << 3) -#define DANUBE_IOM_RBCH_RBC10 (1 << 2) -#define DANUBE_IOM_RBCH_RBC9 (1 << 1) -#define DANUBE_IOM_RBCH_RBC8 (1 << 0) - -/***TEI1 Register 1***/ -#define DANUBE_IOM_TEI1 ((volatile u32*)(DANUBE_IOM+ 0x009C)) -#define DANUBE_IOM_TEI1_TEI1 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define DANUBE_IOM_TEI1_EA (1 << 0) - -/***Receive Status Register***/ -#define DANUBE_IOM_RSTA ((volatile u32*)(DANUBE_IOM+ 0x00A0)) -#define DANUBE_IOM_RSTA_VFR (1 << 7) -#define DANUBE_IOM_RSTA_RDO (1 << 6) -#define DANUBE_IOM_RSTA_CRC (1 << 5) -#define DANUBE_IOM_RSTA_RAB (1 << 4) -#define DANUBE_IOM_RSTA_SA1 (1 << 3) -#define DANUBE_IOM_RSTA_SA0 (1 << 2) -#define DANUBE_IOM_RSTA_TA (1 << 0) -#define DANUBE_IOM_RSTA_CR (1 << 1) - -/***TEI2 Register***/ -#define DANUBE_IOM_TEI2 ((volatile u32*)(DANUBE_IOM+ 0x00A0)) -#define DANUBE_IOM_TEI2_TEI2 (value) (((( 1 << 7) - 1) & (value)) << 1) -#define DANUBE_IOM_TEI2_EA (1 << 0) - -/***Test Mode Register HDLC***/ -#define DANUBE_IOM_TMH ((volatile u32*)(DANUBE_IOM+ 0x00A4)) -#define DANUBE_IOM_TMH_TLP (1 << 0) - -/***Command/Indication Receive 0***/ -#define DANUBE_IOM_CIR0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) -#define DANUBE_IOM_CIR0_CODR0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_IOM_CIR0_CIC0 (1 << 3) -#define DANUBE_IOM_CIR0_CIC1 (1 << 2) -#define DANUBE_IOM_CIR0_SG (1 << 1) -#define DANUBE_IOM_CIR0_BAS (1 << 0) - -/***Command/Indication Transmit 0***/ -#define DANUBE_IOM_CIX0 ((volatile u32*)(DANUBE_IOM+ 0x00B8)) -#define DANUBE_IOM_CIX0_CODX0 (value) (((( 1 << 4) - 1) & (value)) << 4) -#define DANUBE_IOM_CIX0_TBA2 (1 << 3) -#define DANUBE_IOM_CIX0_TBA1 (1 << 2) -#define DANUBE_IOM_CIX0_TBA0 (1 << 1) -#define DANUBE_IOM_CIX0_BAC (1 << 0) - -/***Command/Indication Receive 1***/ -#define DANUBE_IOM_CIR1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) -#define DANUBE_IOM_CIR1_CODR1 (value) (((( 1 << 6) - 1) & (value)) << 2) - -/***Command/Indication Transmit 1***/ -#define DANUBE_IOM_CIX1 ((volatile u32*)(DANUBE_IOM+ 0x00BC)) -#define DANUBE_IOM_CIX1_CODX1 (value) (((( 1 << 6) - 1) & (value)) << 2) -#define DANUBE_IOM_CIX1_CICW (1 << 1) -#define DANUBE_IOM_CIX1_CI1E (1 << 0) - -/***Controller Data Access Reg. (CH10)***/ -#define DANUBE_IOM_CDA10 ((volatile u32*)(DANUBE_IOM+ 0x0100)) -#define DANUBE_IOM_CDA10_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH11)***/ -#define DANUBE_IOM_CDA11 ((volatile u32*)(DANUBE_IOM+ 0x0104)) -#define DANUBE_IOM_CDA11_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH20)***/ -#define DANUBE_IOM_CDA20 ((volatile u32*)(DANUBE_IOM+ 0x0108)) -#define DANUBE_IOM_CDA20_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Controller Data Access Reg. (CH21)***/ -#define DANUBE_IOM_CDA21 ((volatile u32*)(DANUBE_IOM+ 0x010C)) -#define DANUBE_IOM_CDA21_CDA (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define DANUBE_IOM_CDA_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0110)) -#define DANUBE_IOM_CDA_TSDP10_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define DANUBE_IOM_CDA_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0114)) -#define DANUBE_IOM_CDA_TSDP11_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define DANUBE_IOM_CDA_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0118)) -#define DANUBE_IOM_CDA_TSDP20_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define DANUBE_IOM_CDA_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x011C)) -#define DANUBE_IOM_CDA_TSDP21_DPS (1 << 7) -#define DANUBE_IOM_CDA_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH10)***/ -#define DANUBE_IOM_CO_TSDP10 ((volatile u32*)(DANUBE_IOM+ 0x0120)) -#define DANUBE_IOM_CO_TSDP10_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP10_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH11)***/ -#define DANUBE_IOM_CO_TSDP11 ((volatile u32*)(DANUBE_IOM+ 0x0124)) -#define DANUBE_IOM_CO_TSDP11_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP11_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH20)***/ -#define DANUBE_IOM_CO_TSDP20 ((volatile u32*)(DANUBE_IOM+ 0x0128)) -#define DANUBE_IOM_CO_TSDP20_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP20_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Time Slot and Data Port Sel. (CH21)***/ -#define DANUBE_IOM_CO_TSDP21 ((volatile u32*)(DANUBE_IOM+ 0x012C)) -#define DANUBE_IOM_CO_TSDP21_DPS (1 << 7) -#define DANUBE_IOM_CO_TSDP21_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define DANUBE_IOM_CDA1_CR ((volatile u32*)(DANUBE_IOM+ 0x0138)) -#define DANUBE_IOM_CDA1_CR_EN_TBM (1 << 5) -#define DANUBE_IOM_CDA1_CR_EN_I1 (1 << 4) -#define DANUBE_IOM_CDA1_CR_EN_I0 (1 << 3) -#define DANUBE_IOM_CDA1_CR_EN_O1 (1 << 2) -#define DANUBE_IOM_CDA1_CR_EN_O0 (1 << 1) -#define DANUBE_IOM_CDA1_CR_SWAP (1 << 0) - -/***Ctrl. Reg. Contr. Data Access CH1x***/ -#define DANUBE_IOM_CDA2_CR ((volatile u32*)(DANUBE_IOM+ 0x013C)) -#define DANUBE_IOM_CDA2_CR_EN_TBM (1 << 5) -#define DANUBE_IOM_CDA2_CR_EN_I1 (1 << 4) -#define DANUBE_IOM_CDA2_CR_EN_I0 (1 << 3) -#define DANUBE_IOM_CDA2_CR_EN_O1 (1 << 2) -#define DANUBE_IOM_CDA2_CR_EN_O0 (1 << 1) -#define DANUBE_IOM_CDA2_CR_SWAP (1 << 0) - -/***Control Register B-Channel Data***/ -#define DANUBE_IOM_BCHA_CR ((volatile u32*)(DANUBE_IOM+ 0x0144)) -#define DANUBE_IOM_BCHA_CR_EN_BC2 (1 << 4) -#define DANUBE_IOM_BCHA_CR_EN_BC1 (1 << 3) - -/***Control Register B-Channel Data***/ -#define DANUBE_IOM_BCHB_CR ((volatile u32*)(DANUBE_IOM+ 0x0148)) -#define DANUBE_IOM_BCHB_CR_EN_BC2 (1 << 4) -#define DANUBE_IOM_BCHB_CR_EN_BC1 (1 << 3) - -/***Control Reg. for HDLC and CI1 Data***/ -#define DANUBE_IOM_DCI_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) -#define DANUBE_IOM_DCI_CR_DPS_CI1 (1 << 7) -#define DANUBE_IOM_DCI_CR_EN_CI1 (1 << 6) -#define DANUBE_IOM_DCI_CR_EN_D (1 << 5) - -/***Control Reg. for HDLC and CI1 Data***/ -#define DANUBE_IOM_DCIC_CR ((volatile u32*)(DANUBE_IOM+ 0x014C)) -#define DANUBE_IOM_DCIC_CR_DPS_CI0 (1 << 7) -#define DANUBE_IOM_DCIC_CR_EN_CI0 (1 << 6) -#define DANUBE_IOM_DCIC_CR_DPS_D (1 << 5) - -/***Control Reg. Serial Data Strobe x***/ -#define DANUBE_IOM_SDS_CR ((volatile u32*)(DANUBE_IOM+ 0x0154)) -#define DANUBE_IOM_SDS_CR_ENS_TSS (1 << 7) -#define DANUBE_IOM_SDS_CR_ENS_TSS_1 (1 << 6) -#define DANUBE_IOM_SDS_CR_ENS_TSS_3 (1 << 5) -#define DANUBE_IOM_SDS_CR_TSS (value) (((( 1 << 4) - 1) & (value)) << 0) - -/***Control Register IOM Data***/ -#define DANUBE_IOM_IOM_CR ((volatile u32*)(DANUBE_IOM+ 0x015C)) -#define DANUBE_IOM_IOM_CR_SPU (1 << 7) -#define DANUBE_IOM_IOM_CR_CI_CS (1 << 5) -#define DANUBE_IOM_IOM_CR_TIC_DIS (1 << 4) -#define DANUBE_IOM_IOM_CR_EN_BCL (1 << 3) -#define DANUBE_IOM_IOM_CR_CLKM (1 << 2) -#define DANUBE_IOM_IOM_CR_Res (1 << 1) -#define DANUBE_IOM_IOM_CR_DIS_IOM (1 << 0) - -/***Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_STI ((volatile u32*)(DANUBE_IOM+ 0x0160)) -#define DANUBE_IOM_STI_STOV21 (1 << 7) -#define DANUBE_IOM_STI_STOV20 (1 << 6) -#define DANUBE_IOM_STI_STOV11 (1 << 5) -#define DANUBE_IOM_STI_STOV10 (1 << 4) -#define DANUBE_IOM_STI_STI21 (1 << 3) -#define DANUBE_IOM_STI_STI20 (1 << 2) -#define DANUBE_IOM_STI_STI11 (1 << 1) -#define DANUBE_IOM_STI_STI10 (1 << 0) - -/***Acknowledge Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_ASTI ((volatile u32*)(DANUBE_IOM+ 0x0160)) -#define DANUBE_IOM_ASTI_ACK21 (1 << 3) -#define DANUBE_IOM_ASTI_ACK20 (1 << 2) -#define DANUBE_IOM_ASTI_ACK11 (1 << 1) -#define DANUBE_IOM_ASTI_ACK10 (1 << 0) - -/***Mask Synchronous Transfer Interrupt***/ -#define DANUBE_IOM_MSTI ((volatile u32*)(DANUBE_IOM+ 0x0164)) -#define DANUBE_IOM_MSTI_STOV21 (1 << 7) -#define DANUBE_IOM_MSTI_STOV20 (1 << 6) -#define DANUBE_IOM_MSTI_STOV11 (1 << 5) -#define DANUBE_IOM_MSTI_STOV10 (1 << 4) -#define DANUBE_IOM_MSTI_STI21 (1 << 3) -#define DANUBE_IOM_MSTI_STI20 (1 << 2) -#define DANUBE_IOM_MSTI_STI11 (1 << 1) -#define DANUBE_IOM_MSTI_STI10 (1 << 0) - -/***Configuration Register for Serial Data Strobes***/ -#define DANUBE_IOM_SDS_CONF ((volatile u32*)(DANUBE_IOM+ 0x0168)) -#define DANUBE_IOM_SDS_CONF_SDS_BCL (1 << 0) - -/***Monitoring CDA Bits***/ -#define DANUBE_IOM_MCDA ((volatile u32*)(DANUBE_IOM+ 0x016C)) -#define DANUBE_IOM_MCDA_MCDA21 (value) (((( 1 << 2) - 1) & (value)) << 6) -#define DANUBE_IOM_MCDA_MCDA20 (value) (((( 1 << 2) - 1) & (value)) << 4) -#define DANUBE_IOM_MCDA_MCDA11 (value) (((( 1 << 2) - 1) & (value)) << 2) -#define DANUBE_IOM_MCDA_MCDA10 (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : ASC0 register address and bits */ -/***********************************************************************/ -#define DANUBE_ASC0 (KSEG1+0x1E100400) -/***********************************************************************/ -#define DANUBE_ASC0_TBUF ((volatile u32*)(DANUBE_ASC0 + 0x0020)) -#define DANUBE_ASC0_RBUF ((volatile u32*)(DANUBE_ASC0 + 0x0024)) -#define DANUBE_ASC0_FSTAT ((volatile u32*)(DANUBE_ASC0 + 0x0048)) -#define DANUBE_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define DANUBE_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define DANUBE_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define DANUBE_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : ASC1 register address and bits */ -/***********************************************************************/ - -#define DANUBE_ASC1 (KSEG1+0x1E100C00) - /***********************************************************************/ - -#define DANUBE_ASC1_TBUF ((volatile u32*)(DANUBE_ASC1 + 0x0020)) -#define DANUBE_ASC1_RBUF ((volatile u32*)(DANUBE_ASC1 + 0x0024)) -#define DANUBE_ASC1_FSTAT ((volatile u32*)(DANUBE_ASC1 + 0x0048)) -#define DANUBE_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define DANUBE_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define DANUBE_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define DANUBE_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define DANUBE_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define DANUBE_DMA (0xBE104100) -/***********************************************************************/ - -#define DANUBE_DMA_BASE DANUBE_DMA -#define DANUBE_DMA_CLC (volatile u32*)DANUBE_DMA_BASE -#define DANUBE_DMA_ID (volatile u32*)(DANUBE_DMA_BASE+0x08) -#define DANUBE_DMA_CTRL (volatile u32*)(DANUBE_DMA_BASE+0x10) -#define DANUBE_DMA_CPOLL (volatile u32*)(DANUBE_DMA_BASE+0x14) -#define DANUBE_DMA_CS (volatile u32*)(DANUBE_DMA_BASE+0x18) -#define DANUBE_DMA_CCTRL (volatile u32*)(DANUBE_DMA_BASE+0x1C) -#define DANUBE_DMA_CDBA (volatile u32*)(DANUBE_DMA_BASE+0x20) -#define DANUBE_DMA_CDLEN (volatile u32*)(DANUBE_DMA_BASE+0x24) -#define DANUBE_DMA_CIS (volatile u32*)(DANUBE_DMA_BASE+0x28) -#define DANUBE_DMA_CIE (volatile u32*)(DANUBE_DMA_BASE+0x2C) - -#define DANUBE_DMA_PS (volatile u32*)(DANUBE_DMA_BASE+0x40) -#define DANUBE_DMA_PCTRL (volatile u32*)(DANUBE_DMA_BASE+0x44) - -#define DANUBE_DMA_IRNEN (volatile u32*)(DANUBE_DMA_BASE+0xf4) -#define DANUBE_DMA_IRNCR (volatile u32*)(DANUBE_DMA_BASE+0xf8) -#define DANUBE_DMA_IRNICR (volatile u32*)(DANUBE_DMA_BASE+0xfc) -/***********************************************************************/ -/* Module : Debug register address and bits */ -/***********************************************************************/ - -#define DANUBE_Debug (0xBF106000) -/***********************************************************************/ - - -/***MCD Break Bus Switch Register***/ -#define DANUBE_Debug_MCD_BBS ((volatile u32*)(DANUBE_Debug+ 0x0000)) -#define DANUBE_Debug_MCD_BBS_BTP1 (1 << 19) -#define DANUBE_Debug_MCD_BBS_BTP0 (1 << 18) -#define DANUBE_Debug_MCD_BBS_BSP1 (1 << 17) -#define DANUBE_Debug_MCD_BBS_BSP0 (1 << 16) -#define DANUBE_Debug_MCD_BBS_BT5EN (1 << 15) -#define DANUBE_Debug_MCD_BBS_BT4EN (1 << 14) -#define DANUBE_Debug_MCD_BBS_BT5 (1 << 13) -#define DANUBE_Debug_MCD_BBS_BT4 (1 << 12) -#define DANUBE_Debug_MCD_BBS_BS5EN (1 << 7) -#define DANUBE_Debug_MCD_BBS_BS4EN (1 << 6) -#define DANUBE_Debug_MCD_BBS_BS5 (1 << 5) -#define DANUBE_Debug_MCD_BBS_BS4 (1 << 4) - -/***MCD Multiplexer Control Register***/ -#define DANUBE_Debug_MCD_MCR ((volatile u32*)(DANUBE_Debug+ 0x0008)) -#define DANUBE_Debug_MCD_MCR_MUX5 (1 << 4) -#define DANUBE_Debug_MCD_MCR_MUX4 (1 << 3) -#define DANUBE_Debug_MCD_MCR_MUX1 (1 << 0) - - -/***********************************************************************/ -/* Module : SRAM register address and bits */ -/***********************************************************************/ - -#define DANUBE_SRAM (0xBF980000) -/***********************************************************************/ - - -/***SRAM Size Register***/ -#define DANUBE_SRAM_SRAM_SIZE ((volatile u32*)(DANUBE_SRAM+ 0x0800)) -#define DANUBE_SRAM_SRAM_SIZE_SIZE (value) (((( 1 << 23) - 1) & (value)) << 0) - -/***********************************************************************/ -/* Module : BIU register address and bits */ -/***********************************************************************/ - -#define DANUBE_BIU (0xBFA80000) -/***********************************************************************/ - - -/***BIU Identification Register***/ -#define DANUBE_BIU_BIU_ID ((volatile u32*)(DANUBE_BIU+ 0x0000)) -#define DANUBE_BIU_BIU_ID_ARCH (1 << 16) -#define DANUBE_BIU_BIU_ID_ID (value) (((( 1 << 8) - 1) & (value)) << 8) -#define DANUBE_BIU_BIU_ID_REV (value) (((( 1 << 8) - 1) & (value)) << 0) - -/***BIU Access Error Cause Register***/ -#define DANUBE_BIU_BIU_ERRCAUSE ((volatile u32*)(DANUBE_BIU+ 0x0100)) -#define DANUBE_BIU_BIU_ERRCAUSE_ERR (1 << 31) -#define DANUBE_BIU_BIU_ERRCAUSE_PORT (value) (((( 1 << 4) - 1) & (value)) << 16) -#define DANUBE_BIU_BIU_ERRCAUSE_CAUSE (value) (((( 1 << 2) - 1) & (value)) << 0) - -/***BIU Access Error Address Register***/ -#define DANUBE_BIU_BIU_ERRADDR ((volatile u32*)(DANUBE_BIU+ 0x0108)) -#define DANUBE_BIU_BIU_ERRADDR_ADDR - - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define DANUBE_ICU (0xBF880200) -#define DANUBE_ICU (0xBF880200) -#define DANUBE_ICU_EXI (0xBF101000) -/***********************************************************************/ - - -/***IM0 Interrupt Status Register***/ -#define DANUBE_ICU_IM0_ISR ((volatile u32*)(DANUBE_ICU+ 0x0000)) -#define DANUBE_ICU_IM0_ISR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Status Register***/ -#define DANUBE_ICU_IM1_ISR ((volatile u32*)(DANUBE_ICU+ 0x0020)) -#define DANUBE_ICU_IM1_ISR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Status Register***/ -#define DANUBE_ICU_IM2_ISR ((volatile u32*)(DANUBE_ICU+ 0x0040)) -#define DANUBE_ICU_IM2_ISR_IR(value) (1 << (value)) - -/***IM3 Interrupt Status Register***/ -#define DANUBE_ICU_IM3_ISR ((volatile u32*)(DANUBE_ICU+ 0x0060)) -#define DANUBE_ICU_IM3_ISR_IR(value) (1 << (value)) - -/***IM4 Interrupt Status Register***/ -#define DANUBE_ICU_IM4_ISR ((volatile u32*)(DANUBE_ICU+ 0x0080)) -#define DANUBE_ICU_IM4_ISR_IR(value) (1 << (value)) - - -/***IM0 Interrupt Enable Register***/ -#define DANUBE_ICU_IM0_IER ((volatile u32*)(DANUBE_ICU+ 0x0008)) -#define DANUBE_ICU_IM0_IER_IR(value) (1 << (value)) - - -/***IM1 Interrupt Enable Register***/ -#define DANUBE_ICU_IM1_IER ((volatile u32*)(DANUBE_ICU+ 0x0028)) -#define DANUBE_ICU_IM1_IER_IR(value) (1 << (value)) - - -/***IM2 Interrupt Enable Register***/ -#define DANUBE_ICU_IM2_IER ((volatile u32*)(DANUBE_ICU+ 0x0048)) -#define DANUBE_ICU_IM2_IER_IR(value) (1 << (value)8 - -/***IM3 Interrupt Enable Register***/ -#define DANUBE_ICU_IM3_IER ((volatile u32*)(DANUBE_ICU+ 0x0068)) -#define DANUBE_ICU_IM3_IER_IR(value) (1 << (value)) - -/***IM4 Interrupt Enable Register***/ -#define DANUBE_ICU_IM4_IER ((volatile u32*)(DANUBE_ICU+ 0x0088)) -#define DANUBE_ICU_IM4_IER_IR(value) (1 << (value)) - - -/***IM0 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM0_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0010)) -#define DANUBE_ICU_IM0_IOSR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM1_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0030)) -#define DANUBE_ICU_IM1_IOSR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM2_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0050)) -#define DANUBE_ICU_IM2_IOSR_IR(value) (1 << (value)) - -/***IM3 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM3_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0070)) -#define DANUBE_ICU_IM3_IOSR_IR(value) (1 << (value)) - -/***IM4 Interrupt Output Status Register***/ -#define DANUBE_ICU_IM4_IOSR ((volatile u32*)(DANUBE_ICU+ 0x0090)) -#define DANUBE_ICU_IM4_IOSR_IR(value) (1 << (value)) - - -/***IM0 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM0_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0018)) -#define DANUBE_ICU_IM0_IRSR_IR(value) (1 << (value)) - - -/***IM1 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM1_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0038)) -#define DANUBE_ICU_IM1_IRSR_IR(value) (1 << (value)) - - -/***IM2 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM2_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0058)) -#define DANUBE_ICU_IM2_IRSR_IR(value) (1 << (value)) - -/***IM3 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM3_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0078)) -#define DANUBE_ICU_IM3_IRSR_IR(value) (1 << (value)) - -/***IM4 Interrupt Request Set Register***/ -#define DANUBE_ICU_IM4_IRSR ((volatile u32*)(DANUBE_ICU+ 0x0098)) -#define DANUBE_ICU_IM4_IRSR_IR(value) (1 << (value)) - -/***Interrupt Vector Value Register***/ -#define DANUBE_ICU_IM_VEC ((volatile u32*)(DANUBE_ICU+ 0x0060)) - -/***Interrupt Vector Value Mask***/ -#define DANUBE_ICU_IM0_VEC_MASK 0x0000001f -#define DANUBE_ICU_IM1_VEC_MASK 0x000003e0 -#define DANUBE_ICU_IM2_VEC_MASK 0x00007c00 -#define DANUBE_ICU_IM3_VEC_MASK 0x000f8000 -#define DANUBE_ICU_IM4_VEC_MASK 0x01f00000 - -/***DMA Interrupt Mask Value***/ -#define DANUBE_DMA_H_MASK 0x00000fff - -/***External Interrupt Control Register***/ -#define DANUBE_ICU_EXTINTCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0000)) -#define DANUBE_ICU_IRNICR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0004)) -#define DANUBE_ICU_IRNCR ((volatile u32*)(DANUBE_ICU_EXI+ 0x0008)) -#define DANUBE_ICU_IRNEN ((volatile u32*)(DANUBE_ICU_EXI+ 0x000c)) -#define DANUBE_ICU_NMI_CR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f0)) -#define DANUBE_ICU_NMI_SR ((volatile u32*)(DANUBE_ICU_EXI+ 0x00f4)) - -/***********************************************************************/ -/* Module : MPS register address and bits */ -/***********************************************************************/ - -#define DANUBE_MPS (KSEG1+0x1F107000) -/***********************************************************************/ - -#define DANUBE_MPS_CHIPID ((volatile u32*)(DANUBE_MPS + 0x0344)) -#define DANUBE_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define DANUBE_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define DANUBE_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define DANUBE_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define DANUBE_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define DANUBE_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) - - -/* voice channel 0 ... 3 interrupt enable register */ -#define DANUBE_MPS_VC0ENR ((volatile u32*)(DANUBE_MPS + 0x0000)) -#define DANUBE_MPS_VC1ENR ((volatile u32*)(DANUBE_MPS + 0x0004)) -#define DANUBE_MPS_VC2ENR ((volatile u32*)(DANUBE_MPS + 0x0008)) -#define DANUBE_MPS_VC3ENR ((volatile u32*)(DANUBE_MPS + 0x000C)) -/* voice channel 0 ... 3 interrupt status read register */ -#define DANUBE_MPS_RVC0SR ((volatile u32*)(DANUBE_MPS + 0x0010)) -#define DANUBE_MPS_RVC1SR ((volatile u32*)(DANUBE_MPS + 0x0014)) -#define DANUBE_MPS_RVC2SR ((volatile u32*)(DANUBE_MPS + 0x0018)) -#define DANUBE_MPS_RVC3SR ((volatile u32*)(DANUBE_MPS + 0x001C)) -/* voice channel 0 ... 3 interrupt status set register */ -#define DANUBE_MPS_SVC0SR ((volatile u32*)(DANUBE_MPS + 0x0020)) -#define DANUBE_MPS_SVC1SR ((volatile u32*)(DANUBE_MPS + 0x0024)) -#define DANUBE_MPS_SVC2SR ((volatile u32*)(DANUBE_MPS + 0x0028)) -#define DANUBE_MPS_SVC3SR ((volatile u32*)(DANUBE_MPS + 0x002C)) -/* voice channel 0 ... 3 interrupt status clear register */ -#define DANUBE_MPS_CVC0SR ((volatile u32*)(DANUBE_MPS + 0x0030)) -#define DANUBE_MPS_CVC1SR ((volatile u32*)(DANUBE_MPS + 0x0034)) -#define DANUBE_MPS_CVC2SR ((volatile u32*)(DANUBE_MPS + 0x0038)) -#define DANUBE_MPS_CVC3SR ((volatile u32*)(DANUBE_MPS + 0x003C)) -/* common status 0 and 1 read register */ -#define DANUBE_MPS_RAD0SR ((volatile u32*)(DANUBE_MPS + 0x0040)) -#define DANUBE_MPS_RAD1SR ((volatile u32*)(DANUBE_MPS + 0x0044)) -/* common status 0 and 1 set register */ -#define DANUBE_MPS_SAD0SR ((volatile u32*)(DANUBE_MPS + 0x0048)) -#define DANUBE_MPS_SAD1SR ((volatile u32*)(DANUBE_MPS + 0x004C)) -/* common status 0 and 1 clear register */ -#define DANUBE_MPS_CAD0SR ((volatile u32*)(DANUBE_MPS + 0x0050)) -#define DANUBE_MPS_CAD1SR ((volatile u32*)(DANUBE_MPS + 0x0054)) -/* common status 0 and 1 enable register */ -#define DANUBE_MPS_AD0ENR ((volatile u32*)(DANUBE_MPS + 0x0058)) -#define DANUBE_MPS_AD1ENR ((volatile u32*)(DANUBE_MPS + 0x005C)) -/* notification enable register */ -#define DANUBE_MPS_CPU0_NFER ((volatile u32*)(DANUBE_MPS + 0x0060)) -#define DANUBE_MPS_CPU1_NFER ((volatile u32*)(DANUBE_MPS + 0x0064)) -/* CPU to CPU interrup request register */ -#define DANUBE_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(DANUBE_MPS + 0x0070)) -#define DANUBE_MPS_CPU0_2_CPU1_IER ((volatile u32*)(DANUBE_MPS + 0x0074)) -/* Global interrupt request and request enable register */ -#define DANUBE_MPS_GIRR ((volatile u32*)(DANUBE_MPS + 0x0078)) -#define DANUBE_MPS_GIER ((volatile u32*)(DANUBE_MPS + 0x007C)) - - -#define DANUBE_MPS_CPU0_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00100)) - -#define DANUBE_MPS_CPU1_SMP0 ((volatile u32*)(DANUBE_MPS + 0x00200)) - -/************************************************************************/ -/* Module : DEU register address and bits */ -/************************************************************************/ -#define DANUBE_DEU_BASE_ADDR (0xBE102000) -/* DEU Control Register */ -#define DANUBE_DEU_CLK ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0000)) -#define DANUBE_DEU_ID ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0008)) - -/* DEU control register */ -#define DANUBE_DEU_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0010)) -#define DANUBE_DEU_IHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0014)) -#define DANUBE_DEU_ILR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0018)) -#define DANUBE_DEU_K1HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x001C)) -#define DANUBE_DEU_K1LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0020)) -#define DANUBE_DEU_K3HR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0024)) -#define DANUBE_DEU_K3LR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0028)) -#define DANUBE_DEU_IVHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x002C)) -#define DANUBE_DEU_IVLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0030)) -#define DANUBE_DEU_OHR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0040)) -#define DANUBE_DEU_OLR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) - -/* AES DEU register */ -#define DANUBE_AES_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0050)) -#define DANUBE_AES_ID3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0054)) -#define DANUBE_AES_ID2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0058)) -#define DANUBE_AES_ID1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x005C)) -#define DANUBE_AES_ID0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0060)) - -/* AES Key register */ -#define DANUBE_AES_K7R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0064)) -#define DANUBE_AES_K6R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0068)) -#define DANUBE_AES_K5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x006C)) -#define DANUBE_AES_K4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0070)) -#define DANUBE_AES_K3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0074)) -#define DANUBE_AES_K2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0078)) -#define DANUBE_AES_K1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x007C)) -#define DANUBE_AES_K0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0080)) - -/* AES vector register */ -#define DANUBE_AES_IV3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0084)) -#define DANUBE_AES_IV2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0088)) -#define DANUBE_AES_IV1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x008C)) -#define DANUBE_AES_IV0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0090)) -#define DANUBE_AES_0D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0094)) -#define DANUBE_AES_0D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x0098)) -#define DANUBE_AES_OD1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x009C)) -#define DANUBE_AES_OD0R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00A0)) - -/* hash control registe */ -#define DANUBE_HASH_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B0)) -#define DANUBE_HASH_MR ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B4)) -#define DANUBE_HASH_D1R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00B8 )) -#define DANUBE_HASH_D2R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00BC )) -#define DANUBE_HASH_D3R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C0 )) -#define DANUBE_HASH_D4R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C4)) -#define DANUBE_HASH_D5R ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00C8)) - -#define DANUBE_CON ((volatile u32 *)(DANUBE_DEU_BASE_ADDR + 0x00EC)) - - - - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE_BASE_ADDR (KSEG1 + 0x1E180000) -#define DANUBE_PPE_PP32_DEBUG_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0000) << 2))) -#define DANUBE_PPE_PPM_INT_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0030) << 2))) -#define DANUBE_PPE_PP32_INTERNAL_RES_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0040) << 2))) -#define DANUBE_PPE_PPE_CLOCK_CONTROL_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x0100) << 2))) -#define DANUBE_PPE_CDM_CODE_MEMORY_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x1000) << 2))) -#define DANUBE_PPE_CDM_CODE_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x2000) << 2))) -#define DANUBE_PPE_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x4000) << 2))) -#define DANUBE_PPE_PP32_DATA_MEMORY_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x5000) << 2))) -#define DANUBE_PPE_PPM_INT_UNIT_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6000) << 2))) -#define DANUBE_PPE_PPM_TIMER0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6100) << 2))) -#define DANUBE_PPE_PPM_TASK_IND_REG_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6200) << 2))) -#define DANUBE_PPE_PPS_BRK_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6300) << 2))) -#define DANUBE_PPE_PPM_TIMER1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x6400) << 2))) -#define DANUBE_PPE_SB_RAM0_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8000) << 2))) -#define DANUBE_PPE_SB_RAM1_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8400) << 2))) -#define DANUBE_PPE_SB_RAM2_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x8C00) << 2))) -#define DANUBE_PPE_SB_RAM3_ADDR(x) ((volatile u32*)(DANUBE_PPE_BASE_ADDR + (((x) + 0x9600) << 2))) - -#define DANUBE_PPE_PP32_SLEEP DANUBE_PPE_REG_ADDR(0x0010) /* PP32 Power Saving Register */ -#define DANUBE_PPE_CDM_CFG DANUBE_PPE_REG_ADDR(0x0100) /* Code/Data Memory (CDM) Register */ - -/* Mailbox Registers */ -#define DANUBE_PPE_MBOX_IGU0_ISRS DANUBE_PPE_REG_ADDR(0x0200) -#define DANUBE_PPE_MBOX_IGU0_ISRC DANUBE_PPE_REG_ADDR(0x0201) -#define DANUBE_PPE_MBOX_IGU0_ISR DANUBE_PPE_REG_ADDR(0x0202) -#define DANUBE_PPE_MBOX_IGU0_IER DANUBE_PPE_REG_ADDR(0x0203) -#define DANUBE_PPE_MBOX_IGU1_ISRS0 DANUBE_PPE_REG_ADDR(0x0204) -#define DANUBE_PPE_MBOX_IGU1_ISRC0 DANUBE_PPE_REG_ADDR(0x0205) -#define DANUBE_PPE_MBOX_IGU1_ISR0 DANUBE_PPE_REG_ADDR(0x0206) -#define DANUBE_PPE_MBOX_IGU1_IER0 DANUBE_PPE_REG_ADDR(0x0207) -#define DANUBE_PPE_MBOX_IGU1_ISRS1 DANUBE_PPE_REG_ADDR(0x0208) -#define DANUBE_PPE_MBOX_IGU1_ISRC1 DANUBE_PPE_REG_ADDR(0x0209) -#define DANUBE_PPE_MBOX_IGU1_ISR1 DANUBE_PPE_REG_ADDR(0x020A) -#define DANUBE_PPE_MBOX_IGU1_IER1 DANUBE_PPE_REG_ADDR(0x020B) -#define DANUBE_PPE_MBOX_IGU1_ISRS2 DANUBE_PPE_REG_ADDR(0x020C) -#define DANUBE_PPE_MBOX_IGU1_ISRC2 DANUBE_PPE_REG_ADDR(0x020D) -#define DANUBE_PPE_MBOX_IGU1_ISR2 DANUBE_PPE_REG_ADDR(0x020E) -#define DANUBE_PPE_MBOX_IGU1_IER2 DANUBE_PPE_REG_ADDR(0x020F) -#define DANUBE_PPE_MBOX_IGU2_ISRS DANUBE_PPE_REG_ADDR(0x0210) -#define DANUBE_PPE_MBOX_IGU2_ISRC DANUBE_PPE_REG_ADDR(0x0211) -#define DANUBE_PPE_MBOX_IGU2_ISR DANUBE_PPE_REG_ADDR(0x0212) -#define DANUBE_PPE_MBOX_IGU2_IER DANUBE_PPE_REG_ADDR(0x0213) -#define DANUBE_PPE_MBOX_IGU3_ISRS DANUBE_PPE_REG_ADDR(0x0214) -#define DANUBE_PPE_MBOX_IGU3_ISRC DANUBE_PPE_REG_ADDR(0x0215) -#define DANUBE_PPE_MBOX_IGU3_ISR DANUBE_PPE_REG_ADDR(0x0216) -#define DANUBE_PPE_MBOX_IGU3_IER DANUBE_PPE_REG_ADDR(0x0217) -#define DANUBE_PPE_MBOX_IGU4_ISRS DANUBE_PPE_REG_ADDR(0x0218) -#define DANUBE_PPE_MBOX_IGU4_ISRC DANUBE_PPE_REG_ADDR(0x0219) -#define DANUBE_PPE_MBOX_IGU4_ISR DANUBE_PPE_REG_ADDR(0x021A) -#define DANUBE_PPE_MBOX_IGU4_IER DANUBE_PPE_REG_ADDR(0x021B) -/* - * Shared Buffer (SB) Registers - */ -#define DANUBE_PPE_SB_MST_PRI0 DANUBE_PPE_REG_ADDR(0x0300) -#define DANUBE_PPE_SB_MST_PRI1 DANUBE_PPE_REG_ADDR(0x0301) -#define DANUBE_PPE_SB_MST_PRI2 DANUBE_PPE_REG_ADDR(0x0302) -#define DANUBE_PPE_SB_MST_PRI3 DANUBE_PPE_REG_ADDR(0x0303) -#define DANUBE_PPE_SB_MST_PRI4 DANUBE_PPE_REG_ADDR(0x0304) -#define DANUBE_PPE_SB_MST_SEL DANUBE_PPE_REG_ADDR(0x0305) -/* - * RTHA Registers - */ -#define DANUBE_PPE_RFBI_CFG DANUBE_PPE_REG_ADDR(0x0400) -#define DANUBE_PPE_RBA_CFG0 DANUBE_PPE_REG_ADDR(0x0404) -#define DANUBE_PPE_RBA_CFG1 DANUBE_PPE_REG_ADDR(0x0405) -#define DANUBE_PPE_RCA_CFG0 DANUBE_PPE_REG_ADDR(0x0408) -#define DANUBE_PPE_RCA_CFG1 DANUBE_PPE_REG_ADDR(0x0409) -#define DANUBE_PPE_RDES_CFG0 DANUBE_PPE_REG_ADDR(0x040C) -#define DANUBE_PPE_RDES_CFG1 DANUBE_PPE_REG_ADDR(0x040D) -#define DANUBE_PPE_SFSM_STATE0 DANUBE_PPE_REG_ADDR(0x0410) -#define DANUBE_PPE_SFSM_STATE1 DANUBE_PPE_REG_ADDR(0x0411) -#define DANUBE_PPE_SFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0412) -#define DANUBE_PPE_SFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0413) -#define DANUBE_PPE_SFSM_CBA0 DANUBE_PPE_REG_ADDR(0x0414) -#define DANUBE_PPE_SFSM_CBA1 DANUBE_PPE_REG_ADDR(0x0415) -#define DANUBE_PPE_SFSM_CFG0 DANUBE_PPE_REG_ADDR(0x0416) -#define DANUBE_PPE_SFSM_CFG1 DANUBE_PPE_REG_ADDR(0x0417) -#define DANUBE_PPE_SFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x041C) -#define DANUBE_PPE_SFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x041D) -/* - * TTHA Registers - */ -#define DANUBE_PPE_FFSM_DBA0 DANUBE_PPE_REG_ADDR(0x0508) -#define DANUBE_PPE_FFSM_DBA1 DANUBE_PPE_REG_ADDR(0x0509) -#define DANUBE_PPE_FFSM_CFG0 DANUBE_PPE_REG_ADDR(0x050A) -#define DANUBE_PPE_FFSM_CFG1 DANUBE_PPE_REG_ADDR(0x050B) -#define DANUBE_PPE_FFSM_IDLE_HEAD_BC0 DANUBE_PPE_REG_ADDR(0x050E) -#define DANUBE_PPE_FFSM_IDLE_HEAD_BC1 DANUBE_PPE_REG_ADDR(0x050F) -#define DANUBE_PPE_FFSM_PGCNT0 DANUBE_PPE_REG_ADDR(0x0514) -#define DANUBE_PPE_FFSM_PGCNT1 DANUBE_PPE_REG_ADDR(0x0515) -/* - * ETOP MDIO Registers - */ -#define DANUBE_PPE_ETOP_MDIO_CFG DANUBE_PPE_REG_ADDR(0x0600) -#define DANUBE_PPE_ETOP_MDIO_ACC DANUBE_PPE_REG_ADDR(0x0601) -#define DANUBE_PPE_ETOP_CFG DANUBE_PPE_REG_ADDR(0x0602) -#define DANUBE_PPE_ETOP_IG_VLAN_COS DANUBE_PPE_REG_ADDR(0x0603) -#define DANUBE_PPE_ETOP_IG_DSCP_COS3 DANUBE_PPE_REG_ADDR(0x0604) -#define DANUBE_PPE_ETOP_IG_DSCP_COS2 DANUBE_PPE_REG_ADDR(0x0605) -#define DANUBE_PPE_ETOP_IG_DSCP_COS1 DANUBE_PPE_REG_ADDR(0x0606) -#define DANUBE_PPE_ETOP_IG_DSCP_COS0 DANUBE_PPE_REG_ADDR(0x0607) -#define DANUBE_PPE_ETOP_IG_PLEN_CTRL0 DANUBE_PPE_REG_ADDR(0x0608) -#define DANUBE_PPE_ETOP_IG_PLEN_CTRL1 DANUBE_PPE_REG_ADDR(0x0609) -#define DANUBE_PPE_ETOP_ISR DANUBE_PPE_REG_ADDR(0x060A) -#define DANUBE_PPE_ETOP_IER DANUBE_PPE_REG_ADDR(0x060B) -#define DANUBE_PPE_ETOP_VPID DANUBE_PPE_REG_ADDR(0x060C) -#define DANUBE_PPE_ENET_MAC_CFG DANUBE_PPE_REG_ADDR(0x0610) -#define DANUBE_PPE_ENETS_DBA DANUBE_PPE_REG_ADDR(0x0612) -#define DANUBE_PPE_ENETS_CBA DANUBE_PPE_REG_ADDR(0x0613) -#define DANUBE_PPE_ENETS_CFG DANUBE_PPE_REG_ADDR(0x0614) -#define DANUBE_PPE_ENETS_PGCNT DANUBE_PPE_REG_ADDR(0x0615) -#define DANUBE_PPE_ENETS_PGCNT_DSRC_PP32 (0x00020000) -#define DANUBE_PPE_ENETS_PGCNT_DVAL_SHIFT (9) -#define DANUBE_PPE_ENETS_PGCNT_DCMD (0x00000100) -#define DANUBE_PPE_ENETS_PKTCNT DANUBE_PPE_REG_ADDR(0x0616) -#define DANUBE_PPE_ENETS_PKTCNT_DSRC_PP32 (0x00000200) -#define DANUBE_PPE_ENETS_PKTCNT_DCMD (0x00000100) -#define DANUBE_PPE_ENETS_PKTCNT_UPKT (0x000000FF) -#define DANUBE_PPE_ENETS_BUF_CTRL DANUBE_PPE_REG_ADDR(0x0617) -#define DANUBE_PPE_ENETS_COS_CFG DANUBE_PPE_REG_ADDR(0x0618) -#define DANUBE_PPE_ENETS_IGDROP DANUBE_PPE_REG_ADDR(0x0619) -#define DANUBE_PPE_ENETF_DBA DANUBE_PPE_REG_ADDR(0x0630) -#define DANUBE_PPE_ENETF_CBA DANUBE_PPE_REG_ADDR(0x0631) -#define DANUBE_PPE_ENETF_CFG DANUBE_PPE_REG_ADDR(0x0632) -#define DANUBE_PPE_ENETF_PGCNT DANUBE_PPE_REG_ADDR(0x0633) -#define DANUBE_PPE_ENETF_PGCNT_ISRC_PP32 (0x00020000) -#define DANUBE_PPE_ENETF_PGCNT_IVAL_SHIFT (9) -#define DANUBE_PPE_ENETF_PGCNT_ICMD (0x00000100) -#define DANUBE_PPE_ENETF_PKTCNT DANUBE_PPE_REG_ADDR(0x0634) -#define DANUBE_PPE_ENETF_PKTCNT_ISRC_PP32 (0x00000200) -#define DANUBE_PPE_ENETF_PKTCNT_ICMD (0x00000100) -#define DANUBE_PPE_ENETF_PKTCNT_VPKT (0x000000FF) -#define DANUBE_PPE_ENETF_HFCTRL DANUBE_PPE_REG_ADDR(0x0635) -#define DANUBE_PPE_ENETF_TXCTRL DANUBE_PPE_REG_ADDR(0x0636) -#define DANUBE_PPE_ENETF_VLCOS0 DANUBE_PPE_REG_ADDR(0x0638) -#define DANUBE_PPE_ENETF_VLCOS1 DANUBE_PPE_REG_ADDR(0x0639) -#define DANUBE_PPE_ENETF_VLCOS2 DANUBE_PPE_REG_ADDR(0x063A) -#define DANUBE_PPE_ENETF_VLCOS3 DANUBE_PPE_REG_ADDR(0x063B) -#define DANUBE_PPE_ENETF_EGERR DANUBE_PPE_REG_ADDR(0x063C) -#define DANUBE_PPE_ENETF_EGDROP DANUBE_PPE_REG_ADDR(0x063D) -/* - * DPLUS Registers - */ -#define DANUBE_PPE_DPLUS_TXDB DANUBE_PPE_REG_ADDR(0x0700) -#define DANUBE_PPE_DPLUS_TXCB DANUBE_PPE_REG_ADDR(0x0701) -#define DANUBE_PPE_DPLUS_TXCFG DANUBE_PPE_REG_ADDR(0x0702) -#define DANUBE_PPE_DPLUS_TXPGCNT DANUBE_PPE_REG_ADDR(0x0703) -#define DANUBE_PPE_DPLUS_RXDB DANUBE_PPE_REG_ADDR(0x0710) -#define DANUBE_PPE_DPLUS_RXCB DANUBE_PPE_REG_ADDR(0x0711) -#define DANUBE_PPE_DPLUS_RXCFG DANUBE_PPE_REG_ADDR(0x0712) -#define DANUBE_PPE_DPLUS_RXPGCNT DANUBE_PPE_REG_ADDR(0x0713) -/* - * BMC Registers - */ -#define DANUBE_PPE_BMC_CMD3 DANUBE_PPE_REG_ADDR(0x0800) -#define DANUBE_PPE_BMC_CMD2 DANUBE_PPE_REG_ADDR(0x0801) -#define DANUBE_PPE_BMC_CMD1 DANUBE_PPE_REG_ADDR(0x0802) -#define DANUBE_PPE_BMC_CMD0 DANUBE_PPE_REG_ADDR(0x0803) -#define DANUBE_PPE_BMC_CFG0 DANUBE_PPE_REG_ADDR(0x0804) -#define DANUBE_PPE_BMC_CFG1 DANUBE_PPE_REG_ADDR(0x0805) -#define DANUBE_PPE_BMC_POLY0 DANUBE_PPE_REG_ADDR(0x0806) -#define DANUBE_PPE_BMC_POLY1 DANUBE_PPE_REG_ADDR(0x0807) -#define DANUBE_PPE_BMC_CRC0 DANUBE_PPE_REG_ADDR(0x0808) -#define DANUBE_PPE_BMC_CRC1 DANUBE_PPE_REG_ADDR(0x0809) -/* - * SLL Registers - */ -#define DANUBE_PPE_SLL_CMD1 DANUBE_PPE_REG_ADDR(0x0900) -#define DANUBE_PPE_SLL_CMD0 DANUBE_PPE_REG_ADDR(0x0901) -#define DANUBE_PPE_SLL_KEY0 DANUBE_PPE_REG_ADDR(0x0910) -#define DANUBE_PPE_SLL_KEY1 DANUBE_PPE_REG_ADDR(0x0911) -#define DANUBE_PPE_SLL_KEY2 DANUBE_PPE_REG_ADDR(0x0912) -#define DANUBE_PPE_SLL_KEY3 DANUBE_PPE_REG_ADDR(0x0913) -#define DANUBE_PPE_SLL_KEY4 DANUBE_PPE_REG_ADDR(0x0914) -#define DANUBE_PPE_SLL_KEY5 DANUBE_PPE_REG_ADDR(0x0915) -#define DANUBE_PPE_SLL_RESULT DANUBE_PPE_REG_ADDR(0x0920) -/* - * EMA Registers - */ -#define DANUBE_PPE_EMA_CMD2 DANUBE_PPE_REG_ADDR(0x0A00) -#define DANUBE_PPE_EMA_CMD1 DANUBE_PPE_REG_ADDR(0x0A01) -#define DANUBE_PPE_EMA_CMD0 DANUBE_PPE_REG_ADDR(0x0A02) -#define DANUBE_PPE_EMA_ISR DANUBE_PPE_REG_ADDR(0x0A04) -#define DANUBE_PPE_EMA_IER DANUBE_PPE_REG_ADDR(0x0A05) -#define DANUBE_PPE_EMA_CFG DANUBE_PPE_REG_ADDR(0x0A06) -/* - * UTPS Registers - */ -#define DANUBE_PPE_UTP_TXCA0 DANUBE_PPE_REG_ADDR(0x0B00) -#define DANUBE_PPE_UTP_TXNA0 DANUBE_PPE_REG_ADDR(0x0B01) -#define DANUBE_PPE_UTP_TXCA1 DANUBE_PPE_REG_ADDR(0x0B02) -#define DANUBE_PPE_UTP_TXNA1 DANUBE_PPE_REG_ADDR(0x0B03) -#define DANUBE_PPE_UTP_RXCA0 DANUBE_PPE_REG_ADDR(0x0B10) -#define DANUBE_PPE_UTP_RXNA0 DANUBE_PPE_REG_ADDR(0x0B11) -#define DANUBE_PPE_UTP_RXCA1 DANUBE_PPE_REG_ADDR(0x0B12) -#define DANUBE_PPE_UTP_RXNA1 DANUBE_PPE_REG_ADDR(0x0B13) -#define DANUBE_PPE_UTP_CFG DANUBE_PPE_REG_ADDR(0x0B20) -#define DANUBE_PPE_UTP_ISR DANUBE_PPE_REG_ADDR(0x0B30) -#define DANUBE_PPE_UTP_IER DANUBE_PPE_REG_ADDR(0x0B31) -/* - * QSB Registers - */ -#define DANUBE_PPE_QSB_RELOG DANUBE_PPE_REG_ADDR(0x0C00) -#define DANUBE_PPE_QSB_EMIT0 DANUBE_PPE_REG_ADDR(0x0C01) -#define DANUBE_PPE_QSB_EMIT1 DANUBE_PPE_REG_ADDR(0x0C02) -#define DANUBE_PPE_QSB_ICDV DANUBE_PPE_REG_ADDR(0x0C07) -#define DANUBE_PPE_QSB_SBL DANUBE_PPE_REG_ADDR(0x0C09) -#define DANUBE_PPE_QSB_CFG DANUBE_PPE_REG_ADDR(0x0C0A) -#define DANUBE_PPE_QSB_RTM DANUBE_PPE_REG_ADDR(0x0C0B) -#define DANUBE_PPE_QSB_RTD DANUBE_PPE_REG_ADDR(0x0C0C) -#define DANUBE_PPE_QSB_RAMAC DANUBE_PPE_REG_ADDR(0x0C0D) -#define DANUBE_PPE_QSB_ISTAT DANUBE_PPE_REG_ADDR(0x0C0E) -#define DANUBE_PPE_QSB_IMR DANUBE_PPE_REG_ADDR(0x0C0F) -#define DANUBE_PPE_QSB_SRC DANUBE_PPE_REG_ADDR(0x0C10) -/* - * DSP User Registers - */ -#define DANUBE_PPE_DREG_A_VERSION DANUBE_PPE_REG_ADDR(0x0D00) -#define DANUBE_PPE_DREG_A_CFG DANUBE_PPE_REG_ADDR(0x0D01) -#define DANUBE_PPE_DREG_AT_CTRL DANUBE_PPE_REG_ADDR(0x0D02) -#define DANUBE_PPE_DREG_AR_CTRL DANUBE_PPE_REG_ADDR(0x0D08) -#define DANUBE_PPE_DREG_A_UTPCFG DANUBE_PPE_REG_ADDR(0x0D0E) -#define DANUBE_PPE_DREG_A_STATUS DANUBE_PPE_REG_ADDR(0x0D0F) -#define DANUBE_PPE_DREG_AT_CFG0 DANUBE_PPE_REG_ADDR(0x0D20) -#define DANUBE_PPE_DREG_AT_CFG1 DANUBE_PPE_REG_ADDR(0x0D21) -#define DANUBE_PPE_DREG_FB_SIZE0 DANUBE_PPE_REG_ADDR(0x0D22) -#define DANUBE_PPE_DREG_FB_SIZE1 DANUBE_PPE_REG_ADDR(0x0D23) -#define DANUBE_PPE_DREG_AT_CELL0 DANUBE_PPE_REG_ADDR(0x0D24) -#define DANUBE_PPE_DREG_AT_CELL1 DANUBE_PPE_REG_ADDR(0x0D25) -#define DANUBE_PPE_DREG_AT_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D26) -#define DANUBE_PPE_DREG_AT_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D27) -#define DANUBE_PPE_DREG_AT_IDLE0 DANUBE_PPE_REG_ADDR(0x0D28) -#define DANUBE_PPE_DREG_AT_IDLE1 DANUBE_PPE_REG_ADDR(0x0D29) -#define DANUBE_PPE_DREG_AR_CFG0 DANUBE_PPE_REG_ADDR(0x0D60) -#define DANUBE_PPE_DREG_AR_CFG1 DANUBE_PPE_REG_ADDR(0x0D61) -#define DANUBE_PPE_DREG_AR_FB_START0 DANUBE_PPE_REG_ADDR(0x0D62) -#define DANUBE_PPE_DREG_AR_FB_START1 DANUBE_PPE_REG_ADDR(0x0D63) -#define DANUBE_PPE_DREG_AR_FB_END0 DANUBE_PPE_REG_ADDR(0x0D64) -#define DANUBE_PPE_DREG_AR_FB_END1 DANUBE_PPE_REG_ADDR(0x0D65) -#define DANUBE_PPE_DREG_AR_ATM_STAT0 DANUBE_PPE_REG_ADDR(0x0D66) -#define DANUBE_PPE_DREG_AR_ATM_STAT1 DANUBE_PPE_REG_ADDR(0x0D67) -#define DANUBE_PPE_DREG_AR_CELL0 DANUBE_PPE_REG_ADDR(0x0D68) -#define DANUBE_PPE_DREG_AR_CELL1 DANUBE_PPE_REG_ADDR(0x0D69) -#define DANUBE_PPE_DREG_AR_IDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6A) -#define DANUBE_PPE_DREG_AR_IDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6B) -#define DANUBE_PPE_DREG_AR_AIIDLE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6C) -#define DANUBE_PPE_DREG_AR_AIIDLE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6D) -#define DANUBE_PPE_DREG_AR_BE_CNT0 DANUBE_PPE_REG_ADDR(0x0D6E) -#define DANUBE_PPE_DREG_AR_BE_CNT1 DANUBE_PPE_REG_ADDR(0x0D6F) -#define DANUBE_PPE_DREG_AR_HEC_CNT0 DANUBE_PPE_REG_ADDR(0x0D70) -#define DANUBE_PPE_DREG_AR_HEC_CNT1 DANUBE_PPE_REG_ADDR(0x0D71) -#define DANUBE_PPE_DREG_AR_CD_CNT0 DANUBE_PPE_REG_ADDR(0x0D72) -#define DANUBE_PPE_DREG_AR_CD_CNT1 DANUBE_PPE_REG_ADDR(0x0D73) -#define DANUBE_PPE_DREG_AR_IDLE0 DANUBE_PPE_REG_ADDR(0x0D74) -#define DANUBE_PPE_DREG_AR_IDLE1 DANUBE_PPE_REG_ADDR(0x0D75) -#define DANUBE_PPE_DREG_AR_DELIN0 DANUBE_PPE_REG_ADDR(0x0D76) -#define DANUBE_PPE_DREG_AR_DELIN1 DANUBE_PPE_REG_ADDR(0x0D77) -#define DANUBE_PPE_DREG_RESV0 DANUBE_PPE_REG_ADDR(0x0D78) -#define DANUBE_PPE_DREG_RESV1 DANUBE_PPE_REG_ADDR(0x0D79) -#define DANUBE_PPE_DREG_RX_MIB_CMD0 DANUBE_PPE_REG_ADDR(0x0D80) -#define DANUBE_PPE_DREG_RX_MIB_CMD1 DANUBE_PPE_REG_ADDR(0x0D81) -#define DANUBE_PPE_DREG_AR_OVDROP_CNT0 DANUBE_PPE_REG_ADDR(0x0D98) -#define DANUBE_PPE_DREG_AR_OVDROP_CNT1 DANUBE_PPE_REG_ADDR(0x0D99) - - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE32_BASE 0xBE180000 -#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4)) -#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4)) -#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4)) -#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) - -/************************************************************************/ -/* Module : PPE register address and bits */ -/************************************************************************/ -#define DANUBE_PPE32_BASE 0xBE180000 -#define DANUBE_PPE32_DEBUG_BREAK_TRACE_REG (DANUBE_PPE32_BASE + (0x0000 * 4)) -#define DANUBE_PPE32_INT_MASK_STATUS_REG (DANUBE_PPE32_BASE + (0x0030 * 4)) -#define DANUBE_PPE32_INT_RESOURCE_REG (DANUBE_PPE32_BASE + (0x0040 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B0 (DANUBE_PPE32_BASE + (0x1000 * 4)) -#define DANUBE_PPE32_CDM_CODE_MEM_B1 (DANUBE_PPE32_BASE + (0x2000 * 4)) -#define DANUBE_PPE32_DATA_MEM_MAP_REG_BASE (DANUBE_PPE32_BASE + (0x4000 * 4)) - -/* - * ETOP MDIO Registers - */ -#define ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -#define ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -#define ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -#define ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -#define ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -#define ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -#define ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -#define ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -#define ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -#define ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -#define ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -#define ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -#define ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -#define ENETS_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -#define ENETS_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -#define ENETS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -#define ENETS_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -#define ENETS_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -#define ENETS_BUF_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -#define ENETS_COS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -#define ENETS_IGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -#define ENETS_IGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -#define ENET_MAC_DA0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -#define ENET_MAC_DA1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) - -#define ENETF_DBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -#define ENETF_CBA ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -#define ENETF_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -#define ENETF_PGCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -#define ENETF_PKTCNT ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -#define ENETF_HFCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -#define ENETF_TXCTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) - -#define ENETF_VLCOS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -#define ENETF_VLCOS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -#define ENETF_VLCOS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -#define ENETF_VLCOS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -#define ENETF_EGERR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -#define ENETF_EGDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) - - -/* - * ETOP MDIO Registers - */ -#define DANUBE_PPE32_ETOP_MDIO_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -#define DANUBE_PPE32_ETOP_MDIO_ACC ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -#define DANUBE_PPE32_ETOP_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -#define DANUBE_PPE32_ETOP_IG_VLAN_COS ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -#define DANUBE_PPE32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -#define DANUBE_PPE32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -#define DANUBE_PPE32_ETOP_ISR ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -#define DANUBE_PPE32_ETOP_IER ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -#define DANUBE_PPE32_ETOP_VPID ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) - - -/* ENET Register */ -#define DANUBE_PPE32_ENET_MAC_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -#define DANUBE_PPE32_ENET_IG_PKTDROP ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -#define DANUBE_PPE32_ENET_CoS_CFG ((volatile u32 *)(DANUBE_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) - -/*********LED register definition****************/ - -#define DANUBE_LED 0xBE100BB0 -#define DANUBE_LED_CON0 ((volatile u32*)(DANUBE_LED + 0x0000)) -#define DANUBE_LED_CON1 ((volatile u32*)(DANUBE_LED + 0x0004)) -#define DANUBE_LED_CPU0 ((volatile u32*)(DANUBE_LED + 0x0008)) -#define DANUBE_LED_CPU1 ((volatile u32*)(DANUBE_LED + 0x000C)) -#define DANUBE_LED_AR ((volatile u32*)(DANUBE_LED + 0x0010)) - - - - -/***********************************************************************/ -#define DANUBE_REG32(addr) *((volatile u32 *)(addr)) -/***********************************************************************/ -#endif //DANUBE_H diff --git a/package/uboot-ifxmips/files/include/asm-mips/ifx_asc.h b/package/uboot-ifxmips/files/include/asm-mips/ifx_asc.h deleted file mode 100644 index 51abc95..0000000 --- a/package/uboot-ifxmips/files/include/asm-mips/ifx_asc.h +++ /dev/null @@ -1,220 +0,0 @@ -/***************************************************************************** - * DANUBE BootROM - * Copyright (c) 2005, Infineon Technologies AG, All rights reserved - * IFAP DC COM SD - *****************************************************************************/ -#ifndef __ASC_H -#define __ASC_H - -#define DANUBEASC_TXFIFO_FL 1 -#define DANUBEASC_RXFIFO_FL 1 -#define DANUBEASC_TXFIFO_FULL 16 - -/* channel operating modes */ -#define ASCOPT_CSIZE 0x00000003 -#define ASCOPT_CS7 0x00000001 -#define ASCOPT_CS8 0x00000002 -#define ASCOPT_PARENB 0x00000004 -#define ASCOPT_STOPB 0x00000008 -#define ASCOPT_PARODD 0x00000010 -#define ASCOPT_CREAD 0x00000020 - -#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8) - -/* ASC input select (0 or 1) */ -#define CONSOLE_TTY 0 - -#define DANUBEASC_TXFIFO_FL 1 -#define DANUBEASC_RXFIFO_FL 1 -#define DANUBEASC_TXFIFO_FULL 16 - -/* interrupt lines masks for the ASC device interrupts*/ -/* change these macroses if it's necessary */ -#define DANUBEASC_IRQ_LINE_ALL 0x0000007f /* all IRQs */ - -#define DANUBEASC_IRQ_LINE_TIR 0x00000001 /* Tx Int */ -#define DANUBEASC_IRQ_LINE_TBIR 0x00000002 /* Tx Buffer Int */ -#define DANUBEASC_IRQ_LINE_RIR 0x00000004 /* Rx Int */ -#define DANUBEASC_IRQ_LINE_EIR 0x00000008 /* Error Int */ -#define DANUBEASC_IRQ_LINE_ABSTIR 0x00000010 /* Autobaud Start Int */ -#define DANUBEASC_IRQ_LINE_ABDETIP 0x00000020 /* Autobaud Detection Int */ -#define DANUBEASC_IRQ_LINE_SFCIR 0x00000040 /* Software Flow Control Int */ - -/* interrupt controller access macros */ -#define ASC_INTERRUPTS_ENABLE(X) \ -*((volatile unsigned int*) DANUBE_ICU_IM0_IER) |= X; -#define ASC_INTERRUPTS_DISABLE(X) \ -*((volatile unsigned int*) DANUBE_ICU_IM0_IER) &= ~X; -#define ASC_INTERRUPTS_CLEAR(X) \ -*((volatile unsigned int*) DANUBE_ICU_IM0_ISR) = X; - -/* CLC register's bits and bitfields */ -#define ASCCLC_DISR 0x00000001 -#define ASCCLC_DISS 0x00000002 -#define ASCCLC_RMCMASK 0x0000FF00 -#define ASCCLC_RMCOFFSET 8 - -/* CON register's bits and bitfields */ -#define ASCCON_MODEMASK 0x0000000f -#define ASCCON_M_8ASYNC 0x0 -#define ASCCON_M_8IRDA 0x1 -#define ASCCON_M_7ASYNC 0x2 -#define ASCCON_M_7IRDA 0x3 -#define ASCCON_WLSMASK 0x0000000c -#define ASCCON_WLSOFFSET 2 -#define ASCCON_WLS_8BIT 0x0 -#define ASCCON_WLS_7BIT 0x1 -#define ASCCON_PEN 0x00000010 -#define ASCCON_ODD 0x00000020 -#define ASCCON_SP 0x00000040 -#define ASCCON_STP 0x00000080 -#define ASCCON_BRS 0x00000100 -#define ASCCON_FDE 0x00000200 -#define ASCCON_ERRCLK 0x00000400 -#define ASCCON_EMMASK 0x00001800 -#define ASCCON_EMOFFSET 11 -#define ASCCON_EM_ECHO_OFF 0x0 -#define ASCCON_EM_ECHO_AB 0x1 -#define ASCCON_EM_ECHO_ON 0x2 -#define ASCCON_LB 0x00002000 -#define ASCCON_ACO 0x00004000 -#define ASCCON_R 0x00008000 -#define ASCCON_PAL 0x00010000 -#define ASCCON_FEN 0x00020000 -#define ASCCON_RUEN 0x00040000 -#define ASCCON_ROEN 0x00080000 -#define ASCCON_TOEN 0x00100000 -#define ASCCON_BEN 0x00200000 -#define ASCCON_TXINV 0x01000000 -#define ASCCON_RXINV 0x02000000 -#define ASCCON_TXMSB 0x04000000 -#define ASCCON_RXMSB 0x08000000 - -/* STATE register's bits and bitfields */ -#define ASCSTATE_REN 0x00000001 -#define ASCSTATE_PE 0x00010000 -#define ASCSTATE_FE 0x00020000 -#define ASCSTATE_RUE 0x00040000 -#define ASCSTATE_ROE 0x00080000 -#define ASCSTATE_TOE 0x00100000 -#define ASCSTATE_BE 0x00200000 -#define ASCSTATE_TXBVMASK 0x07000000 -#define ASCSTATE_TXBVOFFSET 24 -#define ASCSTATE_TXEOM 0x08000000 -#define ASCSTATE_RXBVMASK 0x70000000 -#define ASCSTATE_RXBVOFFSET 28 -#define ASCSTATE_RXEOM 0x80000000 - -/* WHBSTATE register's bits and bitfields */ -#define ASCWHBSTATE_CLRREN 0x00000001 -#define ASCWHBSTATE_SETREN 0x00000002 -#define ASCWHBSTATE_CLRPE 0x00000004 -#define ASCWHBSTATE_CLRFE 0x00000008 -#define ASCWHBSTATE_CLRRUE 0x00000010 -#define ASCWHBSTATE_CLRROE 0x00000020 -#define ASCWHBSTATE_CLRTOE 0x00000040 -#define ASCWHBSTATE_CLRBE 0x00000080 -#define ASCWHBSTATE_SETPE 0x00000100 -#define ASCWHBSTATE_SETFE 0x00000200 -#define ASCWHBSTATE_SETRUE 0x00000400 -#define ASCWHBSTATE_SETROE 0x00000800 -#define ASCWHBSTATE_SETTOE 0x00001000 -#define ASCWHBSTATE_SETBE 0x00002000 - -/* ABCON register's bits and bitfields */ -#define ASCABCON_ABEN 0x0001 -#define ASCABCON_AUREN 0x0002 -#define ASCABCON_ABSTEN 0x0004 -#define ASCABCON_ABDETEN 0x0008 -#define ASCABCON_FCDETEN 0x0010 - -/* FDV register mask, offset and bitfields*/ -#define ASCFDV_VALUE_MASK 0x000001FF - -/* WHBABCON register's bits and bitfields */ -#define ASCWHBABCON_CLRABEN 0x0001 -#define ASCWHBABCON_SETABEN 0x0002 - -/* ABSTAT register's bits and bitfields */ -#define ASCABSTAT_FCSDET 0x0001 -#define ASCABSTAT_FCCDET 0x0002 -#define ASCABSTAT_SCSDET 0x0004 -#define ASCABSTAT_SCCDET 0x0008 -#define ASCABSTAT_DETWAIT 0x0010 - -/* WHBABSTAT register's bits and bitfields */ -#define ASCWHBABSTAT_CLRFCSDET 0x0001 -#define ASCWHBABSTAT_SETFCSDET 0x0002 -#define ASCWHBABSTAT_CLRFCCDET 0x0004 -#define ASCWHBABSTAT_SETFCCDET 0x0008 -#define ASCWHBABSTAT_CLRSCSDET 0x0010 -#define ASCWHBABSTAT_SETSCSDET 0x0020 -#define ASCWHBABSTAT_CLRSCCDET 0x0040 -#define ASCWHBABSTAT_SETSCCDET 0x0080 -#define ASCWHBABSTAT_CLRDETWAIT 0x0100 -#define ASCWHBABSTAT_SETDETWAIT 0x0200 - -/* TXFCON register's bits and bitfields */ -#define ASCTXFCON_TXFIFO1 0x00000400 -#define ASCTXFCON_TXFEN 0x0001 -#define ASCTXFCON_TXFFLU 0x0002 -#define ASCTXFCON_TXFITLMASK 0x3F00 -#define ASCTXFCON_TXFITLOFF 8 - -/* RXFCON register's bits and bitfields */ -#define ASCRXFCON_RXFIFO1 0x00000400 -#define ASCRXFCON_RXFEN 0x0001 -#define ASCRXFCON_RXFFLU 0x0002 -#define ASCRXFCON_RXFITLMASK 0x3F00 -#define ASCRXFCON_RXFITLOFF 8 - -/* FSTAT register's bits and bitfields */ -#define ASCFSTAT_RXFFLMASK 0x003F -#define ASCFSTAT_TXFFLMASK 0x3F00 -#define ASCFSTAT_TXFFLOFF 8 - -typedef struct /* DanubeAsc_t */ -{ - volatile unsigned long asc_clc; /*0x0000*/ - volatile unsigned long asc_pisel; /*0x0004*/ - volatile unsigned long asc_id; /*0x0008*/ - volatile unsigned long asc_rsvd1[1]; /* for mapping */ /*0x000C*/ - volatile unsigned long asc_con; /*0x0010*/ - volatile unsigned long asc_state; /*0x0014*/ - volatile unsigned long asc_whbstate; /*0x0018*/ - volatile unsigned long asc_rsvd2[1]; /* for mapping */ /*0x001C*/ - volatile unsigned long asc_tbuf; /*0x0020*/ - volatile unsigned long asc_rbuf; /*0x0024*/ - volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0028*/ - volatile unsigned long asc_abcon; /*0x0030*/ - volatile unsigned long asc_abstat; /* not used */ /*0x0034*/ - volatile unsigned long asc_whbabcon; /*0x0038*/ - volatile unsigned long asc_whbabstat; /* not used */ /*0x003C*/ - volatile unsigned long asc_rxfcon; /*0x0040*/ - volatile unsigned long asc_txfcon; /*0x0044*/ - volatile unsigned long asc_fstat; /*0x0048*/ - volatile unsigned long asc_rsvd4[1]; /* for mapping */ /*0x004C*/ - volatile unsigned long asc_bg; /*0x0050*/ - volatile unsigned long asc_bg_timer; /*0x0054*/ - volatile unsigned long asc_fdv; /*0x0058*/ - volatile unsigned long asc_pmw; /*0x005C*/ - volatile unsigned long asc_modcon; /*0x0060*/ - volatile unsigned long asc_modstat; /*0x0064*/ - volatile unsigned long asc_rsvd5[2]; /* for mapping */ /*0x0068*/ - volatile unsigned long asc_sfcc; /*0x0070*/ - volatile unsigned long asc_rsvd6[3]; /* for mapping */ /*0x0074*/ - volatile unsigned long asc_eomcon; /*0x0080*/ - volatile unsigned long asc_rsvd7[26]; /* for mapping */ /*0x0084*/ - volatile unsigned long asc_dmacon; /*0x00EC*/ - volatile unsigned long asc_rsvd8[1]; /* for mapping */ /*0x00F0*/ - volatile unsigned long asc_irnen; /*0x00F4*/ - volatile unsigned long asc_irnicr; /*0x00F8*/ - volatile unsigned long asc_irncr; /*0x00FC*/ -} DanubeAsc_t; - -int asc_init (void); -void asc_puts (const char *s); -void asc_putc (const char c); -int asc_getc (void); - -#endif /* __ASC_H */ diff --git a/package/uboot-ifxmips/files/include/asm-mips/inca-ip2.h b/package/uboot-ifxmips/files/include/asm-mips/inca-ip2.h deleted file mode 100644 index 19c8ceb..0000000 --- a/package/uboot-ifxmips/files/include/asm-mips/inca-ip2.h +++ /dev/null @@ -1,634 +0,0 @@ -/************************************************************************ - * - * Copyright (c) 2005 - * Infineon Technologies AG - * St. Martin Strasse 53; 81669 Muenchen; Germany - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - * - ************************************************************************/ - -/***********************************************************************/ -/* Module : DMA register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_DMA (KSEG1+0x14101000) -/***********************************************************************/ -#define CONFIGURATION_REGISTERS_CLC (INCA_IP2_DMA + 0x00) -#define CONFIGURATION_REGISTERS_ID (INCA_IP2_DMA + 0x08) -#define GENERAL_REGISTERS_DMA_CTRL (INCA_IP2_DMA + 0x10) -#define CHANNEL_RELATED_REGISTERS_DMA_CS (INCA_IP2_DMA + 0x18) -#define CHANNEL_RELATED_REGISTERS_DMA_CCTRL (INCA_IP2_DMA + 0x1C) -#define CHANNEL_RELATED_REGISTERS_DMA_CDBA (INCA_IP2_DMA + 0x20) -#define CHANNEL_RELATED_REGISTERS_DMA_CDLEN (INCA_IP2_DMA + 0x24) -#define CHANNEL_RELATED_REGISTERS_DMA_CIE (INCA_IP2_DMA + 0x2C) -#define CHANNEL_RELATED_REGISTERS_DMA_CIS (INCA_IP2_DMA + 0x28) -#define CHANNEL_RELATED_REGISTERS_DMA_CPOLL (INCA_IP2_DMA + 0x14) - -#define PORT_RELATED_REGISTERS_DMA_PS (INCA_IP2_DMA + 0x40) -#define PORT_RELATED_REGISTERS_DMA_PCTRL (INCA_IP2_DMA + 0x44) - -#define INTERRUPT_NODE_REGISTERS_DMA_IRNEN (INCA_IP2_DMA + 0xF4) -#define INTERRUPT_NODE_REGISTERS_DMA_IRNCR (INCA_IP2_DMA + 0xF8) -#define INTERRUPT_NODE_REGISTERS_DMA_IRNICR (INCA_IP2_DMA + 0xFC) - -#if 0 -/* ISR */ -#define DMA_ISR_RDERR 0x20 -#define DMA_ISR_CMDCPT 0x10 -#define DMA_ISR_CPT 0x8 -#define DMA_ISR_DURR 0x4 -#define DMA_ISR_EOP 0x2 -#endif -#define DMA_RESET_CHANNEL 0x00000002 -#define DMA_ENABLE_CHANNEL 0x00000001 -#define DMA_DESC_BYTEOFF_SHIFT 22 - -#define DMA_POLLING_ENABLE 0x80000000 -#define DMA_POLLING_CNT 0x50 /*minimum 0x10, max 0xfff0*/ - -/***********************************************************************/ -/* Module : ICU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_ICU (KSEG1+0x1F880200) -/***********************************************************************/ - -#define INCA_IP2_ICU_IM0_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0000)) -#define INCA_IP2_ICU_IM0_IER ((volatile u32*)(INCA_IP2_ICU + 0x0008)) -#define INCA_IP2_ICU_IM0_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0010)) -#define INCA_IP2_ICU_IM0_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0018)) -#define INCA_IP2_ICU_IM0_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0020)) -#define INCA_IP2_ICU_IM0_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM0_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM1_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0028)) -#define INCA_IP2_ICU_IM1_IER ((volatile u32*)(INCA_IP2_ICU + 0x0030)) -#define INCA_IP2_ICU_IM1_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0038)) -#define INCA_IP2_ICU_IM1_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0040)) -#define INCA_IP2_ICU_IM1_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0048)) -#define INCA_IP2_ICU_IM1_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM1_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM2_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0050)) -#define INCA_IP2_ICU_IM2_IER ((volatile u32*)(INCA_IP2_ICU + 0x0058)) -#define INCA_IP2_ICU_IM2_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0060)) -#define INCA_IP2_ICU_IM2_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0068)) -#define INCA_IP2_ICU_IM2_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0070)) -#define INCA_IP2_ICU_IM2_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM2_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM3_ISR ((volatile u32*)(INCA_IP2_ICU + 0x0078)) -#define INCA_IP2_ICU_IM3_IER ((volatile u32*)(INCA_IP2_ICU + 0x0080)) -#define INCA_IP2_ICU_IM3_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x0088)) -#define INCA_IP2_ICU_IM3_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x0090)) -#define INCA_IP2_ICU_IM3_IMR ((volatile u32*)(INCA_IP2_ICU + 0x0098)) -#define INCA_IP2_ICU_IM3_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM3_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM4_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00A0)) -#define INCA_IP2_ICU_IM4_IER ((volatile u32*)(INCA_IP2_ICU + 0x00A8)) -#define INCA_IP2_ICU_IM4_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00B0)) -#define INCA_IP2_ICU_IM4_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00B8)) -#define INCA_IP2_ICU_IM4_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00C0)) -#define INCA_IP2_ICU_IM4_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM4_IR(value) (1 << (value)) - -#define INCA_IP2_ICU_IM5_ISR ((volatile u32*)(INCA_IP2_ICU + 0x00C8)) -#define INCA_IP2_ICU_IM5_IER ((volatile u32*)(INCA_IP2_ICU + 0x00D0)) -#define INCA_IP2_ICU_IM5_IOSR ((volatile u32*)(INCA_IP2_ICU + 0x00D8)) -#define INCA_IP2_ICU_IM5_IRSR ((volatile u32*)(INCA_IP2_ICU + 0x00E0)) -#define INCA_IP2_ICU_IM5_IMR ((volatile u32*)(INCA_IP2_ICU + 0x00E8)) -#define INCA_IP2_ICU_IM5_IMR_IID (1 << 31) -#define INCA_IP2_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -#define INCA_IP2_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -#define INCA_IP2_ICU_IM5_IR(value) (1 << (value)) - - -/***********************************************************************/ -/* Module : CGU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_CGU (KSEG1+0x1F100800) -/***********************************************************************/ - -#define INCA_IP2_CGU_PLL2CR ((volatile u32*)(INCA_IP2_CGU + 0x0008)) -#define INCA_IP2_CGU_FBSCR ((volatile u32*)(INCA_IP2_CGU + 0x0018)) -#define INCA_IP2_CGU_FBSCR_LPBSDIV_GET(value) (((value) >> 6) & ((1 << 2) - 1)) -#define INCA_IP2_CGU_FBSCR_DIV0_GET(value) (((value) >> 0) & ((1 << 3) - 1)) -#define INCA_IP2_CGU_FBSCR_DIV1_GET(value) (((value) >> 4) & ((1 << 2) - 1)) - -/***********************************************************************/ -/* Module : MPS register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_MPS (KSEG1+0x1F101400) -/***********************************************************************/ - -#define INCA_IP2_MPS_CHIPID ((volatile u32*)(INCA_IP2_MPS + 0x0344)) -#define INCA_IP2_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -#define INCA_IP2_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -#define INCA_IP2_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -#define INCA_IP2_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -#define INCA_IP2_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -#define INCA_IP2_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) - - -/* voice channel 0 ... 3 interrupt enable register */ -#define INCA_IP2_MPS_VC0ENR ((volatile u32*)(INCA_IP2_MPS + 0x0000)) -#define INCA_IP2_MPS_VC1ENR ((volatile u32*)(INCA_IP2_MPS + 0x0004)) -#define INCA_IP2_MPS_VC2ENR ((volatile u32*)(INCA_IP2_MPS + 0x0008)) -#define INCA_IP2_MPS_VC3ENR ((volatile u32*)(INCA_IP2_MPS + 0x000C)) -/* voice channel 0 ... 3 interrupt status read register */ -#define INCA_IP2_MPS_RVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0010)) -#define INCA_IP2_MPS_RVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0014)) -#define INCA_IP2_MPS_RVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0018)) -#define INCA_IP2_MPS_RVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x001C)) -/* voice channel 0 ... 3 interrupt status set register */ -#define INCA_IP2_MPS_SVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0020)) -#define INCA_IP2_MPS_SVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0024)) -#define INCA_IP2_MPS_SVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0028)) -#define INCA_IP2_MPS_SVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x002C)) -/* voice channel 0 ... 3 interrupt status clear register */ -#define INCA_IP2_MPS_CVC0SR ((volatile u32*)(INCA_IP2_MPS + 0x0030)) -#define INCA_IP2_MPS_CVC1SR ((volatile u32*)(INCA_IP2_MPS + 0x0034)) -#define INCA_IP2_MPS_CVC2SR ((volatile u32*)(INCA_IP2_MPS + 0x0038)) -#define INCA_IP2_MPS_CVC3SR ((volatile u32*)(INCA_IP2_MPS + 0x003C)) -/* common status 0 and 1 read register */ -#define INCA_IP2_MPS_RAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0040)) -#define INCA_IP2_MPS_RAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0044)) -/* common status 0 and 1 set register */ -#define INCA_IP2_MPS_SAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0048)) -#define INCA_IP2_MPS_SAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x004C)) -/* common status 0 and 1 clear register */ -#define INCA_IP2_MPS_CAD0SR ((volatile u32*)(INCA_IP2_MPS + 0x0050)) -#define INCA_IP2_MPS_CAD1SR ((volatile u32*)(INCA_IP2_MPS + 0x0054)) -/* notification enable register */ -#define INCA_IP2_MPS_CPU0_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0060)) -#define INCA_IP2_MPS_CPU1_NFER ((volatile u32*)(INCA_IP2_MPS + 0x0064)) -/* CPU to CPU interrup request register */ -#define INCA_IP2_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(INCA_IP2_MPS + 0x0070)) -#define INCA_IP2_MPS_CPU0_2_CPU1_IER ((volatile u32*)(INCA_IP2_MPS + 0x0074)) -/* Global interrupt request and request enable register */ -#define INCA_IP2_MPS_GIRR ((volatile u32*)(INCA_IP2_MPS + 0x0078)) -#define INCA_IP2_MPS_GIER ((volatile u32*)(INCA_IP2_MPS + 0x007C)) - -/* Addresses of enable registers not yet defined -#define INCA_IP2_MPS_AD0ENR ((volatile u32*)(INCA_IP2_MPS + 0x????)) -#define INCA_IP2_MPS_AD1ENR ((volatile u32*)(INCA_IP2_MPS + 0x????)) -*/ - - -/***********************************************************************/ -/* Module : ASC0 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_ASC0 (KSEG1+0x1E000400) -/***********************************************************************/ - -#define INCA_IP2_ASC0_TBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0020)) -#define INCA_IP2_ASC0_RBUF ((volatile u32*)(INCA_IP2_ASC0 + 0x0024)) -#define INCA_IP2_ASC0_FSTAT ((volatile u32*)(INCA_IP2_ASC0 + 0x0048)) -#define INCA_IP2_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define INCA_IP2_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP2_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP2_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define INCA_IP2_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : ASC1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_ASC1 (KSEG1+0x1E000800) -/***********************************************************************/ - -#define INCA_IP2_ASC1_TBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0020)) -#define INCA_IP2_ASC1_RBUF ((volatile u32*)(INCA_IP2_ASC1 + 0x0024)) -#define INCA_IP2_ASC1_FSTAT ((volatile u32*)(INCA_IP2_ASC1 + 0x0048)) -#define INCA_IP2_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -#define INCA_IP2_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -#define INCA_IP2_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -#define INCA_IP2_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -#define INCA_IP2_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_RCU (KSEG1+0x1E001C00) -/***********************************************************************/ - -/***Reset Request Register***/ -#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000)) -#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31) -#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30) -#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29) -#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28) -#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27) -#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26) -#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) -#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) -#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22) -#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21) -#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20) -#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19) -#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18) - -/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000 - -/***NMI Status Register***/ -#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4)) -#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2) -#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1) -#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0) - - -/***********************************************************************/ -/* Module : WDT register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_WDT (KSEG1+0x1F880000) -/***********************************************************************/ - -/***Watchdog Timer Control Register ***/ -#define INCA_IP2_WDT_BIU_WDT_CR ((volatile u32*)(INCA_IP2_WDT + 0x03F0)) -#define INCA_IP2_WDT_BIU_WDT_CR_GEN (1 << 31) -#define INCA_IP2_WDT_BIU_WDT_CR_DSEN (1 << 30) -#define INCA_IP2_WDT_BIU_WDT_CR_LPEN (1 << 29) -#define INCA_IP2_WDT_BIU_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -#define INCA_IP2_WDT_BIU_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -#define INCA_IP2_WDT_BIU_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) - -/***Watchdog Timer Status Register***/ -#define INCA_IP2_WDT_BIU_WDT_SR ((volatile u32*)(INCA_IP2_WDT + 0x03F8)) -#define INCA_IP2_WDT_BIU_WDT_SR_EN (1 << 31) -#define INCA_IP2_WDT_BIU_WDT_SR_AE (1 << 30) -#define INCA_IP2_WDT_BIU_WDT_SR_PRW (1 << 29) -#define INCA_IP2_WDT_BIU_WDT_SR_EXP (1 << 28) -#define INCA_IP2_WDT_BIU_WDT_SR_PWD (1 << 27) -#define INCA_IP2_WDT_BIU_WDT_SR_DS (1 << 26) -#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -#define INCA_IP2_WDT_BIU_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) - - -/***********************************************************************/ -/* Module : BCU0 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_BCU0 (KSEG1+0x14100000) -/***********************************************************************/ - -#define INCA_IP2_BCU0_CON ((volatile u32*)(INCA_IP2_BCU0 + 0x0010)) -#define INCA_IP2_BCU0_ECON ((volatile u32*)(INCA_IP2_BCU0 + 0x0020)) -#define INCA_IP2_BCU0_EADD ((volatile u32*)(INCA_IP2_BCU0 + 0x0024)) -#define INCA_IP2_BCU0_EDAT ((volatile u32*)(INCA_IP2_BCU0 + 0x0028)) -#define INCA_IP2_BCU0_IRNCR1 ((volatile u32*)(INCA_IP2_BCU0 + 0x00F8)) -#define INCA_IP2_BCU0_IRNCR0 ((volatile u32*)(INCA_IP2_BCU0 + 0x00FC)) - - -/***********************************************************************/ -/* Module : BCU1 register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_BCU1 (KSEG1+0x1E000000) -/***********************************************************************/ - -#define INCA_IP2_BCU1_CON ((volatile u32*)(INCA_IP2_BCU1 + 0x0010)) -#define INCA_IP2_BCU1_ECON ((volatile u32*)(INCA_IP2_BCU1 + 0x0020)) -#define INCA_IP2_BCU1_EADD ((volatile u32*)(INCA_IP2_BCU1 + 0x0024)) -#define INCA_IP2_BCU1_EDAT ((volatile u32*)(INCA_IP2_BCU1 + 0x0028)) -#define INCA_IP2_BCU1_IRNCR1 ((volatile u32*)(INCA_IP2_BCU1 + 0x00F8)) -#define INCA_IP2_BCU1_IRNCR0 ((volatile u32*)(INCA_IP2_BCU1 + 0x00FC)) - - -/***********************************************************************/ -/* Module : MC register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_MC (KSEG1+0x1F800000) -/***********************************************************************/ - -#define INCA_IP2_MC_ERRCAUSE ((volatile u32*)(INCA_IP2_MC + 0x0010)) -#define INCA_IP2_MC_ERRADDR ((volatile u32*)(INCA_IP2_MC + 0x0020)) -#define INCA_IP2_MC_CON ((volatile u32*)(INCA_IP2_MC + 0x0060)) - -/***********************************************************************/ -/* Module : MC SDRAM register address and bits */ -/***********************************************************************/ -#define INCA_IP2_SDRAM (KSEG1+0x1F800200) -/***********************************************************************/ -#define INCA_IP2_SDRAM_MC_CFGPB0 ((volatile u32*)(INCA_IP2_SDRAM + 0x0040)) - -/***********************************************************************/ -/* Module : MC DDR register address and bits */ -/***********************************************************************/ -#define INCA_IP2_DDR (KSEG1+0x1F801000) -/***********************************************************************/ -#define INCA_IP2_DDR_MC_DC19 ((volatile u32*)(INCA_IP2_DDR + 0x0130)) -#define INCA_IP2_DDR_MC_DC20 ((volatile u32*)(INCA_IP2_DDR + 0x0140)) - - -/***********************************************************************/ -/* Module : PMS register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_PMS (KSEG1 + 0x1F100C00) - -#define INCA_IP2_PMS_PMS_SR ((volatile u32*) (INCA_IP2_PMS + 0x0000)) -#define INCA_IP2_PMS_PMS_SR_ASC1 (1 << 14) -#define INCA_IP2_PMS_PMS_SR_ASC0 (1 << 13) -#define INCA_IP2_PMS_PMS_GEN ((volatile u32*) (INCA_IP2_PMS + 0x0004)) -#define INCA_IP2_PMS_PMS_GEN_DMA (1 << 16) -#define INCA_IP2_PMS_PMS_GEN_ASC1 (1 << 14) -#define INCA_IP2_PMS_PMS_GEN_ASC0 (1 << 13) -#define INCA_IP2_PMS_PMS_GEN_SPI0 (1 << 11) -#define INCA_IP2_PMS_PMS_GEN_SPI1 (1 << 12) -#define INCA_IP2_PMS_PMS_CFG ((volatile u32*) (INCA_IP2_PMS + 0x0008)) - - -/***********************************************************************/ -/* Module : GPIO register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_GPIO (KSEG1 + 0x1F102600) - -#define INCA_IP2_GPIO_OUT ((volatile u32*) (INCA_IP2_GPIO + 0x0000)) -#define INCA_IP2_GPIO_IN ((volatile u32*) (INCA_IP2_GPIO + 0x0004)) -#define INCA_IP2_GPIO_DIR ((volatile u32*) (INCA_IP2_GPIO + 0x0008)) -#define INCA_IP2_GPIO_ALTSEL1 ((volatile u32*) (INCA_IP2_GPIO + 0x000C)) -#define INCA_IP2_GPIO_ALTSEL2 ((volatile u32*) (INCA_IP2_GPIO + 0x0010)) -#define INCA_IP2_GPIO_STOFF ((volatile u32*) (INCA_IP2_GPIO + 0x0014)) -#define INCA_IP2_GPIO_OD ((volatile u32*) (INCA_IP2_GPIO + 0x0018)) -#define INCA_IP2_GPIO_PUDEB ((volatile u32*) (INCA_IP2_GPIO + 0x001C)) - -/***********************************************************************/ -/* Module : RCU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_RCU (KSEG1+0x1E001C00) -/***********************************************************************/ - -/***Reset Request Register***/ -#define INCA_IP2_RCU_RST_REQ ((volatile u32*)(INCA_IP2_RCU + 0x0000)) -#define INCA_IP2_RCU_RST_REQ_CPU0 (1 << 31) -#define INCA_IP2_RCU_RST_REQ_CPU1 (1 << 30) -#define INCA_IP2_RCU_RST_REQ_CPUSUB (1 << 29) -#define INCA_IP2_RCU_RST_REQ_HRST (1 << 28) -#define INCA_IP2_RCU_RST_REQ_WDT0 (1 << 27) -#define INCA_IP2_RCU_RST_REQ_WDT1 (1 << 26) -#define INCA_IP2_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) -#define INCA_IP2_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) -#define INCA_IP2_RCU_RST_REQ_SWTBOOT (1 << 22) -#define INCA_IP2_RCU_RST_REQ_DMA (1 << 21) -#define INCA_IP2_RCU_RST_REQ_ETHPHY1 (1 << 20) -#define INCA_IP2_RCU_RST_REQ_ETHPHY0 (1 << 19) -#define INCA_IP2_RCU_RST_REQ_CPU0_BR (1 << 18) - -/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -#define INCA_IP2_RCU_RST_REQ_ALL 0xFC380000 - -/***Reset Status Register***/ -#define INCA_IP2_RCU_SR ((volatile u32*)(INCA_IP2_RCU + 0x0008)) - -/***NMI Status Register***/ -#define INCA_IP2_RCU_NMISR ((volatile u32*)(INCA_IP2_RCU + 0x00F4)) -#define INCA_IP2_RCU_NMISR_NMIEXT (1 << 2) -#define INCA_IP2_RCU_NMISR_NMIPLL2 (1 << 1) -#define INCA_IP2_RCU_NMISR_NMIPLL1 (1 << 0) - -/***********************************************************************/ -/* Module : EBU register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_EBU (KSEG1+0x14102000) -/***********************************************************************/ - -#define INCA_IP2_EBU_ADDSEL0 ((volatile u32*)(INCA_IP2_EBU + 0x0020)) -#define INCA_IP2_EBU_ADDSEL1 ((volatile u32*)(INCA_IP2_EBU + 0x0024)) -#define INCA_IP2_EBU_ADDSEL2 ((volatile u32*)(INCA_IP2_EBU + 0x0028)) -#define INCA_IP2_EBU_ADDSEL3 ((volatile u32*)(INCA_IP2_EBU + 0x002C)) -#define INCA_IP2_EBU_CON0 ((volatile u32*)(INCA_IP2_EBU + 0x0060)) -#define INCA_IP2_EBU_CON1 ((volatile u32*)(INCA_IP2_EBU + 0x0064)) -#define INCA_IP2_EBU_CON2 ((volatile u32*)(INCA_IP2_EBU + 0x0068)) -#define INCA_IP2_EBU_CON3 ((volatile u32*)(INCA_IP2_EBU + 0x006C)) -#define INCA_IP2_EBU_CON_WRDIS (1 << 31) - - - - -/***********************************************************************/ -/* Module : SWITCH register address and bits */ -/***********************************************************************/ - -#define INCA_IP2_SWITCH (KSEG1+0x18000000) -/***********************************************************************/ - -/* PR Base address */ -#define PR_BASE (INCA_IP2_SWITCH + 0x00008000) - -/* SE Base Address */ -#define SE_BASE (INCA_IP2_SWITCH + 0x00009000) - -#define PR_CTRL_REG (PR_BASE + 0x0000) -#define MA_LEARN_REG (PR_BASE + 0x0004) -#define DST_LOOKUP_REG (PR_BASE + 0x0008) - -#define COS_SEL_REG (PR_BASE + 0x000c) -#define PRI2_COS_REG (PR_BASE + 0x0010) -#define UNKNOWN_DEST_REG (PR_BASE + 0x0014) - -#define CPU_ACS_CTRL_REG (PR_BASE + 0x0018) -#define CPU_ACS_DATA_REG (PR_BASE + 0x001c) - -#define MA_READ_REG (PR_BASE + 0x0020) -#define TB_CTRL_REG (PR_BASE + 0x0024) -#define RATE_REG (PR_BASE + 0x0028) -#define BURST_REG (PR_BASE + 0x0048) -#define EBURST_REG (PR_BASE + 0x0068) - -#define RULE_SEL_REG (PR_BASE + 0x0088) - -#define GEN_SFT_AGE_STB (PR_BASE + 0x008C) -#define PR_ISR_REG (PR_BASE + 0x0090) -#define PR_IMR_REG (PR_BASE + 0x0094) -#define PR_IPR_REG (PR_BASE + 0x0098) -#define BPDU_REG (PR_BASE + 0x00A4) - -/* Switching Engine Register Description */ -#define QLL_CMD_REG (SE_BASE) -#define QLL_DATA_REG0 (SE_BASE + 0x0004) -#define QLL_DATA_REG1 (SE_BASE + 0x0008) - -#define VLAN_MIBS_CMD_REG (SE_BASE + 0x000c) -#define VLAN_MIBS_DATA_REG (SE_BASE + 0x0010) - -#define SD_CMD_REG (SE_BASE + 0x0014) -#define SD_DATA_REGS0 (SE_BASE + 0x0018) -#define SD_DATA_REGS1 (SE_BASE + 0x001C) -#define SD_DATA_REGS2 (SE_BASE + 0x0020) - -#define VLAN_TBL_CMD_REG (SE_BASE + 0x0024) -#define VLAN_TBL_DATA_REG (SE_BASE + 0x0028) - -#define FD_TBL_CMD_REG (SE_BASE + 0x002c) -#define FD_TBL_DATA_REG (SE_BASE + 0x0030) - -#define SYMM_VLAN_REG (SE_BASE + 0x0038) -#define PORT_AUTH (SE_BASE + 0x0048) -#define CPU_LINK_OK_REG (SE_BASE + 0x0050) -/* #define TRUNK_CTRL_REGS (SE_BASE + 0x0054) */ -#define MIRROR_PORT_REG (SE_BASE + 0x0064) - -#define ST_PT_REG (SE_BASE + 0x0068) -#define JUMBO_ENABLE_REG (SE_BASE + 0x006C) -#define STACK_PORT_REG (SE_BASE + 0x0074) -#define EG_MON_REG (SE_BASE + 0x007C) -#define VR_MIB_REG (SE_BASE + 0x0080) -#define QUEUE_CMD_REGS (SE_BASE + 0x0090) - -#define GLOBAL_RX_WM_REG (SE_BASE + 0x0200) -#define PORT0_RX_WM_REG0 (SE_BASE + 0x0204) -#define PORT1_RX_WM_REG0 (SE_BASE + 0x0208) -#define PORT2_RX_WM_REG0 (SE_BASE + 0x020C) - -#define PORT_RX_WM_REGS (SE_BASE + 0x0200) -#define PORT_TX_WM_REGS (SE_BASE + 0x0300) -#define PORT0_TX_WM_REG0 (SE_BASE + 0x0330) -#define PORT1_TX_WM_REG0 (SE_BASE + 0x0338) -#define PORT2_TX_WM_REG0 (SE_BASE + 0x0340) -#define PORT0_TX_WM_REG1 (SE_BASE + 0x0334) -#define PORT1_TX_WM_REG1 (SE_BASE + 0x033C) -#define PORT2_TX_WM_REG1 (SE_BASE + 0x0344) - - -#define QUEUE_STATUS_REGS (SE_BASE + 0x0400) - -#define SE_INT_STS_REG (SE_BASE + 0x08e0) -#define SE_INT_MSK_REG_RD (SE_BASE + 0x08e4) -#define SE_INT_MSK_REG_WR (SE_BASE + 0x08e8) -#define SE_INT_PRI_REG_RD (SE_BASE + 0x08ec) -#define SE_INT_PRI_REG_WR (SE_BASE + 0x08f0) /* address too be defined*/ - -/***********************************************************************/ -/* Module : Ethernet Switch port related addresses and bits */ -/***********************************************************************/ -#define GPORT0_BASE (KSEG1+0x18006000) -#define GPORT1_BASE (KSEG1+0x18007000) -#define GPORT2_BASE (KSEG1+0x1800C000) - -#define PORTREG_BASE GPORT0_BASE - -#define SWITCH_P0_GMAC_REG (GPORT0_BASE + 0x0004) -#define SWITCH_P0_GMAC_CTRL (GPORT0_BASE + 0x000C) -#define SWITCH_P0_RTX_INT_STATUS (GPORT0_BASE + 0x0010) -#define SWITCH_P0_RTX_INT_MASK (GPORT0_BASE + 0x0014) -#define SWITCH_P0_INT_PRIORITY (GPORT0_BASE + 0x0018) -#define SWITCH_P0_RX_CONF (GPORT0_BASE + 0x0400) -#define SWITCH_P0_OFFSET0_REG (GPORT0_BASE + 0x0404) -#define SWITCH_P0_OFFSET1_REG (GPORT0_BASE + 0x0408) -#define SWITCH_P0_PORT_MASK0_REG (GPORT0_BASE + 0x0420) -#define SWITCH_P0_PORT_MASK1_REG (GPORT0_BASE + 0x0424) -#define SWITCH_P0_PORT_MASK2_REG (GPORT0_BASE + 0x0428) -#define SWITCH_P0_PORT_MASK3_REG (GPORT0_BASE + 0x042C) -#define SWITCH_P0_PORT_RULE0_REG (GPORT0_BASE + 0x0430) -#define SWITCH_P0_PORT_RULE1_REG (GPORT0_BASE + 0x0434) -#define SWITCH_P0_PORT_RULE2_REG (GPORT0_BASE + 0x0438) -#define SWITCH_P0_PORT_RULE3_REG (GPORT0_BASE + 0x043C) -#define SWITCH_P0_PORT_IKEY_SEL (GPORT0_BASE + 0x0440) -#define SWITCH_P0_PORT_RX_VLAN_ID (GPORT0_BASE + 0x0450) -#define SWITCH_P0_TX_CONF (GPORT0_BASE + 0x0800) -#define SWITCH_P0_PORT_TX_VLAN_ID (GPORT0_BASE + 0x0804) -#define SWITCH_P0_PORT_MIB_REG_0 (GPORT0_BASE + 0x0C00) -#define SWITCH_P0_GMAC_MIB_REG_0 (GPORT0_BASE + 0x0C54) - -#define SWITCH_P1_GMAC_REG (GPORT1_BASE + 0x0004) -#define SWITCH_P1_GMAC_CTRL (GPORT1_BASE + 0x000C) -#define SWITCH_P1_RTX_INT_STATUS (GPORT1_BASE + 0x0010) -#define SWITCH_P1_RTX_INT_MASK (GPORT1_BASE + 0x0014) -#define SWITCH_P1_INT_PRIORITY (GPORT1_BASE + 0x0018) -#define SWITCH_P1_RX_CONF (GPORT1_BASE + 0x0400) -#define SWITCH_P1_OFFSET0_REG (GPORT1_BASE + 0x0404) -#define SWITCH_P1_OFFSET1_REG (GPORT1_BASE + 0x0408) -#define SWITCH_P1_PORT_MASK0_REG (GPORT1_BASE + 0x0420) -#define SWITCH_P1_PORT_MASK1_REG (GPORT1_BASE + 0x0424) -#define SWITCH_P1_PORT_MASK2_REG (GPORT1_BASE + 0x0428) -#define SWITCH_P1_PORT_MASK3_REG (GPORT1_BASE + 0x042C) -#define SWITCH_P1_PORT_RULE0_REG (GPORT1_BASE + 0x0430) -#define SWITCH_P1_PORT_RULE1_REG (GPORT1_BASE + 0x0434) -#define SWITCH_P1_PORT_RULE2_REG (GPORT1_BASE + 0x0438) -#define SWITCH_P1_PORT_RULE3_REG (GPORT1_BASE + 0x043C) -#define SWITCH_P1_PORT_IKEY_SEL (GPORT1_BASE + 0x0440) -#define SWITCH_P1_PORT_RX_VLAN_ID (GPORT1_BASE + 0x0450) -#define SWITCH_P1_TX_CONF (GPORT1_BASE + 0x0800) -#define SWITCH_P1_PORT_TX_VLAN_ID (GPORT1_BASE + 0x0804) -#define SWITCH_P1_PORT_MIB_REG_0 (GPORT1_BASE + 0x0C00) -#define SWITCH_P1_GMAC_MIB_REG_0 (GPORT1_BASE + 0x0C54) - -#define SWITCH_P2_GMAC_REG (GPORT2_BASE + 0x0004) -#define SWITCH_P2_GMAC_CTRL (GPORT2_BASE + 0x000C) -#define SWITCH_P2_RTX_INT_STATUS (GPORT2_BASE + 0x0010) -#define SWITCH_P2_RTX_INT_MASK (GPORT2_BASE + 0x0014) -#define SWITCH_P2_INT_PRIORITY (GPORT2_BASE + 0x0018) -#define SWITCH_P2_MDIO_ID_1 (GPORT2_BASE + 0x00A8) -#define SWITCH_P2_PAUSE_CTL_1 (GPORT2_BASE + 0x00B0) -#define SWITCH_P2_MDIO_MOD_SEL (GPORT2_BASE + 0x00B4) -#define SWITCH_P2_MDIO_ACC_0 (GPORT2_BASE + 0x00B8) -#define SWITCH_P2_RX_CONF (GPORT2_BASE + 0x0400) -#define SWITCH_P2_OFFSET0_REG (GPORT2_BASE + 0x0404) -#define SWITCH_P2_OFFSET1_REG (GPORT2_BASE + 0x0408) -#define SWITCH_P2_PORT_MASK0_REG (GPORT2_BASE + 0x0420) -#define SWITCH_P2_PORT_MASK1_REG (GPORT2_BASE + 0x0424) -#define SWITCH_P2_PORT_MASK2_REG (GPORT2_BASE + 0x0428) -#define SWITCH_P2_PORT_MASK3_REG (GPORT2_BASE + 0x042C) -#define SWITCH_P2_PORT_RULE0_REG (GPORT2_BASE + 0x0430) -#define SWITCH_P2_PORT_RULE1_REG (GPORT2_BASE + 0x0434) -#define SWITCH_P2_PORT_RULE2_REG (GPORT2_BASE + 0x0438) -#define SWITCH_P2_PORT_RULE3_REG (GPORT2_BASE + 0x043C) -#define SWITCH_P2_PORT_IKEY_SEL (GPORT2_BASE + 0x0440) -#define SWITCH_P2_PORT_RX_VLAN_ID (GPORT2_BASE + 0x0450) -#define SWITCH_P2_TX_CONF (GPORT2_BASE + 0x0800) -#define SWITCH_P2_PORT_TX_VLAN_ID (GPORT2_BASE + 0x0804) -#define SWITCH_P2_PORT_MIB_REG_0 (GPORT2_BASE + 0x0C00) -#define SWITCH_P2_GMAC_MIB_REG_0 (GPORT2_BASE + 0x0C54) - -#define MDIO_MOD_SEL SWITCH_P2_MDIO_MOD_SEL -#define SWITCH_MDIO_ACC SWITCH_P2_MDIO_ACC_0 -#define SWITCH_MDIO_ID SWITCH_P2_MDIO_ID_1 -/* #define TX_CONFIG_REG SWITCH_P0_TX_CONF */ - -#define SWITCH_PMAC_HD_CTL (GPORT2_BASE + 0x0070) -#define SWITCH_PMAC_SA1 (GPORT2_BASE + 0x0074) -#define SWITCH_PMAC_SA2 (GPORT2_BASE + 0x0078) -#define SWITCH_PMAC_DA1 (GPORT2_BASE + 0x007C) -#define SWITCH_PMAC_DA2 (GPORT2_BASE + 0x0080) -#define SWITCH_PMAC_VLAN (GPORT2_BASE + 0x0084) -#define SWITCH_PMAC_TX_IPG (GPORT2_BASE + 0x0088) -#define SWITCH_PMAC_RX_IPG (GPORT2_BASE + 0x008C) - diff --git a/package/uboot-ifxmips/files/include/asm-mips/pinstrap.h b/package/uboot-ifxmips/files/include/asm-mips/pinstrap.h deleted file mode 100644 index 1a446fa..0000000 --- a/package/uboot-ifxmips/files/include/asm-mips/pinstrap.h +++ /dev/null @@ -1,12 +0,0 @@ -#define FLASH_STRAP 0x1 -#define MII_0_STRAP 0x2 -#define MII_1_STRAP 0x3 -#define ASC_STRAP 0x4 -#define SFLASH_STRAP 0x5 -#define RESERVE_STRAP 0x6 -#define PRODUCT_TEST_STRAP 0x7 -#define PIN_STRAP_MASK 0x001C0000 -#define PIN_STRAP_SHIFT 18 -#define PIN_STRAP 0xB0100914 -#define SDRAM_WIDTH_MASK 0x400000 -#define SDRAM_WIDTH_SHIFT 22 diff --git a/package/uboot-ifxmips/files/include/boot.h b/package/uboot-ifxmips/files/include/boot.h deleted file mode 100644 index 8f70ebb..0000000 --- a/package/uboot-ifxmips/files/include/boot.h +++ /dev/null @@ -1,86 +0,0 @@ -#ifndef _BOOT_H -#define _BOOT_H - -/* All this should be defined somewhere in danube.h later... */ - -#define MPS_SRAM_BASE_ADDRESS 0xBF200000 -#define MPS_SRAM_BOOT_OFFSET 0x1C0 - -/* Offset for CPU1 (both CPUs have same register set) */ -#define BOOT_BASE_ADDRESS (MPS_SRAM_BASE_ADDRESS + MPS_SRAM_BOOT_OFFSET) -#define BOOT_CPU_OFFSET 0x20 - - -#ifdef __ASSEMBLY__ -#define BOOT_RVEC (BOOT_BASE_ADDRESS + 0x00) -#define BOOT_NVEC (BOOT_BASE_ADDRESS + 0x04) -#define BOOT_EVEC (BOOT_BASE_ADDRESS + 0x08) -#define BOOT_CP0_CAUSE (BOOT_BASE_ADDRESS + 0x0C) -#define BOOT_CP0_EPC (BOOT_BASE_ADDRESS + 0x10) -#define BOOT_CP0_EEPC (BOOT_BASE_ADDRESS + 0x14) -#define BOOT_SIZE (BOOT_BASE_ADDRESS + 0x18) /* for CPU1 */ -#define BOOT_RCU_SR (BOOT_BASE_ADDRESS + 0x18) /* for CPU0 */ -#define BOOT_CFG_STAT (BOOT_BASE_ADDRESS + 0x1C) -#else -#define BOOT_RVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x00) -#define BOOT_NVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x04) -#define BOOT_EVEC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x08) -#define BOOT_CP0_STATUS(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x0C) -#define BOOT_CP0_EPC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x10) -#define BOOT_CP0_EEPC(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x14) -#define BOOT_SIZE(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18) /* for CPU1 */ -#define BOOT_RCU_SR(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x18) /* for CPU0 */ -#define BOOT_CFG_STAT(cpu) (volatile u32*)(BOOT_BASE_ADDRESS + (cpu * BOOT_CPU_OFFSET) + 0x1C) -#endif - -#define BOOT_CFG_NOR 0x01 -#define BOOT_CFG_MII 0x02 -#define BOOT_CFG_PCI 0x03 -#define BOOT_CFG_ASC 0x04 -#define BOOT_CFG_SFLASH 0x05 -#define BOOT_CFG_NAND 0x06 -#define BOOT_CFG_RMII 0x07 -#define BOOT_CFG_TEST 0x00 - -#define BOOT_NUM_RETRY 3 - -#define BOOT_STAT_MASK_ALL 0x0000FFFF -#define BOOT_STAT_MASK_STAT 0x0000F000 -#define BOOT_STAT_MASK_BERR 0x00000F00 -#define BOOT_STAT_MASK_BSTRAP 0x000000F0 -#define BOOT_STAT_MASK_BMODULE 0x0000000F - -#define BOOT_STAT_INIT 0x00000000 -#define BOOT_STAT_BSTRAP 0x00001000 -#define BOOT_STAT_RETRY 0x00002000 -#define BOOT_STAT_START 0x00003000 -#define BOOT_STAT_HALT 0x0000F000 - -#define BOOT_ERR_NO_RVEC 0x00000100 -#define BOOT_ERR_NO_NVEC 0x00000200 -#define BOOT_ERR_NO_EVEC 0x00000300 -#define BOOT_ERR_BSTRAP 0x00000400 -#define BOOT_ERR_EXC 0x00000800 - -#ifndef __ASSEMBLY__ -void boot_set_status( u32 status, u32 mask); -void boot_set_config( u32 config); -void boot_set_rvec( u32 vector); -void boot_set_size( u32 size); -void boot_sdbg( u8* string, u32 value); -void boot_error( u32 berr); -int boot_from_ebu(void); -void _boot_rvec(void); -typedef struct -{ - u32 cpu; /** CPU number */ - u32 config; /** Boot configuration */ - u32 endian; /** CPU endianess */ - u32 debug; /** Debug mode */ - u32 (*exit)(void); /** application vector */ -} boot_data; - -extern boot_data bootrom; -#endif - -#endif /* #ifdef _BOOT_H */ diff --git a/package/uboot-ifxmips/files/include/configs/danube.h b/package/uboot-ifxmips/files/include/configs/danube.h deleted file mode 100644 index cd2d247..0000000 --- a/package/uboot-ifxmips/files/include/configs/danube.h +++ /dev/null @@ -1,273 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * This file contains the configuration parameters for the danube board. - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#define USE_REFERENCE_BOARD -//#define USE_EVALUATION_BOARD - -//#define DANUBE_BOOT_FROM_EBU -#define DANUBE_USE_DDR_RAM - -#ifdef DANUBE_USE_DDR_RAM -//#define DANUBE_DDR_RAM_111M -//#define DANUBE_DDR_RAM_166M -//#define PROMOSDDR400 -//#define DDR_SAMSUNG_166M -#define DDR_PSC_166M -//#define DANUBE_DDR_RAM_133M -#define DANUBE_DDR_RAM_SIZE 32 /* 32M DDR-DRAM for reference board */ -#endif - -#define CONFIG_LZMA 1 /* use LZMA for compression */ - -#define CLK_OUT2_25MHZ -#define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ -#define CONFIG_IFX_MIPS 1 /* in an Infineon chip */ -#define CONFIG_DANUBE 1 /* on a danube Board */ -#define RAM_SIZE 0x2000000 /*32M ram*/ - -#define CPU_CLOCK_RATE 235000000 /* 235 MHz clock for the MIPS core */ - -#define INFINEON_EBU_BOOTCFG 0x688C688C /* CMULT = 8 for 150 MHz */ - -#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ - -#define CONFIG_BAUDRATE 115200 - -#define DEBUG_PARSER 2 - -/* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 300, 9600, 19200, 38400, 57600, 115200 } - -#ifndef CFG_BOOTSTRAP_CODE -#define CONFIG_TIMESTAMP /* Print image info with timestamp */ -#endif - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS -/* by MarsLin 2005/05/10, to support different hardware configuations */ -//#define CONFIG_EXTRA_ENV_SETTINGS <configs/ifx_extra_env.h> -#define CONFIG_EXTRA_ENV_SETTINGS \ - "ethaddr=11:22:33:44:55:66\0" \ - "serverip=192.168.45.100\0" \ - "ipaddr=192.168.45.108\0" \ - "ram_addr=0x80500000\0" \ - "kernel_addr=0xb0030000\0" \ - "flashargs=setenv bootargs rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} init=/etc/preinit\0" \ - "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off\0" \ - "addmisc=setenv bootargs ${bootargs} console=ttyS1,115200 ethaddr=${ethaddr} ${mtdparts}\0" \ - "flash_flash=run flashargs addip addmisc;bootm ${kernel_addr}\0" \ - "flash_nfs=run nfsargs addip addmisc;bootm ${kernel_addr}\0" \ - "net_flash=run load_kernel flashargs addip addmisc;bootm ${ram_addr}\0" \ - "net_nfs=run load_kernel nfsargs addip addmisc;bootm ${ram_addr}\0" \ - "load_kernel=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-uImage\0" \ - "update_uboot=tftp 0x80500000 u-boot.ifx;era 1:0-10; cp.b 0x80500000 0xb0000000 0x10000\0" \ - "update_openwrt=tftp ${ram_addr} ${tftppath}openwrt-ifxmips-squashfs.image; era ${kernel_addr} +${filesize} 0; cp.b ${ram_addr} ${kernel_addr} ${filesize}\0" - -#define CONFIG_BOOTCOMMAND "run flash_flash" - -#define CONFIG_COMMANDS_YES (CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_NET ) - -#define CONFIG_COMMANDS_NO (CFG_CMD_NFS | \ - CFG_CMD_FPGA | \ - CFG_CMD_IMLS | \ - CFG_CMD_ITEST | \ - CFG_CMD_XING | \ - CFG_CMD_IMI | \ - CFG_CMD_BMP | \ - CFG_CMD_BOOTD | \ - CFG_CMD_CONSOLE | \ - CFG_CMD_LOADS | \ - CFG_CMD_LOADB ) - -#define CONFIG_COMMANDS (CONFIG_COMMANDS_YES & ~CONFIG_COMMANDS_NO) - -#if 0 - CFG_CMD_DHCP - CFG_CMD_ELF - CFG_CMD_NAND -#endif - -#include <cmd_confdefs.h> - -/* - * Miscellaneous configurable options - */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "DANUBE # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args*/ - -#define CFG_MALLOC_LEN 128*1024 - -#define CFG_BOOTPARAMS_LEN 128*1024 - -#define CFG_HZ (CPU_CLOCK_RATE / 2) - -#define CFG_LOAD_ADDR 0x80100000 /* default load address */ - -#define CFG_MEMTEST_START 0x80100000 -#define CFG_MEMTEST_END 0x80400000 - -/*----------------------------------------------------------------------- - * FLASH and environment organization - */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT (135) /* max number of sectors on one chip */ - -#define PHYS_FLASH_1 0xB0000000 /* Flash Bank #1 */ -#define PHYS_FLASH_2 0xB4000000 /* Flash Bank #2 */ - -#define BOOTSTRAP_TEXT_BASE 0xb0000000 - -/* The following #defines are needed to get flash environment right */ -#define CFG_MONITOR_BASE UBOOT_RAM_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */ -#define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE /* board/danube/config.mk. = 0xA0800000 */ -#define CFG_MONITOR_LEN (256 << 10) - -#define CFG_INIT_SP_OFFSET 0x400000 - -#define CFG_FLASH_BASE PHYS_FLASH_1 - -/* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (20 * CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (20 * CFG_HZ) /* Timeout for Flash Write */ - -#define CFG_ENV_IS_IN_FLASH 1 -//#define CFG_ENV_IS_NOWHERE 1 -//#define CFG_ENV_IS_IN_NVRAM 1 -/* Address and size of Primary Environment Sector */ -#define CFG_ENV_ADDR 0xB0020000 -#define CFG_ENV_SIZE 0x10000 - -#define CONFIG_FLASH_16BIT - -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_DANUBE_SWITCH -#define CONFIG_NET_MULTI -#define CONFIG_ENV_OVERWRITE - -#define EXCEPTION_BASE 0x200 - -/** - *\brief definition for nand - * - */ -#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define NAND_ChipID_UNKNOWN 0x00 -#define SECTORSIZE 512 -#define NAND_MAX_FLOORS 1 -#define NAND_MAX_CHIPS 1 - - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - - -#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */ -#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */ - -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) -#define NAND_WAIT_READY(nand) -#define WRITE_NAND_COMMAND(d, adr) -#define WRITE_NAND_ADDRESS(d, adr) -#define WRITE_NAND(d, adr) -#define READ_NAND(adr) -/* the following are NOP's in our implementation */ -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) - - - -#define NAND_BASE_ADDRESS 0xB4000000 - -#define NAND_WRITE(addr, val) *((u8*)(NAND_BASE_ADDRESS | (addr))) = val;while((*EBU_NAND_WAIT & 0x08) == 0); -#define NAND_READ(addr, val) val = *((u8*)(NAND_BASE_ADDRESS | (addr))) -#define NAND_CE_SET -#define NAND_CE_CLEAR -#define NAND_READY ( ((*EBU_NAND_WAIT)&0x07) == 7) -#define NAND_READY_CLEAR *EBU_NAND_WAIT = 0; -#define WRITE_CMD 0x18 -#define WRITE_ADDR 0x14 -#define WRITE_LADDR 0x10 -#define WRITE_DATA 0x10 -#define READ_DATA 0x10 -#define READ_LDATA 0x00 -#define ACCESS_WAIT -#define IFX_ATC_NAND 0xc176 -#define IFX_BTC_NAND 0xc166 -#define ST_512WB2_NAND 0x2076 - -#define NAND_OK 0x00000000 /* Bootstrap succesful, start address in BOOT_RVEC */ -#define NAND_ERR 0x80000000 -#define NAND_ACC_TIMEOUT (NAND_ERR | 0x00000001) -#define NAND_ACC_ERR (NAND_ERR | 0x00000002) - - -/***************************************************************************** - * DANUBE - *****************************************************************************/ -/* lock cache for C program stack */ -/* points to ROM */ -/* stack size is 16K */ -#define LOCK_DCACHE_ADDR 0x9FC00000 -#define LOCK_DCACHE_SIZE 0x1000 - -/* - * Memory layout - */ -#define CFG_SDRAM_BASE 0x80000000 -#define CFG_SDRAM_BASE_UNCACHE 0xA0000000 -#define CFG_CACHE_LOCK_SIZE LOCK_DCACHE_SIZE - -/* - * Cache settings - */ -#define CFG_CACHE_SIZE 16384 -#define CFG_CACHE_LINES 32 -#define CFG_CACHE_WAYS 4 -#define CFG_CACHE_SETS 128 - -#define CFG_ICACHE_SIZE CFG_CACHE_SIZE -#define CFG_DCACHE_SIZE CFG_CACHE_SIZE -#define CFG_CACHELINE_SIZE CFG_CACHE_LINES - -#endif /* __CONFIG_H */ diff --git a/package/uboot-ifxmips/files/lib_bootstrap/Makefile b/package/uboot-ifxmips/files/lib_bootstrap/Makefile deleted file mode 100644 index 9dc77df..0000000 --- a/package/uboot-ifxmips/files/lib_bootstrap/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB := $(obj)libbootstrap.a - -OBJS := board.o LzmaDecode.o string.o crc32.o LzmaWrapper.o -CFLAGS += -DCFG_BOOTSTRAP_CODE - -ifeq ($(BOOTSTRAP_PRINTF_STATUS), BOOTSTRAP_PRINTF_ENABLED) -OBJS += time.o console.o ctype.o display_options.o vsprintf.o lists.o devices.o -CFLAGS += -DDEBUG_ENABLE_BOOTSTRAP_PRINTF -endif - -SRCS := $(OBJS:.o=.c) -OBJS := $(addprefix $(obj),$(OBJS)) - -all: $(SRCS) $(obj).depend $(LIB) - -$(LIB): $(obj).depend $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) - -vpath %.c ../common ../lib_generic ../lib_$(CPU) - -board_bootstrap.c: - ln -s ../lib_$(CPU)/board.c $@ - -#LzmaDecode.c LzmaWrapper.c string.c crc32.c: -# ln -s ../lib_generic/$@ $@ - -######################################################################### - -#include $(SRCTREE)/rules.mk -$(obj).depend: $(SRCS) - $(CC) -M $(CFLAGS) $^ > $@ - -sinclude $(obj).depend - -######################################################################### diff --git a/package/uboot-ifxmips/files/lib_generic/LzmaDecode.c b/package/uboot-ifxmips/files/lib_generic/LzmaDecode.c deleted file mode 100644 index 1ce2398..0000000 --- a/package/uboot-ifxmips/files/lib_generic/LzmaDecode.c +++ /dev/null @@ -1,620 +0,0 @@ -/* - LzmaDecode.c - LZMA Decoder (optimized for Speed version) - - LZMA SDK 4.40 Copyright (c) 1999-2006 Igor Pavlov (2006-05-01) - http://www.7-zip.org/ - - LZMA SDK is licensed under two licenses: - 1) GNU Lesser General Public License (GNU LGPL) - 2) Common Public License (CPL) - It means that you can select one of these two licenses and - follow rules of that license. - - SPECIAL EXCEPTION: - Igor Pavlov, as the author of this Code, expressly permits you to - statically or dynamically link your Code (or bind by name) to the - interfaces of this file without subjecting your linked Code to the - terms of the CPL or GNU LGPL. Any modifications or additions - to this file, however, are subject to the LGPL or CPL terms. -*/ - -#include <config.h> -#include <common.h> - -#ifdef CONFIG_LZMA - -#include "LzmaDecode.h" - -#define kNumTopBits 24 -#define kTopValue ((UInt32)1 << kNumTopBits) - -#define kNumBitModelTotalBits 11 -#define kBitModelTotal (1 << kNumBitModelTotalBits) -#define kNumMoveBits 5 - -#define RC_READ_BYTE (*Buffer++) - -#define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ - { int i; for(i = 0; i < 5; i++) { RC_TEST; Code = (Code << 8) | RC_READ_BYTE; }} - -#ifdef _LZMA_IN_CB - -#ifndef CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) \ - { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return result; } \ - BufferLim = Buffer + size; if (size == 0) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } }} -#else //CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) \ - { SizeT size; int result = InCallback->Read(InCallback, &Buffer, &size); if (result != LZMA_RESULT_OK) { return result; } \ - BufferLim = Buffer + size; if (size == 0) { return LZMA_RESULT_DATA_ERROR; } }} -#endif //CFG_BOOTSTRAP_CODE - -#define RC_INIT Buffer = BufferLim = 0; RC_INIT2 - -#else //_LZMA_IN_CB - -#ifndef CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) { printf("ERROR, %s, %d\n", __FILE__, __LINE__); return LZMA_RESULT_DATA_ERROR; } } -#else //CFG_BOOTSTRAP_CODE -#define RC_TEST { if (Buffer == BufferLim) { return LZMA_RESULT_DATA_ERROR; } } -#endif //CFG_BOOTSTRAP_CODE - -#define RC_INIT(buffer, bufferSize) Buffer = buffer; BufferLim = buffer + bufferSize; RC_INIT2 - -#endif //_LZMA_IN_CB - -#define RC_NORMALIZE if (Range < kTopValue) { RC_TEST; Range <<= 8; Code = (Code << 8) | RC_READ_BYTE; } -#define IfBit0(p) RC_NORMALIZE; bound = (Range >> kNumBitModelTotalBits) * *(p); if (Code < bound) -#define UpdateBit0(p) Range = bound; *(p) += (kBitModelTotal - *(p)) >> kNumMoveBits; -#define UpdateBit1(p) Range -= bound; Code -= bound; *(p) -= (*(p)) >> kNumMoveBits; - -#define RC_GET_BIT2(p, mi, A0, A1) IfBit0(p) \ - { UpdateBit0(p); mi <<= 1; A0; } else \ - { UpdateBit1(p); mi = (mi + mi) + 1; A1; } - -#define RC_GET_BIT(p, mi) RC_GET_BIT2(p, mi, ; , ;) - -#define RangeDecoderBitTreeDecode(probs, numLevels, res) \ - { int i = numLevels; res = 1; \ - do { CProb *p = probs + res; RC_GET_BIT(p, res) } while(--i != 0); \ - res -= (1 << numLevels); } - - -#define kNumPosBitsMax 4 -#define kNumPosStatesMax (1 << kNumPosBitsMax) - -#define kLenNumLowBits 3 -#define kLenNumLowSymbols (1 << kLenNumLowBits) -#define kLenNumMidBits 3 -#define kLenNumMidSymbols (1 << kLenNumMidBits) -#define kLenNumHighBits 8 -#define kLenNumHighSymbols (1 << kLenNumHighBits) - -#define LenChoice 0 -#define LenChoice2 (LenChoice + 1) -#define LenLow (LenChoice2 + 1) -#define LenMid (LenLow + (kNumPosStatesMax << kLenNumLowBits)) -#define LenHigh (LenMid + (kNumPosStatesMax << kLenNumMidBits)) -#define kNumLenProbs (LenHigh + kLenNumHighSymbols) - - -#define kNumStates 12 -#define kNumLitStates 7 - -#define kStartPosModelIndex 4 -#define kEndPosModelIndex 14 -#define kNumFullDistances (1 << (kEndPosModelIndex >> 1)) - -#define kNumPosSlotBits 6 -#define kNumLenToPosStates 4 - -#define kNumAlignBits 4 -#define kAlignTableSize (1 << kNumAlignBits) - -#define kMatchMinLen 2 - -#define IsMatch 0 -#define IsRep (IsMatch + (kNumStates << kNumPosBitsMax)) -#define IsRepG0 (IsRep + kNumStates) -#define IsRepG1 (IsRepG0 + kNumStates) -#define IsRepG2 (IsRepG1 + kNumStates) -#define IsRep0Long (IsRepG2 + kNumStates) -#define PosSlot (IsRep0Long + (kNumStates << kNumPosBitsMax)) -#define SpecPos (PosSlot + (kNumLenToPosStates << kNumPosSlotBits)) -#define Align (SpecPos + kNumFullDistances - kEndPosModelIndex) -#define LenCoder (Align + kAlignTableSize) -#define RepLenCoder (LenCoder + kNumLenProbs) -#define Literal (RepLenCoder + kNumLenProbs) - -#if Literal != LZMA_BASE_SIZE -StopCompilingDueBUG -#endif - -int LzmaDecodeProperties(CLzmaProperties *propsRes, const unsigned char *propsData, int size) -{ - unsigned char prop0; - if (size < LZMA_PROPERTIES_SIZE) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - prop0 = propsData[0]; - if (prop0 >= (9 * 5 * 5)) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - { - for (propsRes->pb = 0; prop0 >= (9 * 5); propsRes->pb++, prop0 -= (9 * 5)); - for (propsRes->lp = 0; prop0 >= 9; propsRes->lp++, prop0 -= 9); - propsRes->lc = prop0; - /* - unsigned char remainder = (unsigned char)(prop0 / 9); - propsRes->lc = prop0 % 9; - propsRes->pb = remainder / 5; - propsRes->lp = remainder % 5; - */ - } - - #ifdef _LZMA_OUT_READ - { - int i; - propsRes->DictionarySize = 0; - for (i = 0; i < 4; i++) - propsRes->DictionarySize += (UInt32)(propsData[1 + i]) << (i * 8); - if (propsRes->DictionarySize == 0) - propsRes->DictionarySize = 1; - } - #endif - return LZMA_RESULT_OK; -} - -#define kLzmaStreamWasFinishedId (-1) - -int LzmaDecode(CLzmaDecoderState *vs, - #ifdef _LZMA_IN_CB - ILzmaInCallback *InCallback, - #else - const unsigned char *inStream, SizeT inSize, SizeT *inSizeProcessed, - #endif - unsigned char *outStream, SizeT outSize, SizeT *outSizeProcessed) -{ - CProb *p = vs->Probs; - SizeT nowPos = 0; - Byte previousByte = 0; - UInt32 posStateMask = (1 << (vs->Properties.pb)) - 1; - UInt32 literalPosMask = (1 << (vs->Properties.lp)) - 1; - int lc = vs->Properties.lc; - - #ifdef _LZMA_OUT_READ - - UInt32 Range = vs->Range; - UInt32 Code = vs->Code; - #ifdef _LZMA_IN_CB - const Byte *Buffer = vs->Buffer; - const Byte *BufferLim = vs->BufferLim; - #else - const Byte *Buffer = inStream; - const Byte *BufferLim = inStream + inSize; - #endif - int state = vs->State; - UInt32 rep0 = vs->Reps[0], rep1 = vs->Reps[1], rep2 = vs->Reps[2], rep3 = vs->Reps[3]; - int len = vs->RemainLen; - UInt32 globalPos = vs->GlobalPos; - UInt32 distanceLimit = vs->DistanceLimit; - - Byte *dictionary = vs->Dictionary; - UInt32 dictionarySize = vs->Properties.DictionarySize; - UInt32 dictionaryPos = vs->DictionaryPos; - - Byte tempDictionary[4]; - - #ifndef _LZMA_IN_CB - *inSizeProcessed = 0; - #endif - *outSizeProcessed = 0; - if (len == kLzmaStreamWasFinishedId) - return LZMA_RESULT_OK; - - if (dictionarySize == 0) - { - dictionary = tempDictionary; - dictionarySize = 1; - tempDictionary[0] = vs->TempDictionary[0]; - } - - if (len == kLzmaNeedInitId) - { - { - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); - UInt32 i; - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - rep0 = rep1 = rep2 = rep3 = 1; - state = 0; - globalPos = 0; - distanceLimit = 0; - dictionaryPos = 0; - dictionary[dictionarySize - 1] = 0; - #ifdef _LZMA_IN_CB - RC_INIT; - #else - RC_INIT(inStream, inSize); - #endif - } - len = 0; - } - while(len != 0 && nowPos < outSize) - { - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - outStream[nowPos++] = dictionary[dictionaryPos] = dictionary[pos]; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - len--; - } - if (dictionaryPos == 0) - previousByte = dictionary[dictionarySize - 1]; - else - previousByte = dictionary[dictionaryPos - 1]; - - #else /* if !_LZMA_OUT_READ */ - - int state = 0; - UInt32 rep0 = 1, rep1 = 1, rep2 = 1, rep3 = 1; - int len = 0; - const Byte *Buffer; - const Byte *BufferLim; - UInt32 Range; - UInt32 Code; - - #ifndef _LZMA_IN_CB - *inSizeProcessed = 0; - #endif - *outSizeProcessed = 0; - - { - UInt32 i; - UInt32 numProbs = Literal + ((UInt32)LZMA_LIT_SIZE << (lc + vs->Properties.lp)); - for (i = 0; i < numProbs; i++) - p[i] = kBitModelTotal >> 1; - } - - #ifdef _LZMA_IN_CB - RC_INIT; - #else - RC_INIT(inStream, inSize); - #endif - - #endif /* _LZMA_OUT_READ */ - - while(nowPos < outSize) - { - CProb *prob; - UInt32 bound; - int posState = (int)( - (nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - & posStateMask); - - prob = p + IsMatch + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - int symbol = 1; - UpdateBit0(prob) - prob = p + Literal + (LZMA_LIT_SIZE * - ((( - (nowPos - #ifdef _LZMA_OUT_READ - + globalPos - #endif - ) - & literalPosMask) << lc) + (previousByte >> (8 - lc)))); - - if (state >= kNumLitStates) - { - int matchByte; - #ifdef _LZMA_OUT_READ - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - matchByte = dictionary[pos]; - #else - matchByte = outStream[nowPos - rep0]; - #endif - do - { - int bit; - CProb *probLit; - matchByte <<= 1; - bit = (matchByte & 0x100); - probLit = prob + 0x100 + bit + symbol; - RC_GET_BIT2(probLit, symbol, if (bit != 0) break, if (bit == 0) break) - } - while (symbol < 0x100); - } - while (symbol < 0x100) - { - CProb *probLit = prob + symbol; - RC_GET_BIT(probLit, symbol) - } - previousByte = (Byte)symbol; - - outStream[nowPos++] = previousByte; - #ifdef _LZMA_OUT_READ - if (distanceLimit < dictionarySize) - distanceLimit++; - - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #endif - if (state < 4) state = 0; - else if (state < 10) state -= 3; - else state -= 6; - } - else - { - UpdateBit1(prob); - prob = p + IsRep + state; - IfBit0(prob) - { - UpdateBit0(prob); - rep3 = rep2; - rep2 = rep1; - rep1 = rep0; - state = state < kNumLitStates ? 0 : 3; - prob = p + LenCoder; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG0 + state; - IfBit0(prob) - { - UpdateBit0(prob); - prob = p + IsRep0Long + (state << kNumPosBitsMax) + posState; - IfBit0(prob) - { - #ifdef _LZMA_OUT_READ - UInt32 pos; - #endif - UpdateBit0(prob); - - #ifdef _LZMA_OUT_READ - if (distanceLimit == 0) - #else - if (nowPos == 0) - #endif - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - state = state < kNumLitStates ? 9 : 11; - #ifdef _LZMA_OUT_READ - pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - previousByte = dictionary[pos]; - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #else - previousByte = outStream[nowPos - rep0]; - #endif - outStream[nowPos++] = previousByte; - #ifdef _LZMA_OUT_READ - if (distanceLimit < dictionarySize) - distanceLimit++; - #endif - - continue; - } - else - { - UpdateBit1(prob); - } - } - else - { - UInt32 distance; - UpdateBit1(prob); - prob = p + IsRepG1 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep1; - } - else - { - UpdateBit1(prob); - prob = p + IsRepG2 + state; - IfBit0(prob) - { - UpdateBit0(prob); - distance = rep2; - } - else - { - UpdateBit1(prob); - distance = rep3; - rep3 = rep2; - } - rep2 = rep1; - } - rep1 = rep0; - rep0 = distance; - } - state = state < kNumLitStates ? 8 : 11; - prob = p + RepLenCoder; - } - { - int numBits, offset; - CProb *probLen = prob + LenChoice; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenLow + (posState << kLenNumLowBits); - offset = 0; - numBits = kLenNumLowBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenChoice2; - IfBit0(probLen) - { - UpdateBit0(probLen); - probLen = prob + LenMid + (posState << kLenNumMidBits); - offset = kLenNumLowSymbols; - numBits = kLenNumMidBits; - } - else - { - UpdateBit1(probLen); - probLen = prob + LenHigh; - offset = kLenNumLowSymbols + kLenNumMidSymbols; - numBits = kLenNumHighBits; - } - } - RangeDecoderBitTreeDecode(probLen, numBits, len); - len += offset; - } - - if (state < 4) - { - int posSlot; - state += kNumLitStates; - prob = p + PosSlot + - ((len < kNumLenToPosStates ? len : kNumLenToPosStates - 1) << - kNumPosSlotBits); - RangeDecoderBitTreeDecode(prob, kNumPosSlotBits, posSlot); - if (posSlot >= kStartPosModelIndex) - { - int numDirectBits = ((posSlot >> 1) - 1); - rep0 = (2 | ((UInt32)posSlot & 1)); - if (posSlot < kEndPosModelIndex) - { - rep0 <<= numDirectBits; - prob = p + SpecPos + rep0 - posSlot - 1; - } - else - { - numDirectBits -= kNumAlignBits; - do - { - RC_NORMALIZE - Range >>= 1; - rep0 <<= 1; - if (Code >= Range) - { - Code -= Range; - rep0 |= 1; - } - } - while (--numDirectBits != 0); - prob = p + Align; - rep0 <<= kNumAlignBits; - numDirectBits = kNumAlignBits; - } - { - int i = 1; - int mi = 1; - do - { - CProb *prob3 = prob + mi; - RC_GET_BIT2(prob3, mi, ; , rep0 |= i); - i <<= 1; - } - while(--numDirectBits != 0); - } - } - else - rep0 = posSlot; - if (++rep0 == (UInt32)(0)) - { - /* it's for stream version */ - len = kLzmaStreamWasFinishedId; - break; - } - } - - len += kMatchMinLen; - #ifdef _LZMA_OUT_READ - if (rep0 > distanceLimit) - #else - if (rep0 > nowPos) - #endif - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("ERROR: %s, %d\n", __FILE__, __LINE__); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - #ifdef _LZMA_OUT_READ - if (dictionarySize - distanceLimit > (UInt32)len) - distanceLimit += len; - else - distanceLimit = dictionarySize; - #endif - - do - { - #ifdef _LZMA_OUT_READ - UInt32 pos = dictionaryPos - rep0; - if (pos >= dictionarySize) - pos += dictionarySize; - previousByte = dictionary[pos]; - dictionary[dictionaryPos] = previousByte; - if (++dictionaryPos == dictionarySize) - dictionaryPos = 0; - #else - previousByte = outStream[nowPos - rep0]; - #endif - len--; - outStream[nowPos++] = previousByte; - } - while(len != 0 && nowPos < outSize); - } - } - RC_NORMALIZE; - - #ifdef _LZMA_OUT_READ - vs->Range = Range; - vs->Code = Code; - vs->DictionaryPos = dictionaryPos; - vs->GlobalPos = globalPos + (UInt32)nowPos; - vs->DistanceLimit = distanceLimit; - vs->Reps[0] = rep0; - vs->Reps[1] = rep1; - vs->Reps[2] = rep2; - vs->Reps[3] = rep3; - vs->State = state; - vs->RemainLen = len; - vs->TempDictionary[0] = tempDictionary[0]; - #endif - - #ifdef _LZMA_IN_CB - vs->Buffer = Buffer; - vs->BufferLim = BufferLim; - #else - *inSizeProcessed = (SizeT)(Buffer - inStream); - #endif - *outSizeProcessed = nowPos; - return LZMA_RESULT_OK; -} - -#endif /* CONFIG_LZMA */ diff --git a/package/uboot-ifxmips/files/lib_generic/LzmaWrapper.c b/package/uboot-ifxmips/files/lib_generic/LzmaWrapper.c deleted file mode 100644 index 1ee5c12..0000000 --- a/package/uboot-ifxmips/files/lib_generic/LzmaWrapper.c +++ /dev/null @@ -1,220 +0,0 @@ -/****************************************************************************** -** -** FILE NAME : LzmaWrapper.c -** PROJECT : bootloader -** MODULES : U-boot -** -** DATE : 2 Nov 2006 -** AUTHOR : Lin Mars -** DESCRIPTION : LZMA decoder support for U-boot 1.1.5 -** COPYRIGHT : Copyright (c) 2006 -** Infineon Technologies AG -** Am Campeon 1-12, 85579 Neubiberg, Germany -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** HISTORY -** $Date $Author $Comment -** 2 Nov 2006 Lin Mars init version which derived from LzmaTest.c from -** LZMA v4.43 SDK -** 24 May 2007 Lin Mars Fix issue for multiple lzma_inflate involved -*******************************************************************************/ -#define LZMA_NO_STDIO -#ifndef LZMA_NO_STDIO -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#endif - -#include <config.h> -#include <common.h> -#include <linux/types.h> -#include <linux/string.h> -#include <linux/ctype.h> -#include <malloc.h> - -#ifdef CONFIG_LZMA - -#include "LzmaDecode.h" -#include "LzmaWrapper.h" - -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) -static const char *kCantReadMessage = "Can not read from source buffer"; -static const char *kCantAllocateMessage = "Not enough buffer for decompression"; -#endif - -static size_t rpos=0, dpos=0; - -static int MyReadFileAndCheck(unsigned char *src, void *dest, size_t size) -{ - if (size == 0) - return 0; - memcpy(dest, src + rpos, size); - rpos += size; - return 1; -} - -int lzma_inflate(unsigned char *source, int s_len, unsigned char *dest, int *d_len) -{ - /* We use two 32-bit integers to construct 64-bit integer for file size. - You can remove outSizeHigh, if you don't need >= 4GB supporting, - or you can use UInt64 outSize, if your compiler supports 64-bit integers*/ - UInt32 outSize = 0; - UInt32 outSizeHigh = 0; - SizeT outSizeFull; - unsigned char *outStream; - - int waitEOS = 1; - /* waitEOS = 1, if there is no uncompressed size in headers, - so decoder will wait EOS (End of Stream Marker) in compressed stream */ - - SizeT compressedSize; - unsigned char *inStream; - - CLzmaDecoderState state; /* it's about 24-80 bytes structure, if int is 32-bit */ - unsigned char properties[LZMA_PROPERTIES_SIZE]; - - int res; - - rpos=0; dpos=0; - - if (sizeof(UInt32) < 4) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("LZMA decoder needs correct UInt32\n"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - { - long length=s_len; - if ((long)(SizeT)length != length) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Too big compressed stream\n"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - compressedSize = (SizeT)(length - (LZMA_PROPERTIES_SIZE + 8)); - } - - /* Read LZMA properties for compressed stream */ - - if (!MyReadFileAndCheck(source, properties, sizeof(properties))) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("%s\n", kCantReadMessage); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - /* Read uncompressed size */ - { - int i; - for (i = 0; i < 8; i++) - { - unsigned char b; - if (!MyReadFileAndCheck(source, &b, 1)) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("%s\n", kCantReadMessage); -#endif - return LZMA_RESULT_DATA_ERROR; - } - if (b != 0xFF) - waitEOS = 0; - if (i < 4) - outSize += (UInt32)(b) << (i * 8); - else - outSizeHigh += (UInt32)(b) << ((i - 4) * 8); - } - - if (waitEOS) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Stream with EOS marker is not supported"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - outSizeFull = (SizeT)outSize; - if (sizeof(SizeT) >= 8) - outSizeFull |= (((SizeT)outSizeHigh << 16) << 16); - else if (outSizeHigh != 0 || (UInt32)(SizeT)outSize != outSize) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Too big uncompressed stream"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - } - - /* Decode LZMA properties and allocate memory */ - if (LzmaDecodeProperties(&state.Properties, properties, LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("Incorrect stream properties"); -#endif - return LZMA_RESULT_DATA_ERROR; - } - state.Probs = (CProb *)malloc(LzmaGetNumProbs(&state.Properties) * sizeof(CProb)); - - if (outSizeFull == 0) - outStream = 0; - else - { - if (outSizeFull > d_len) - outStream = 0; - else - outStream = dest; - } - - if (compressedSize == 0) - inStream = 0; - else - { - if ((compressedSize+rpos) > s_len ) - inStream = 0; - else - inStream = source + rpos; - } - - if (state.Probs == 0 - || (outStream == 0 && outSizeFull != 0) - || (inStream == 0 && compressedSize != 0) - ) - { - free(state.Probs); -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("%s\n", kCantAllocateMessage); -#endif - return LZMA_RESULT_DATA_ERROR; - } - - /* Decompress */ - { - SizeT inProcessed; - SizeT outProcessed; - res = LzmaDecode(&state, - inStream, compressedSize, &inProcessed, - outStream, outSizeFull, &outProcessed); - if (res != 0) - { -#if defined(DEBUG_ENABLE_BOOTSTRAP_PRINTF) || !defined(CFG_BOOTSTRAP_CODE) - printf("\nDecoding error = %d\n", res); -#endif - res = 1; - } - else - { - *d_len = outProcessed; - } - } - - free(state.Probs); - return res; -} - -#endif /* CONFIG_LZMA */ diff --git a/package/uboot-ifxmips/files/net/ifx_eth.c b/package/uboot-ifxmips/files/net/ifx_eth.c deleted file mode 100644 index 02e72ae..0000000 --- a/package/uboot-ifxmips/files/net/ifx_eth.c +++ /dev/null @@ -1,4 +0,0 @@ - -#define IFX_ETH_INITIALIZE_EXTERN extern int danube_switch_initialize(bd_t *); -#define IFX_ETH_INITIALIZE(bd_t) danube_switch_initialize(bd_t); - |