diff options
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/102-MIPS-ath79-fix-regression-in-PCI-window-initializati.patch')
| -rw-r--r-- | target/linux/ar71xx/patches-4.4/102-MIPS-ath79-fix-regression-in-PCI-window-initializati.patch | 37 |
1 files changed, 0 insertions, 37 deletions
diff --git a/target/linux/ar71xx/patches-4.4/102-MIPS-ath79-fix-regression-in-PCI-window-initializati.patch b/target/linux/ar71xx/patches-4.4/102-MIPS-ath79-fix-regression-in-PCI-window-initializati.patch deleted file mode 100644 index e5226a5..0000000 --- a/target/linux/ar71xx/patches-4.4/102-MIPS-ath79-fix-regression-in-PCI-window-initializati.patch +++ /dev/null @@ -1,37 +0,0 @@ -From: Felix Fietkau <nbd@nbd.name> -Date: Sun, 15 May 2016 13:09:20 +0200 -Subject: [PATCH] MIPS: ath79: fix regression in PCI window initialization - -ath79_ddr_pci_win_base has the type void __iomem *, so register offsets -need to be a multiple of 4. - -Cc: Alban Bedel <albeu@free.fr> -Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface") -Signed-off-by: Felix Fietkau <nbd@nbd.name> ---- - ---- a/arch/mips/ath79/common.c -+++ b/arch/mips/ath79/common.c -@@ -76,14 +76,14 @@ void ath79_ddr_set_pci_windows(void) - { - BUG_ON(!ath79_ddr_pci_win_base); - -- __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0); -- __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 1); -- __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 2); -- __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 3); -- __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 4); -- __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 5); -- __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 6); -- __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 7); -+ __raw_writel(AR71XX_PCI_WIN0_OFFS, ath79_ddr_pci_win_base + 0x0); -+ __raw_writel(AR71XX_PCI_WIN1_OFFS, ath79_ddr_pci_win_base + 0x4); -+ __raw_writel(AR71XX_PCI_WIN2_OFFS, ath79_ddr_pci_win_base + 0x8); -+ __raw_writel(AR71XX_PCI_WIN3_OFFS, ath79_ddr_pci_win_base + 0xc); -+ __raw_writel(AR71XX_PCI_WIN4_OFFS, ath79_ddr_pci_win_base + 0x10); -+ __raw_writel(AR71XX_PCI_WIN5_OFFS, ath79_ddr_pci_win_base + 0x14); -+ __raw_writel(AR71XX_PCI_WIN6_OFFS, ath79_ddr_pci_win_base + 0x18); -+ __raw_writel(AR71XX_PCI_WIN7_OFFS, ath79_ddr_pci_win_base + 0x1c); - } - EXPORT_SYMBOL_GPL(ath79_ddr_set_pci_windows); - |